JPH04354368A - Semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory device which is highly resistant to oxidation, heat and chemicals and is provided with a lower capacitor electrode which enables highly selective etching to a layer insulating film which becomes a foundation and a manufacture method thereof. CONSTITUTION:A contact hole 25b is provided to a layer insulating film 30 covering all over a semiconductor substrate 21 and a polysilicon layer containing impurities is deposited thereon to nitrify a surface thereof directly. Thereby, a lower capacitor electrode 27 having a directly nitrified silicon film 27a on a surface is formed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly to a one-transistor, one-capacitor type semiconductor memory device (hereinafter also referred to as a ferroelectric memory cell) having a capacitor using a ferroelectric film; The present invention relates to a manufacturing method thereof.

0002

[Prior Art] Figures 5 and 6 are from ``1989 IEE International Solid State Circuits Conference; Digest of Technical Papers 242''.
~243 pages” (1989 International
l Solid-State Circuits Co.
nference; Digest of Techn.
ical Papers pp. 242-243)
2 is a schematic cross-sectional process diagram for explaining the manufacturing process of the conventional ferroelectric memory cell shown in FIG.
3 is a gate oxide film, 4 is a word line serving as a gate electrode, and 5 is a gate oxide film.
5a is the source/drain region, 5a is the contact hole, and 6 is the source/drain region.
is a first interlayer insulating film, 7 is a lower capacitor electrode, 8 is a capacitor dielectric film, 9 is an upper capacitor electrode, 9a is a contact hole, 10 is a second interlayer insulating film, 11 is a bit line, and 12 is a wiring. be.

Next, a method of manufacturing this conventional device will be explained with reference to these figures. First, as shown in FIG. 5(a), a field oxide film 2 for element region isolation is formed on a silicon semiconductor substrate 1.

Next, a gate oxide film 3 is formed by thermal oxidation on the silicon semiconductor substrate 1 in a region other than the region where the field oxide film 2 is formed, and a gate oxide film 3 is formed on the gate insulating film 3 as shown in FIG. 5(b).
A word line 4 serving as a gate electrode is formed as shown in FIG. This word line 4 can be formed by depositing a polysilicon layer containing impurities to make it conductive by LPCVD (low pressure chemical vapor deposition) and patterning it by photolithography.

Using such gate electrode 4 and field oxide film 2 as a mask, source/drain regions 5 are self-aligned on both sides of the channel region under gate electrode 4 by ion implantation as shown in FIG. 5(c). to form. Thereafter, a first interlayer insulating film 6 covering the gate electrode 4 and source/drain regions 5 is formed as shown in FIG. 5(d).

A lower capacitor electrode 7 is formed above the gate electrode 4 on the interlayer insulating film 6. Here, the lower capacitor electrode 7 can be formed by depositing a conductive layer on the interlayer insulating film 6 by sputtering or the like, and patterning the conductive layer. Thereafter, a ferroelectric film is deposited by a sputtering method or a sol-gel method so as to cover the lower capacitor electrode 7, and is patterned after an appropriate heat treatment to form a capacitor dielectric film 8 as shown in FIG. 6(a). Form. Next, an upper capacitor electrode 9 is formed on this capacitor dielectric film 8 by sputtering and photolithography, and a second interlayer insulating film 10 is further formed on the entire surface so as to cover it (FIG. 6(b)).
).

Contact holes 5a and 9a are formed in interlayer insulating films 6 and 1, respectively, to enable electrical connection with the source/drain region 5 and upper capacitor electrode 9.
A hole is made using a photolithography technique so as to penetrate through the hole (FIG. 6(c)).

Thereafter, as shown in FIG. 6(d), a bit line 11 connected to one side of the source/drain region 5 and a wiring 12 connected between the other side of the source/drain region 5 and the upper capacitor electrode 9 are formed. do. These bit lines 11
The wiring 12 can be formed by depositing and patterning a conductive layer so as to cover the second interlayer insulating film 10 and the contact holes 5a and 9a. Finally, a surface protection film (not shown) is applied to complete the ferroelectric memory cell. FIG. 7 shows the top surface pattern of the ferroelectric memory cell completed in FIG. 6(d).
corresponds to a cross section along line IVd-IVd in FIG.

By the way, as a ferroelectric material constituting the capacitor dielectric film 8 of the ferroelectric memory having such a structure, a material called PZT, which has high insulating properties, is used. PZT is ABO3 = Pb(Tix Zr1-x)O
It is represented by the chemical formula 3. That is, atom A corresponds to Pb, atom B is represented by Ti or Zr, and atom O represents oxygen. PZT can be produced by sputtering method, sol-gel method, C
Although the film is formed by a VD method or the like, there are many vacancies of oxygen atoms immediately after deposition. Oxygen atom vacancies are defects in PZT crystals, and are known to contribute to Frenkel-type electrical conduction. In other words, the more oxygen vacancies there are, the better the electrical conductivity and the greater the leakage current. To improve this point, after forming the PZT film, an oxygen-containing atmosphere is usually used.
Heat treatment is performed at about 50°C to 700°C for about 30 minutes to 1 hour. During this heat treatment, oxygen reaches the surface of the lower capacitor electrode 7 through the PZT film and oxidizes the surface. In addition, it is possible that the lower capacitor electrode and PZT may undergo a chemical reaction or an alloy reaction due to thermal energy of about 700°C, so the lower capacitor electrode 7 is generally made of a chemically stable and highly oxidation-resistant rare metal. Pt (platinum) is often used. The lattice constant of Pt is about 4 angstroms, which is close to the lattice constant of PZT and has the advantage of good interfacial matching. However, Pt is an interlayer insulating film 6 (SiO2
), Ti is used as the buffer layer, and the lower capacitor electrode 7 is a composite film of Pt/Ti.

[0010] Here, since Pt is chemically stable,
Removal methods using chemical reactions are difficult to use. For this purpose, Pt
An ion milling method using Ar ions is used for etching. Ar ion milling is an etching method that utilizes the physical sputtering phenomenon of Ar, and since it has little selectivity for the lower capacitor electrode 7 and the interlayer insulating film 6, the interlayer insulating film is removed when the lower capacitor electrode 7 is patterned. The film 1 will also be scraped off to some extent. Therefore, for a capacitor containing a ferroelectric material, a ferroelectric film is formed on the lower capacitor electrode 7, which has excellent oxidation resistance, heat resistance, and chemical resistance, and can be etched with high selectivity with respect to the underlying interlayer insulating film 6. 8 is desired to be formed.

[0011]

The conventional semiconductor memory device is constructed as described above, and Pt or Pt/Ti is used for the lower capacitor electrode 7 of the capacitor including the ferroelectric film. Since the end point cannot be detected when forming the lower capacitor electrode 7 pattern, variations in processing accuracy occur.In other words, the interlayer insulating film 6 is scraped away and its thickness is locally thinned, resulting in poor long-term reliability due to deterioration of the interlayer dielectric strength voltage. There have been problems in that process instability occurs, such as a decrease in Pt or an intralayer short circuit caused by etching residue of Pt.

The present invention has been made to solve the above-mentioned problems, and has excellent oxidation resistance, heat resistance, and chemical resistance, and can detect the end point during etching processing, and is suitable for use with the underlying interlayer insulating film. It is an object of the present invention to provide a ferroelectric type semiconductor memory device including a lower capacitor electrode having sufficient selectivity during etching between the ferroelectric semiconductor memory device and a method for manufacturing the same.

[0013]

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes one field effect transistor and one capacitor, and includes a semiconductor substrate and a channel region on one main surface of the semiconductor substrate. A source/drain region formed on both sides, a word line formed on the channel region via a first gate insulating film, and a word line formed on the main surface and electrically connected to one of the source/drain regions. a first interlayer insulating film covering the word line and the bit line; and a first interlayer insulating film formed on the first interlayer insulating film and electrically connected to the other of the source/drain regions. a lower capacitor electrode, a silicon direct nitride film formed on the lower capacitor electrode, a ferroelectric film formed on the silicon direct nitride film, and an upper capacitor electrode formed on the ferroelectric film. It is equipped with a capacitor electrode.

Further, the method for manufacturing a semiconductor memory device according to the present invention includes depositing a polysilicon layer on an interlayer insulating film to form a lower electrode of a capacitor, and then forming a nitride film directly on the surface of the lower electrode of the capacitor. A ferroelectric film is formed directly on the nitride film, and after this is heated and annealed, a third conductive layer is deposited on the ferroelectric film to form an upper electrode of the capacitor. This is how it was done.

[0015]

In the semiconductor memory device of the present invention, since the lower capacitor electrode has a polysilicon electrode structure having a silicon direct nitride film on the surface, a highly reliable capacitor structure can be realized.

Furthermore, in the method for manufacturing a semiconductor memory device according to the present invention, the nitride film is directly formed on the surface of the lower capacitor electrode formed on the interlayer insulating film, so that the oxidation of the lower capacitor electrode is prevented during heat treatment of the ferroelectric film. In addition, it is possible to perform highly selective etching with respect to the interlayer insulating film, and a highly reliable capacitor structure can be obtained without causing instability in the process.

[0017]

Embodiment FIGS. 1 to 3 are schematic cross-sectional process diagrams for explaining the manufacturing process of a semiconductor memory device according to an embodiment of the present invention. In the figures, 21 is a silicon semiconductor substrate, 22 is an element. Field oxide film for area isolation, 2
3 is a gate insulating film, 24 is a word line serving as a gate electrode,
25 is a source/drain region, 25a and 25b are contact holes, 26 and 26a are insulating films, 27 is a lower capacitor electrode, 27a is a silicon nitride film, 28 is a ferroelectric film,
29 is an upper capacitor film, 30 is a first interlayer insulating film, 31
is a bit line, 33 is a second interlayer insulating film, 34 is a wiring layer,
40 is an insulating film.

Next, a method of manufacturing a semiconductor device according to this embodiment will be explained with reference to these figures. First, a field oxide film 22 for element region isolation and a gate insulating film 23 are formed on a silicon semiconductor substrate 21 by a thermal oxidation method or the like. A polysilicon layer containing impurities is deposited on the gate insulating film 23 by the LPCVD method so as to have conductivity.
An insulating film 26 such as a silicon oxide film is deposited on the polysilicon layer by the CVD method and patterned by photolithography, so that the upper surface is covered with the insulating film 26 as shown in FIG. 1(a). A gate electrode 24 is formed. This gate electrode 24 can also be formed of polycide such as WSi2, MoSi2, TiSi2, etc. or high melting point metal such as W, Mo, Ti, Ta, etc. instead of polysilicon. Furthermore, the side walls of the gate electrode 24 are covered with an insulating film 26a in a self-aligned manner by etching the deposited silicon oxide film from above anisotropically, as shown in FIG. 1(b).

Gate electrode 24 and field oxide film 22
Figure 1(c)
The source/drain regions 25 are formed in a self-aligned manner as shown in FIG.

In order to enable electrical connection with one of the source/drain regions 25, a contact hole 25a is opened by photolithography, and the contact hole 25a is connected to one of the source/drain regions through this contact hole 25a. LPCVD a polysilicon layer containing impurities.
An insulating film 4, such as a silicon oxide film, is deposited by
By depositing 0 by CVD and patterning by photolithography, a bit line 31 whose upper surface is covered with an insulating film 40 is formed as shown in FIG. 1(d). The bit line 31 is formed by photolithography by forming a barrier metal layer such as polysilicon, polycide, TiN, TiW, WSi2, TiSi2, etc. on the bottom surface, and then depositing a conductive layer of a high melting point metal such as W, Ti, Mo, Ta, etc. It can also be formed by patterning. Then bit line 31
A first interlayer insulating film 30 is deposited over the entire surface so as to cover (FIG. 2(a)).

In order to enable electrical connection with the other source/drain region 25, another contact hole 25b is formed through the first interlayer insulating film 30 using photolithography (see FIG. 2(b)). The source/drain region 2 is connected through this contact hole 25b.
A polysilicon layer containing an impurity is deposited by the LPCVD method so as to be connected to the other side of the polysilicon layer 5. This polysilicon layer becomes the lower capacitor electrode 27. Thereafter, the polysilicon layer 27 is heated to a temperature of 800 to
A silicon nitride film 27a having a thickness of about 10 angstroms is formed on the surface of the polysilicon layer 27 as shown in FIG. 2(c) by direct nitriding using lamp annealing at 1100 DEG C. for about 30 to 300 seconds. Alternatively, a silicon oxynitride film or a silicon nitride film may be formed by directly nitriding the natural oxide film on the surface of the polysilicon layer 27 using the same method.

Subsequently, a ferroelectric film 28 is deposited on the lower capacitor electrode layer 27 made of polysilicon having a silicon nitride film 27a on its surface, and heated at 500° C. to 80° C. in an oxygen atmosphere.
Annealing is performed in a temperature range of 00° C. for a period of about 10 minutes to 3 hours. At this time, lower capacitor electrode 2
The extremely thin silicon nitride film 27a on the surface of the polysilicon 7 serves as an oxidation prevention mask for the polysilicon. This silicon nitride film 27a also functions as a barrier layer to prevent reaction between polysilicon and ferroelectric film 28.

Further, an upper capacitor electrode 29 is deposited on the ferroelectric film 28, and these lower capacitor electrodes 27
, the ferroelectric film 28, and the upper capacitor electrode 29 are patterned all at once by photolithography to form the lower capacitor electrode 27, as shown in FIG. 2(d).
A capacitor including a ferroelectric film 28 and an upper capacitor electrode 29 is formed. Note that as the material for the upper capacitor electrode 29, for example, Pt, V, Ta, W, Mo, Al, Cu, etc. may be deposited.

After covering this capacitor with a second interlayer insulating film 33, a contact hole 29a is opened to enable electrical connection with the upper capacitor electrode 29 (FIG. 3).
(a)) Finally, a conductive layer such as Al, W, W silicide or Cu is deposited so as to cover the second interlayer insulating film 33 and the contact hole 29a, and patterned by photolithography to form a wiring layer. form 34. At this time, a barrier metal layer such as TiN or TiW may be provided between the wiring layer 34 and the upper capacitor electrode 29. Further, a surface protective film may be formed on the wiring layer 34, or a multilayer wiring structure may be further formed instead. FIG. 4 shows the top surface pattern of the ferroelectric memory cell in FIG. 3(b), and FIG. 3(b) shows the line IIIb-II in FIG.
This corresponds to a cross-sectional view along Ib.

In this embodiment, as described above, the interlayer insulating film 3
A polysilicon layer containing impurities was deposited on the silicon nitride film 27a, and its surface was directly nitrided to form the lower capacitor electrode 27 having the silicon nitride film 27a.
a functions as an oxidation prevention mask and a barrier layer to prevent oxidation, alloying, etc. of the lower capacitor electrode 27, and the lower capacitor electrode 27 is etched between layers using plasma etching technology commonly used in LSI processes. Since the insulating film 30 can be patterned with good selectivity, a highly reliable capacitor structure can be realized.

In the above embodiment, the lower capacitor electrode 27, the ferroelectric film 28, and the upper capacitor electrode 29 constituting the capacitor are all laminated and then patterned at once. The dielectric film 28 or the ferroelectric film 28 and the upper capacitor electrode 29 may be combined and patterned at the same time, or each layer may be patterned individually as in the conventional method. It can be performed.

[0027]

As described above, according to the present invention, since the lower capacitor electrode has a polysilicon electrode structure having a silicon direct nitride film on the surface, a semiconductor memory device having a highly reliable capacitor structure can be obtained. It has the effect of

Further, according to the present invention as described above, since the silicon nitride film is directly formed on the surface of the lower capacitor electrode formed on the interlayer insulating film, the oxidation of the lower capacitor electrode is prevented during heat treatment of the ferroelectric film. etc. can be prevented, and
Etching with high selectivity for the interlayer insulating film becomes possible, and a highly reliable capacitor structure can be formed without causing instability in the process.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional process diagram for explaining a manufacturing process of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional process diagram for explaining a manufacturing process of a semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional process diagram for explaining a manufacturing process of a semiconductor memory device according to an embodiment of the present invention.

FIG. 4 is a top view of a semiconductor memory device according to an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional process diagram for explaining the manufacturing process of a conventional semiconductor memory device.

FIG. 6 is a schematic cross-sectional process diagram for explaining the manufacturing process of a conventional semiconductor memory device.

FIG. 7 is a top view of a conventional semiconductor memory device.

[Explanation of symbols]

21 Semiconductor substrate 22 Field oxide film for element region isolation 23 Gate insulating film 24 Word line 25 Source/drain regions 25a, 25b Contact holes 26, 26a Insulating film 27 Lower capacitor electrode 27a Silicon nitride film 28 Ferroelectric film 29 Upper capacitor electrode 30 interlayer insulating film 31 bit line 33 interlayer insulating film 34 wiring layer 40 insulating film

Claims (2)

[Claims] 1. A semiconductor memory device having one field effect transistor and one capacitor, comprising: a semiconductor substrate; source/drain regions formed on one main surface of the semiconductor substrate with a channel region in between; a word line formed on the channel region via a first gate insulating film; a bit line formed on the main surface and electrically connected to one of the source/drain regions; a first interlayer insulating film formed to cover the line and the bit line, and a lower capacitor electrode formed on the first interlayer insulating film and electrically connected to the other of the source/drain regions. a silicon direct nitride film formed on the lower capacitor electrode, a ferroelectric film formed on the silicon direct nitride film, and an upper capacitor electrode formed on the ferroelectric film. A semiconductor memory device characterized by: 2. In a method of manufacturing a semiconductor memory device having one field effect transistor and one capacitor, a gate electrode is formed on one main surface of a semiconductor substrate of a first conductivity type via a first insulating film. forming a pair of impurity regions in the semiconductor substrate by ion-implanting a second conductivity type impurity using the gate electrode as a mask; and connecting one of the pair of impurity regions to at least the gate electrode. a step of forming a first wiring layer extending above the electrode; a step of covering the entire surface of the semiconductor substrate with an insulating film, and then providing an opening through which the other of the pair of impurity regions is exposed; Depositing a second conductive layer on the entire surface of the semiconductor substrate to form a lower electrode of the capacitor connected to the other of the pair of impurity regions, and forming a nitride film directly on the surface of the lower electrode of the capacitor. forming a ferroelectric film directly on the nitride film; heating and annealing the ferroelectric film; and depositing a third conductive layer on the ferroelectric film. . A method of manufacturing a semiconductor memory device, comprising: forming an upper electrode of the capacitor.