JPH0435308A - Differential amplifier with variable gain - Google Patents

Abstract

PURPOSE:To adjust the gain to a desired gain and to obtain an optimum gain and frequency band by applying a control voltage generate based on a saturated internal voltage drop to gates of 1s and 2nd load transistors (TRs). CONSTITUTION:A current flows to TRs Q4A, Q4B in differential pair form a power supply VDD via P-channel TRs Q3A, Q3B and a current In flows from a source to other power supply Vss via current source TRs Q5A, Q5B. Moreover, a control voltage or a reference voltage E generated by TRs Q2A, Q2B and a current source TR Q6 is applied to gates of load TRs Q1A, Q1B to offer a desired load resistor. Thus, the gain AV is decided by a current ratio IN/IP, which is set to an optional desired ratio depending on the ratio of gm of the TRs, that is, the size and shape.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a gain-adjustable differential amplifier, and particularly to a differential amplifier whose gain and frequency characteristics can be set to optimal values depending on the application. Regarding the technology.

[Prior Art] Generally, it is said that it is difficult to adjust the gain of a differential amplifier itself to a predetermined value, and usually a feedback circuit or the like is connected to the differential amplifier to obtain the desired gain and frequency characteristics. Either they are realized, or they are selectively used that have the desired gain.

For this reason, conventionally, for example, US Patent No. 4.881°044
As described in the issue, a current source for current bypass is connected in parallel with the load resistance of a differential amplifier, and the conductance of the differentially connected transistors is increased to set the gain to a desired high value. Are known.

[Problem to be solved by the invention] However, in such a conventional differential amplifier,
It is almost impossible to change the gain by changing the current of a current source connected in parallel with the load resistance, and it is impossible to set the gain of a differential amplifier to any desired value. There was an inconvenience. Furthermore, since each current source and load resistor has different temperature characteristics and process dependencies, there is a disadvantage that the gain fluctuates due to changes in temperature or process conditions.

SUMMARY OF THE INVENTION In view of the above-mentioned problems with the conventional differential amplifier, it is an object of the present invention to enable the gain of the differential amplifier, and therefore its frequency characteristics, to be adjusted to any desired value, and to adjust the gain to any desired value. The objective is to be unaffected by changes or changes in process conditions.

[Means for Solving the Problems] A gain-adjustable differential amplifier according to the present invention includes first and second differential transistors of a first conductivity type;
and first and second load transistors of a second conductivity type connected in series between the drains of the second differential transistor, and a saturated internal voltage drop thereof at the gates of the first and second load transistors. The present invention is characterized in that it comprises a second conductivity type control voltage generating transistor means for supplying a control voltage that is not generated based on the current.

[Operation] In the above-mentioned differential amplifier, the square of the internal resistance R of the load transistor is the current (2) flowing through the control voltage generating transistor means. is inversely proportional to.

Furthermore, the square of gI of the differential transistor is proportional to the current IN flowing through the differential transistor. Therefore, the voltage gain Av of the differential amplifier = g11. R squared or A is the current IN and I. Therefore, by adjusting the ratio of these currents IN and Ip, the gain of the differential amplifier can be adjusted to an arbitrary value. Furthermore, since the gain can be adjusted to an arbitrary value, the frequency characteristics of the differential amplifier can also be adjusted to an appropriate value in consideration of the gain.

[Example] Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows a circuit configuration of a gain-adjustable differential amplifier according to an embodiment of the present invention.
These transistors 4^ and Q4B have their sources connected to each other, and 4^ parallel connected N-channel current source transistors Q5A.
” 5B to the power supply ■ss (ground in the figure). Each transistor Q4A and Q4
P-channel load transistors QIA and Q18 are connected in series between the drains of B, ie between nodes B and C. Further, each node B and C is connected to the power supply voltage V through P-channel transistors Q3 and Q, respectively.

Connected to 0.

B. Common connection point A of load transistors Q and QIB, and node D is connected to gate A of each transistor Q and Q3B. And each differential transistor Q
and Q4B's gates are connected to input terminals A INI and IN2, respectively. In addition, the drains of transistors Q and Q4B, that is, nodes A and B and C, respectively, are the output terminals 0UTI of the differential amplifier.
and connected to 0UT2. Further, a predetermined bias voltage VB is applied to each gate of current source transistors Q5A8 and Q5B.

Furthermore, in the differential amplifier of FIG. 1, the gates of load transistors QIA and Q18, ie, node E, and power supply V are connected to each other. - two control voltage generating transistors Q2A and Q2B are connected in series. Further, another current source transistor Q6 is connected between node E and ground. Note that each transistor Q and Q2
B has its gate A connected to its drain, that is, diode connected.

In the circuit shown in FIG. 1, current flows from the power supply VDo to transistors Q4A and Q4B forming a differential pair through P channel transistors Q3A and Q3B, respectively, and a current source flows from the mutually connected sources of transistors Q4A and Q4B. Transistors Q5A and Q5B
Current flows through the other power supply v88, in this case ground. Further, a control voltage or a reference voltage generated by transistors Q and Q28 and current source transistor Q6 is applied to the gates of load transistors Q1A and QlB, which are connected between the drains of transistors Q and Q4B. , providing the desired load resistance. With this configuration, the circuit of FIG. 1 has input terminals INI and I
The input voltage applied between N2 is amplified with a predetermined gain and output between output terminals 0UTI and 0UT2.

Next, the gain characteristics of the differential amplifier shown in FIG. 1 will be explained with reference to FIGS. 2 and 3. FIG. 2 is a principle diagram for explaining the value of the resistance R of the load transistor Q1- or QIB in the circuit of FIG. 1.

In FIG. 2, transistor Q 1 corresponds to the load transistor Q1A, t or Q 2 and has a channel width W1 and a channel length L1. Further, the transistor Q2 corresponds to the reference voltage generating transistor Q or Q2B in the circuit of FIG. 1, and has a channel width WA2 and a channel length L2. Also, the current source ISI
corresponds to transistor Q6 in the circuit of FIG.

In FIG. 2, transistor Q1 operates in a linear region, and its internal resistance R is given by the following equation.

R=(1/(μC)+(LlpO×f1/(vGs-Vl))/W1) In this equation, μ is the mobility of the P-channel transistor, C is the gate capacitance, GSx is the gate-source voltage, and Vl is the threshold voltage.

In addition, in FIG. 2, the current source IS is connected to the transistor Q2.
Current flowing through 1! . is given by the following formula.

I = (μ C/2) (W2/L2)D
p ox When formula (2) is transformed, (V6s-■1)2=(L2/W2) (2/(μ c)) ID...(3po
x Calculating R2 from equation (1) and equation (3), R” = (1
/ (μ C) 12 (L 7vti) 200X
11 (W/L2) (μpCox/2) (1/■D) ... (4) = +1
/(2μDCox)) (L 2W /(L W 2)1(1/ID)
... (5) Looking at the right side of equation (5), it is the product of the three terms enclosed in parentheses, but the first term is a term that is affected by the circuit manufacturing process and temperature changes. The second term is a constant value that is not affected by these, and the third term is a value that can be adjusted.

Next, referring to FIG. 3, there is shown a similar amplifier in which the internal resistance R of the transistor Q1 in FIG. 2 described above is used as a load resistance. This amplifier consists of a load resistor with a resistance value R and a transistor Q. and the power supply V in series. 0 and ground. The voltage gain A of this circuit is expressed by the following equation.

A = Vo/V■, = g, -R- (6) Here, g
l is a transistor Q. It is the mutual conductance of , and is expressed by the following formula.

1/2 g1=(2μNCox(W/L)■o)... (7) Here, ■o is the transistor Q. This is the drain current that flows to . Therefore, we obtain. Therefore, when the gain is determined using the above-mentioned equations (5), (6), and (8), the following equation is obtained.

=g, ,R =2μNC0x(W/L)IN (1/(2μpcoX)) (L W /(L2W1 (1/I,)... (9) In this equation, the current source ISI in Fig. 2 The current I flowing through the drain of the transistor Q in FIG.

A 2=((W/L)(L 2/w 2)v
1 1
(W2/L2)) (μN/μ, MI, /I.) ... (10) The right side of equation (10) is composed of the product of three terms enclosed in parentheses, but the first The 62nd term is determined by design factors and is not affected by temperature or process.The 62nd term consists of the mobility ratio and seems to be affected by temperature and process, but in reality it is The mobility and the mobility of a P-type transistor change with the same tendency with respect to temperature changes, changes in gate oxide film thickness, and the like. Therefore, this second term also has a stable value that is not affected by process and temperature changes. Therefore, the gain A,
What determines the current ratio ■N/I. This value can be set to any desired value depending on the ratio of gl, that is, the size and shape of each transistor. That is, this current ratio ■N/I. By adjusting , the gain can be set to a desired value.

The above considerations can also be applied to the circuit in Figure 1, and the transistor Q or Q in the circuit in Figure 1
4B corresponds to transistor 4^Q in the circuit of FIG. 3, load transistor Q or QIB in the circuit of FIG. 1 corresponds to transistor A, transistor Q1 in the circuit of FIG. If the transistor Q or Q2A corresponds to the transistor Q2 in the circuit B of FIG. 2, the gain in the circuit of FIG. 1 will be approximately the same as that shown by the above equation (10). In the circuit of FIG. 1, two control transistors (Q2° and Q2B) are connected in series, and one of these is for correcting the voltage drop A caused by the transistor Q or Q3B. Therefore, in the differential amplifier shown in FIG. 1, the gain can be set to any desired value by adjusting the current ratio (N/Il) or by fixing Ih and adjusting I. Current specific gravity N/■. is the gl of transistors Q5A1Q5B and Q6
This can be varied by adjusting the ratio of l and thus the size and shape ratio of each transistor.

FIG. 4 shows a circuit configuration of a differential amplifier according to another embodiment of the present invention. Q61. Q62. ...Q6N etc. are used. Transistor Q61゜Q ,...,Q6-
The sources are both grounded, and the gates are both connected to the bias power supply Ve.
It is connected to the. The drain of transistor Q61 is connected to node E, and the other transistors Q,...,Q
6N trains each have an interrupting section S2. using a metal mask or the like. ...Connected to node E via SN.

In the circuit of FIG. 4, the interrupting section S1. ..., transistor Q is connected between node E and ground by making a desired one of SN conductive and cutting off the others.
61. Q62. ..., it is possible to connect only the necessary ones among Q6N. Thereby, the current B flowing through the series circuit of transistors Q2A and Q2 for generating the control voltage can be adjusted to a desired value, and the gain of the differential amplifier can be set to a desired value. Note that the intermittent parts Sl, ..., SN may be formed by, for example, providing electrodes facing each other on the semiconductor substrate and connecting these electrodes with a metal mask as necessary, or each intermittent part may be It is also possible to set Sl, . Also, the fourth
In the circuit shown, each transistor Q62. ...”
The drain side of each transistor Q62.6N is connected to node E intermittently, but the drain side is always connected to node E. ..., the source side of Q6N can also be made intermittent. Furthermore, by controlling the value of the current IO with another circuit, the gain of the differential amplifier can be controlled or made variable, and an AGC circuit or the like can be constructed.

In the differential amplifiers shown in FIGS. 1 and 4, an additional current path is provided by transistors Q and Q3B, and the drain currents of differential transistors Q and Q4B are connected to nodes B and 4C. Since the DC voltage can be supplied without changing, it has a very good common mode suppression ratio.
ctionratio) is realized. Also, the voltage at node D, that is, the gates of transistors Q3A and Q3B, is the average value of the voltages at nodes B and C because of the division A by P-channel load transistors Q and Q18, and the input voltage IN1. Even if IN2 changes, it will be the same rm person.

In addition, since the load circuit of differential transistors Q and Q4B is a completely balanced circuit, it is guaranteed that load transistors QIA and QlB operate in the linear region, and these load transistors Q1A and QI
No direct current will flow through B.

Also, because it is a fully balanced circuit, extremely low distortion and low offset voltage can be achieved.

Furthermore, as is clear from the above equation (10), the differential amplifier according to the present invention includes a P-channel transistor Q2A,
It can be adjusted by changing the current 1p flowing through Q28, and changing the current I2 has no effect on the operating conditions of the N-channel input stage.

In addition, each factor on the right side of equation (10) is composed of a ratio of parameters of the same type, that is, for example, P
Ratio of channel and N channel mobilities (ttH/μO
), the current ratio of P-channel and N-channel transistors (IN/I, ), etc., and the gain is extremely stable without being affected by process or temperature changes.

Furthermore, since a method is used to control the current in each part in the saturation region, the gain does not fluctuate due to, for example, the power supply voltage.

Furthermore, as a result of being able to adjust the gain as described above, it is possible to obtain optimal characteristics depending on the application, taking into account the gain and the frequency band.

Table 1 shows the gain Gv and frequency band B− when each parameter is changed in the differential amplifier shown in FIG.
These are simulation results showing how the

Process TYP TYP C8 C3 OW Otl OL OL 1lC8 C3 C5 C8 Support C8 C8 11C3 Temperature Vdd (V 5.0 5.0 5.5 5.5 5.0 5.0 5.0 5.0 4.5 4 .5 4.5 4.5 4.5 4.5 4.5 Table 1 Vcon Vd1f (V nV 4.0 4.0 2.0 4.0 2.0 4.0 4.0 4.0 2 .0 4.0 4.0 4.0 2.0 4.0 4.0 4.0 4.0 4.0 2.0 4.0 4.0 0.01 4.0 0.1 4.0 1.0 4.0 10.0 4.0 100.0 8w (HN3) 22.5 22.5 31.6 31.6 18.0 19.95 19.95 19.95 12.59 15.85 12 .59 12.59 12.59 12.59 22.50 Gv (db) 12.0 10.9 10.3 11.7 12.5 13.5 9.98 9.15 12.2 11.4 12. 2 12.2 12.2 12.2 4.93 In this table, each symbol in the process column indicates that the mobility of the P-channel transistor and the N-channel transistor is in the following state.

P channel N channel TYP tyElical typlcal
BC3maximuIlmaxvui VORminimum maximumIIVOL
l1aXIlull 1lInllulW
C8i+rmwull minimuII, that is,
The symbol TYP indicates that the mobilities of P-channel transistors and N-channel transistors are both typical values (typical values).
l), the symbol BC3 indicates that the mobility of the P-channel transistor and the N-channel transistor are both maximum, and the symbol VOH indicates that the mobility of the P-channel transistor is the minimum and the mobility of the N-channel transistor is the maximum. In some cases, the same applies below. In addition, in Table 1, Vdd (V) is the power supply voltage, and Vcom (V)
represents the common-mode input voltage, and Vd i f (mV) represents the differential input voltage.

As is clear from Table 1, it can be seen that the differential amplifier according to the present invention is stable with very little change in gain with respect to changes in mobility, temperature, power supply voltage, etc. Note that under the conditions in the bottom row of Table 1, the differential input voltage Vd1f is large, so the differential amplifier becomes saturated, and the gain G.

It is a good value for appearance.

[Effect 3 of the Invention As described above, according to the present invention, the gain can be adjusted to a desired value with a simple circuit configuration, and the optimum gain and frequency band can be obtained. Further, it is possible to realize an extremely stable differential amplifier in which the gain value is less affected by process variations, temperature changes, power supply voltage changes, etc. Furthermore, the completely balanced circuit configuration provides a high common mode suppression ratio, low signal distortion, and low offset voltage, making it possible to realize an extremely high-performance circuit.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing the circuit configuration of a differential amplifier according to one embodiment of the present invention, and FIGS. 2 and 3 are diagrams for considering the operating characteristics of the differential amplifier according to the present invention, respectively. Explanatory Electrical Circuit Diagram FIG. 4 is an electrical circuit diagram showing the circuit configuration of a differential amplifier according to another embodiment of the present invention. QIA"1B" load transistor, Q2A"2B' control voltage generation transistor, Q3A
"3B' Current source transistor, Q4A, Q48: Differential transistor, Q5^・Q5B°Q6゛Q61°Q62'"'-Q6
N' current source transistor. Patent applicant Motorola Japan Co., Ltd. Representative Patent attorney Yoshiaki Ikeuchi Figure 1 Figure 2 Figure 8

Claims (1)

[Claims] 1. First and second differential transistors of a first conductivity type whose sources are differentially connected to each other, and connected in series between the drains of the first and second transistors. first and second load transistors of a second conductivity type that operate in a linear region, and a control voltage that is generated based on the saturated internal voltage drop to the gates of the first and second load transistors. 1. A gain-adjustable differential amplifier comprising: transistor means for generating a control voltage of two conductivity types. 2, further comprising first and second current source transistors each having a drain-source circuit connected between each drain of the first and second differential transistors and a first power supply conductor; The gates of the first and second current source transistors are both connected to a common connection point of the first and second load transistors, and the control voltage generating transistor means is configured to connect two transistors of a second conductivity type. a series circuit, one end of the series circuit being connected to the first power supply conductor and the other end being connected to the second power supply conductor via third current source transistor means and The adjustable gain differential amplifier of claim 1, connected to the gate of the second load transistor. 3. Said third current source transistor means comprises a plurality of transistors, each gate of said plurality of transistors is connected to a common bias power supply, each source is connected together to said second power supply conductor, and each drain of said plurality of transistors is connected to a common bias power supply. 3. The gain adjustable differential amplifier according to claim 2, wherein is selectively connectable to or disconnected from the other end of the series circuit.