JPH04351800A - Semiconductor storage device with error self-correcting function - Google Patents

Abstract

PURPOSE:To save the one which has incorrigible error bit numbers only in an inspection cell in a semiconductor storage device with an error self-correcting function. CONSTITUTION:The semiconductor storage device with an error self-correcting function has plural memory cells which store information and plural inspection cells which detect errors in the memory cell information and make corrections. This device has a defective address storing circuit 7, which stores the address at which defects are being-generated only in the inspection cells, and a defective address input detecting circuit 8 which based on the output of the above mentioned defective address storing circuit 7 detects the address when defects are being generated only in the inspection cells inputted from an address input circuit 2 and controls the operations on an error correcting circuit 5 to an inhibit condition.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to a semiconductor memory device with an error self-correction function, and in particular, it has data bits and check bits in a memory area, and when an error occurs in the data bits, it ECC (
The present invention relates to a semiconductor memory device equipped with an Error Check and Correct circuit.

0002

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional semiconductor memory device with an error self-correction function. In the figure, 1 is a memory cell array including test cells, 2 is an address input circuit, 3 is a row decoder, and 4 5 is a column decoder and readout circuit, 5 is an error correction circuit (ECC circuit), and 6 is an output circuit.

Next, the operation will be explained. An address signal from the address input circuit 2 is input to a row decoder 3 and a column decoder and readout circuit 4, and memory cells and test cells in the memory cell array 1 are selected and read out. Here, if an error occurs in the information of the read memory cell, the error is corrected by the error correction circuit 5 based on the information of the test cell, and the error is output from the output circuit 6.

[0004] Here, the error correction function of the error correction circuit 5 will be specifically explained. When the data bits of a memory cell consist of 3 bits (D0, D1, D2) and the test bits of a test cell consist of 3 bits (K0, K1, K2), the test bits are generated as follows.

[Math 1]

[0005] Then, the data bits (D0, D1
, D2) is (0, 1, 1), the check bit (K0
, K1 , K2 ) becomes (1,0,1). For example, if the data bit D1 is defective from "1" to "0", the data bit (D0
',D1',D2')=(0,0,1)

0006
] This is the incorrect data. The ECC circuit 5 is connected to this D1
' Find the error and correct it as follows.

First, syndromes (S0, S1, S2
).

From Equation 2, (S0, S1, S2) becomes (0, 1, 1).

Next, this syndrome (S0, S1,
Error signals (e0, e1, e2) are created from S2).

[Math 3]

From [0009], (e0, e1, e2) is (0
,1,0), and finally,

[Math 4]

Correct errors in the erroneous data by (
D0, D1, D2) = (0, 1, 1), the original correct data is obtained.

[0011]

However, since the conventional semiconductor memory device with error self-correction function is configured as described above, even if the original memory cell is normal, the error correction circuit 5 is not installed in the test cell. If there are more errors than the number of error bits that can be corrected, the resulting product will be defective, resulting in a reduction in yield.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor memory device with an error self-correction function that can be repaired even when only a test cell is defective.

[0013]

[Means for Solving the Problems] A semiconductor memory device with an error self-correction function according to the present invention stores an address in which only a test cell is defective, and when an address in which only a test cell is defective is input. This is detected and the error self-correction function is disabled.

[0014]

[Operation] The semiconductor memory device with an error self-correction function according to the present invention disables the error correction function when an address in which only the test cell is defective is input, so that only the test cell is incapable of error correction. Those with an erroneous number of bits are also saved.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a semiconductor memory device with an error self-correction function according to an embodiment of the present invention. In FIG. 1, 1 is a memory cell array including test cells, 2 is an address input circuit, 3 is a row decoder, 4 is a column decoder and read circuit, 5 is an error correction circuit (ECC circuit), and 6 is an output circuit. Further, 7 is a defective address storage circuit for storing an address in which only the test cell is defective;
inputs the output signal 17 from the address input circuit and the output signal 10 from the defective address storage circuit 7, and based on the output signal 10 of the defective address storage circuit 7, the address input circuit 2 selects an address where only the test cell is defective. This is a defective address input detection circuit which detects the input of a defective address and outputs a control signal 16 to the error self-correction circuit 5 for controlling the operation of the circuit 5 to a prohibited state.

Further, FIG. 2 shows a specific example of the circuit configuration of the defective address storage circuit 7 in FIG. 1, and FIG. 3 shows a specific example of the circuit configuration of the defective address input detection circuit 8 in FIG. In the figure, 9 is an inverter, 10 is an output terminal of the defective address storage circuit 7, 11a and 11b are capacitors, 12 is a fuse, 13 is an FET, and 14 is an output terminal of the address input circuit 2 and the defective address. An XOR circuit 15 receives the output signal 10 of the storage circuit and performs a logical operation on these output signals, and an XOR circuit 15 receives the output signal of the XOR circuit 14 and controls the operation of the error correction circuit 5. NOR outputs a control signal to
It is a circuit.

Next, the operation will be explained. An address signal from the address input circuit 2 is input to a row decoder 3 and a column decoder and readout circuit 4, and memory cells and test cells in the memory cell array 1 are selected and read out. Here, if only the memory cell has an error, the error in the data of the memory cell is corrected by the error correction circuit 5 based on the information of the test cell, as in the conventional example.

On the other hand, if more errors occur only in the check bits than the number of error bits that can be corrected by the error correction circuit 5, the address is stored in the defective address storage circuit 7.

[0019] A method for detecting addresses where only the test bits are defective is to test the LSI with a test device and compare the data read with the error correction circuit 5 deactivated using a control signal and the data read normally. This can be easily done by comparing the data and finding the address of the data where the former data is normal and the latter data is defective. In this searched address, only the check bits are defective, exceeding the number of bits that can be corrected by the error correction circuit 5, and even though the original memory data is normal, the data is incorrectly corrected. It is something that is kept away.

[0020] Addresses in which only the detected test bits are defective are stored in the defective address storage circuit 7. This can be easily done by cutting the fuse 12 shown in FIG. 2 with a laser. fuse 12
When disconnected, the output signal pn (however, n is 1 to j
(integer) 10 becomes "L", and becomes "H" when the fuse is not cut.

In this state, when the address signal 17 (A0 to Ai) in which only the test bits are defective is input from the address input circuit 2 to the defective address input detection circuit 8, the defective address detection circuit 8 Then, based on the output signal (p0 to pi) of the defective address storage circuit 7, it is detected that the above-mentioned address has been input, and an inhibition signal 16 for inhibiting the correction function is output to the error correction circuit 5. This prohibition signal 16 is generated by arithmetic processing of the address signal 17 from the address input circuit 2 and the output signal 10 from the defective address storage circuit in the XOR circuit 14 for each address.
The output of each XOR circuit 14 is further connected to a NOR circuit 1.
It can be obtained by performing arithmetic processing in step 5.

As described above, when an address in which only the test bit is defective is detected, this prohibition signal 1 is
6, the error correction circuit 5 outputs the information of the memory cell to the output circuit 6 without correction.

Therefore, according to the present embodiment, it is possible to save defective products due to the number of error bits that cannot be corrected by the error correction circuit 5 only in the test cells, thereby improving the yield. can do.

[0024]

[Effects of the Invention] As described above, according to the present invention, only the defective address of the test cell is memorized, and when the input of the address is detected, the error self-correction function is disabled. This has the effect of increasing the defect recovery rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a semiconductor memory device with an error self-correction function according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific circuit configuration example of the defective address storage circuit of FIG. 1;

FIG. 3 is a diagram showing a specific circuit configuration example of the defective address input detection circuit of FIG. 1;

FIG. 4 is a block diagram showing a conventional semiconductor memory device with an error self-correction function.

[Explanation of symbols]

1 Memory cell array 2 including test cells
Address input circuit 3 Row decoder 4 Column decoder and readout circuit 5
Error correction circuit 6 Output circuit 7 Defective address storage circuit 8 Defective address input detection circuit 9
Inverter 10 Output signal 11a of defective address storage circuit
Capacitor 11b Capacitor 12 Fuse 13 FET 14 XOR circuit 15 NOR circuit 16 Output signal 17 of defective address input detection circuit
address signal

Claims (1)

[Claims] Claim 1: A plurality of memory cells that store information;
In a semiconductor memory device with an error self-correction function, which includes a plurality of test cells for detecting and correcting errors in information in the memory cell, means for storing an address in which only the test cell is defective; , means for detecting input of an address in which only the test cell is defective based on the output of the means, and controlling the error self-correction function to a disabled state. Functional semiconductor memory device.