JPH04351477A - Lighting device for discharge lamp - Google Patents

Abstract

PURPOSE:To prevent simultaneous turning on due to a change in the ON period of a self-excited switching element. CONSTITUTION:A transistor Q1 in an inverter circuit 1 is turned on and off in a self-excited manner in response to a current flowing to a load circuit including a discharge lamp La. FETQ2 is turned on and off in a separately excitated manner by the output from a control circuit 3. After the transistor Q1 is turned off, the control circuit 3 sets the FETQ2 to the state where ON is possible before the current flowing through the primary winding L1 of drive transformer T1 is inverted.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides discharge lamp lighting using an inverter circuit with a half-bridge configuration in which one switching element is controlled on and off using a self-excitation type, and the other switching element is controlled on and off using a separately excited type. It is related to the device.

0002

2. Description of the Related Art A discharge lamp lighting device of this type is shown in FIG. This discharge lamp lighting device obtains DC power from an AC power supply e through a voltage doubler rectifier circuit 2, and supplies high-frequency power to the discharge lamp La from an inverter circuit 1 that operates using this DC power supply as a power supply. It lights up.

[0003] The voltage doubler rectifier circuit 2 includes diodes D1,
D2 and capacitors C1 and C2, which are connected in series by charging the capacitor C1 through the diode D1 during the positive half cycle of the AC power supply e and charging the capacitor C2 during the negative half cycle. This generates a voltage approximately twice that of a normal rectifying and smoothing circuit consisting of a diode and a capacitor across C2.

The inverter circuit 1 has a so-called half-bridge configuration, and uses a transistor Q1 and a FET Q2 as switching elements. The transistor Q1 is connected to the output of the voltage doubler rectifier circuit 2 via resistors R3 and R4, and has a diode D3 connected in antiparallel between its collector and emitter. Also, FETQ2
is connected between the base of the transistor Q1 and the negative output side of the voltage doubler rectifier circuit 2. That is, the transistor Q1 and the FET Q2 are connected to the output of the voltage doubler rectifier circuit 2 in substantially series.

[0005] The discharge lamp La is equipped with a capacitor C for cutting direct current.
3 and the primary winding L1 of the drive transformer T1 to both ends of the transistor Q1, and a preheating capacitor C4 is connected to the non-power supply side of the filament. Note that discharge resistors R1 and R2 are connected to the capacitors C3 and C4, respectively. Further, the primary winding L1 of the drive transformer T1 functions as a current limiting element and forms a series resonant circuit together with the preheating capacitor C4.

The drive transformer T1 supplies the voltage induced in the secondary winding L2 to the base of the transistor Q1 via the base resistor R5 to bias the transistor Q1, and connects the discharge lamp La, the capacitor C3,
The transistor Q1 is controlled to be turned on and off in a self-excited manner according to the current flowing through the load circuit consisting of C4 and the primary winding L1. Note that a diode D4 is connected between the base and emitter of the transistor Q1 to reverse bias the transistor Q1 to ensure that it is turned off when the FET Q2 is turned on.

Resistors R3 and R4 connected in series with the transistor Q1 detect the on state of the transistor Q1, and provide a detection output to a control circuit 3 that controls on/off of the FET Q2. The control circuit 3 includes a general-purpose timer IC (for example, μPC1555 manufactured by NEC) 4
An astable multivibrator 5 constructed using an IC 6, a T flip-flop 7 constructed using a D flip-flop IC 6, and an on-detection output of a transistor Q1, which is a voltage divided by resistors R3 and R4, are connected to an inverter gate G2. It consists of an AND gate G1 that ANDs the inverted output and the output of the T flip-flop 7.

In the astable multivibrator 5, the oscillation period is determined by the time constant of an external resistor R7 and a capacitor C5, and the capacitor C5 is determined by a current mirror circuit consisting of transistors Q4 and Q5 whose current value is determined by the resistance value of a resistor R6. Charging with current. The astable multivibrator 5 will be described in more detail as follows. Capacitor C5 is charged with a constant current supplied from the current mirror circuit, and when the voltage across this capacitor C5 reaches the threshold (2Vcc/3) set at the ■ pin as the threshold terminal, the output terminal The potential of (2) becomes high level. At this time, the ■ pin, which is the discharge terminal that had been in the open state, becomes low level, so the resistor R7
The charge in the capacitor C5 is discharged through the capacitor C5. Due to this discharge, the voltage across the capacitor C5 increases to Vcc/3
When the voltage drops to 1, a trigger is applied to the trigger terminal (■ pin), the ■ pin is inverted to a low level, and at the same time, the ■ pin becomes open, and charging of the capacitor C5 is started. Thereafter, the above operation is repeated until the voltage across capacitor C5 is between 2Vcc/3 and Vcc/3. An output waveform diagram of this astable multivibrator 5 is shown in FIG. 6(a).

The T flip-flop 7 is constructed by connecting the inverted output QB (QB indicates the upper bar of Q) of the D flip-flop IC 6 to the delay terminal D, and connects the clock input C of the astable multivibrator 5 to the delay terminal D. Every time a high level output is input (the output of the astable multivibrator 5 rises), the output Q is inverted. Therefore, the high and low level periods from the T flip-flop 7 are both one period of the astable multivibrator 5, and the duty is 50%.
A square wave signal is output. This T flip-flop 7
The output waveform of is shown in FIG. 6(b).

[0010] The operation of the above-mentioned discharge lamp lighting device during normal operation will be explained below based on FIG. 6. Now, the point in time when the output of the T flip-flop 7 becomes low level (time t0 in FIG.
), and if the output of AND gate G1 is inverted from high level to low level, FET Q2 is turned off. At this time, the primary winding L1 of the drive transformer T1 works so that the current that had been flowing until then due to the ON of FET Q2 continues to flow. Current flows through the path. Therefore, a voltage that forward biases the transistor Q1 shown in FIG. 6(d) is induced in the secondary winding L2 of the drive transformer T1, and this voltage causes a base current to flow through the transistor Q1.
is ready to be turned on.

When the energy stored in the primary winding L1 is consumed, the transistor Q1 turns on. When the transistor Q1 turns on in this way, the charge accumulated in the capacitor C3 up to that point is used as a power source.
Capacitor C3 → Transistor Q1 → Primary winding L1
→The current shown in Fig. 6(c) flows in the path of the discharge lamp La,
The charge on capacitor C3 is discharged. Note that the current flowing through the diode D3 until the transistor Q1 is turned on is shown as a negative current in FIG. 6(c).

The current in this path increases as shown in FIG. 6(c) as the on state of the transistor Q1 deepens because positive feedback is applied to the drive transformer T1. This current causes the secondary winding L2 of the drive transformer T1 to
The voltage induced in the secondary winding L is canceled out, and finally the voltage induced in the secondary winding L
The voltage induced in the transistor Q1 becomes a negative voltage, and a reverse bias is applied to the transistor Q1, turning off the transistor Q1. However, in this case, the delay shown in FIG. 6(c) occurs due to the switching delay of the transistor Q1.

When the transistor Q1 is turned off, the primary winding L1 works to maintain the current in the same direction.
Current flows through the following path: primary winding L1 → discharge lamp La → capacitor C3 → capacitor C1 → capacitor C2 → FET Q2 (parasitic diode) → secondary winding L2. In this case, as shown in FIG. 6(f), the transistor Q
1 is on, the output voltage E of the voltage doubler rectifier circuit 2 is applied between the drain and source of FETQ2, but the parasitic diode (damper diode) of FETQ2
The forward voltage drops to .

At this time, since the divided voltages of the resistors R3 and R4 become low, the output of the inverter gate G2 becomes high level as shown in FIG. The output of AND gate G1, which takes an AND with the output of T flip-flop 7 shown in FIG.
is ready to be turned on.

By the way, the gradual rise and fall of the input to inverter gate G2 is due to the input capacitance of inverter gate G2, and the delay time between the rise and fall in this case is due to the input capacitance. and resistance R3,R
It is determined by the value of 4. Therefore, there is a delay in the change in the output of the inverter gate G2 shown in FIG.

Here, resistors R3, R4, inverter gate G2, and AND gate G1 are provided to prevent FET Q2 from being turned on when transistor Q1 is turned on. Then, when the energy stored in the primary winding L1 is consumed, the FET Q2
is turned on and the current direction is reversed. When FETQ2 turns on, voltage doubler rectifier circuit 2 → capacitor C3 →
Discharge lamp La → Primary winding L1 → Diode D4 → FE
Current flows through the path of TQ2. Note that the negative current in FIG. 6(e) indicates the current flowing through the parasitic diode of FETQ2.

Here, when FETQ2 is turned on and current flows through the above path, diode D4 is turned on, so that the base-emitter of transistor Q1 is reverse biased, and FETQ2 is turned on. It is ensured that transistor Q1 is turned off at certain times. Thereafter, by repeating the above operation, transistor Q1 and FET Q2 are turned on and off alternately,
The inverter circuit 1 converts the output of the voltage doubler rectifier circuit 2 into a high frequency signal, and lights up the discharge lamp La at high frequency.

[0018]

However, in the case of the above-mentioned conventional example, the so-called self-excited and separately excited type inverter circuit 1 is used, and the secondary winding L2 is caused by the oscillating current flowing in the primary winding L1 of the drive transformer T1. The voltage induced in the transistor Q1 is fed back to the base of the transistor Q1.
is under self-excitation control. Therefore, if the AC power supply e fluctuates in a decreasing direction, or the amplification factor of the transistor Q1 (
hFE) or changes in ambient temperature,
The phase of the oscillating current flowing through the primary winding L1 may advance. In this case, as shown in FIG. 7(d), the secondary winding L
Since the phase of the voltage induced in Q2 also advances, the on-period of transistor Q1 becomes shorter, as shown in (c) of the same figure.
The following problems arise.

Now, at time t0 shown in FIG. 7(a), FE
TQ2 is turned off and transistor Q1 is turned off by the operation described above.
Assume that transistor Q1 is turned on and transistor Q1 is turned off at time t1. In this case, the transistor Q1 is turned off earlier for the reason mentioned above. When the transistor Q1 is turned off in this way, a current flows through the path of the primary winding L1 → discharge lamp La → capacitor C3 → capacitor C1 → capacitor C2 → FET Q2 (parasitic diode) → secondary winding L2, as described above. FETQ
The voltage between the drain and source of FET Q2 drops to the forward voltage of the parasitic diode (damper diode) of FET Q2, as shown in FIG. 7(f). Then, at time t2, the input voltage of inverter gate G2 drops below the threshold voltage Vth of inverter gate G2, and the output of inverter gate G2 becomes as shown in (h) in the figure.
The level becomes high as shown in .

[0020] Then, at time t3, the current flowing through the primary winding L1 is reversed. Note that the current reversal point in the primary winding L1 is earlier than in normal conditions because the on period of the transistor Q1 is shortened. When this current is reversed, normally FET Q2 is turned on, so as mentioned above, voltage doubler rectifier circuit 2 → capacitor C3
→Discharge lamp La→Primary winding L1 →Diode D4 →
Current flows through the path of FETQ2.

However, in this case, the output of the T flip-flop 7 is still at a low level as shown in FIG. do not have. Therefore, in this case, current flows through the path of primary winding L1 -> diode D3 -> capacitor C3 -> discharge lamp La. At this time, the drain-source voltage of FET Q2 (that is, the voltage across resistors R3 and R4) rises to the output voltage E of voltage doubler rectifier circuit 2 as shown in FIG. 7(f), so inverter gate G2 The input voltage of the inverter gate G rises as shown in FIG.
The input voltage of G1 does not reach the threshold voltage Vth, so both inputs of AND gate G1 become high level, and the output becomes high level.

Therefore, in this case, the voltage doubler rectifier circuit 2 → diode D3 →
A short circuit current will flow through the path from diode D2 to FET Q2. Here, after the reverse recovery time of the diode D3 has elapsed, the normal operation is temporarily resumed, but the above-mentioned operation is repeated as shown in FIG. In other words, a situation similar to the power supply short-circuit condition caused by simultaneous turning on of the switching elements occurs, which is a problem in this type of half-bridge inverter circuit in which switching elements are completely connected in series. Therefore, due to the above-mentioned excessive short circuit current, a large stress is applied to FETQ2 etc., and in some cases, FETQ2 etc. may be damaged. In the following description, the problematic operation of the conventional example described above will also be referred to as simultaneous on.

The present invention has been made in view of the above-mentioned points, and its object is to provide a discharge lamp lighting device that does not cause simultaneous on-on by changing the on-period of a self-excited switching element. It is about providing.

[0024]

[Means for Solving the Problems] In order to achieve the above object, in the present invention, the control circuit switches the second switching element on before the oscillating current in the load circuit is reversed after the first switching element is turned off. It is enabled to be turned on. Note that the control circuit controls the second switching element to be turned on before the oscillating current in the load circuit is reversed after the first switching element is turned off, depending on the on state of the first switching element. It is preferable to vary it.

[0025]

[Operation] As described above, the control circuit enables the second switching element to turn on before the oscillating current in the load circuit is reversed after the first switching element is turned off. Even if the switching element turns off earlier, the second switching element turns on when the oscillating current in the load circuit is reversed, thereby preventing simultaneous turning on.

[0026]

【Example】

(Embodiment 1) FIG. 1 shows an embodiment of the present invention. The circuit configuration of the discharge lamp lighting device of this embodiment is almost the same as the conventional discharge lamp lighting device explained in FIG. It's in the action.

The control circuit 3 of this embodiment includes a general-purpose timer I
An astable multivibrator 5 configured using C (for example, μPC1555 manufactured by NEC, etc.) and an AND gate G
1 and an inverter gate G2. Although the astable multivibrator 5 does not use a current mirror circuit, it oscillates by charging and discharging the capacitor C5 between Vcc/3 and 2Vcc/3, substantially the same as the conventional circuit shown in FIG. Operate. Here, if the high level period of the output of pin ■, which is the output of the astable multivibrator 5, is TH, and the low level period is TL, then
TH = 0.693 (R6 + R7)・C5 TL
=0.693R7・C5.

In the case of this embodiment, if the low level period TL of the output of the astable multivibrator 5 is taken as T1 and the on period of the transistor Q1 is taken as T1, then TL
<T1...(1
). Note that this condition is made sure to hold even if the on-period T1 of the transistor Q1 fluctuates due to factors such as voltage fluctuations of the AC power source e, variations in hFE of the transistor Q1, or changes in ambient temperature.

Furthermore, the low level period TL of the output of the astable multivibrator 5 is defined as T2, which is the period during which the FET Q2 is completely turned off and the divided voltage of the resistors R3 and R4 exceeds the threshold voltage of the inverter gate G2. If TH > T2
...(2) is set.

In other words, even if the on period of transistor Q1 is shortened due to voltage fluctuations in AC power supply e, variations in hFE of transistor Q1, or changes in ambient temperature, the transistor shown in FIG. 2(c), for example, At time t1 when Q1 is turned off, the output of the astable multivibrator 5 is always at a high level, as shown in FIG. 4(b).

The operation of this embodiment will be explained below. now,
At the output of AND gate G1 shown in FIG. 2(i), time t0
At time t1, FET Q2 is turned off, and transistor Q1 is turned on by the operation explained in the conventional example circuit of FIG.
Assume that transistor Q1 is turned off. In this case, it is assumed that the transistor Q1 is turned off earlier for the reason mentioned above.

When transistor Q1 is turned off, a current flows through the path of primary winding L1 → discharge lamp La → capacitor C3 → capacitor C1 → capacitor C2 → FETQ2 (parasitic diode) → secondary winding L2, and FETQ
The voltage between the drain and source of FET Q2 drops to the forward voltage of the parasitic diode (damper diode) of FET Q2, as shown in FIG. 2(f). Then, at time t2,
As shown in (g), the input voltage of inverter gate G2 falls below the threshold voltage Vth of inverter gate G2, and the output of inverter gate G2 becomes high level as shown in (h) of the same figure.

Then, the current flowing through the primary winding L1 is reversed. When this current is reversed, the output of the astable multivibrator 5 is always at a high level at time t1 when the transistor Q1 is turned off as described above, so the FET Q2 is turned on. Therefore, voltage doubler rectifier circuit 2 → capacitor C3 → discharge lamp La
Current flows through the following path: → primary winding L1 → diode D4 → FET Q2.

That is, in the case of this embodiment, the primary winding L
When the current in G1 is reversed, FETQ2 is always turned on. In other words, when the parasitic diode of FETQ2 is on, the output of AND gate G1 is always at a high level that enables FETQ1 to be turned on. It's made to look like it's there. Therefore, like the conventional circuit, 1
When the current in the next winding L1 is reversed, the AND gate G1 remains
The output of FET Q2 is at low level, FET Q2 is not in a state where it can be turned on, and current flows through the path of primary winding L1 → diode D3 → capacitor C3 → discharge lamp La, and then FET
Q2 is turned on, and no short-circuit current flows in the path from voltage doubler rectifier circuit 2 to diode D3 to diode D2 to FET Q2 for the reverse recovery time of diode D3.

However, as shown in FIGS. 2(c) and 2(h), there is a delay indicated by T in the figure between the time t1 when the transistor Q1 is turned off and the time t2 when the output of the inverter gate G2 becomes high level. There is. However, since the delay time T is shorter than the time required for the current in the primary winding L1 to reverse after the transistor Q1 is turned off, there is no problem and it can be ignored.

(Embodiment 2) FIG. 3 shows another embodiment of the present invention. In this embodiment, the astable multivibrator 5 of the above-mentioned embodiment 1 has a different structure, and operates in the same manner as in the above-mentioned embodiment 1. is designed to prevent this from occurring.

The configuration of the astable multivibrator 5 of this embodiment will be explained below. This astable multivibrator 5 includes an operational amplifier OP1, an inverter gate G
3, transistors Q3 to Q8, capacitor C5
, and resistors R6 to R13. Here, the operational amplifier OP1 is used as a comparator, and the reference voltage of this comparator is created by dividing the drive voltage Vcc using resistors R6 to R8. The reference voltage is switched by the output of the operational amplifier OP1. That is, the transistor Q3 connected to both ends of the resistor R8 is turned on and off by the output of the inverter gate G3 which inverts the output of the comparator.

Here, the voltage divided by the resistors R6 to R8 is (R7 +R8)·Vcc/(R6 +
R7 +R8)=2Vcc/3. Also, the voltage divided by the resistors R6 and R7 is R7 ・Vcc/
(R6 +R7)=Vcc/3.

The comparison input of the comparator is the voltage across the capacitor C5. This capacitor C5
are transistors Q4 to Q6 and resistors R9 to R1
The transistors Q7, Q
8 and a second current mirror circuit consisting of resistors R12 and R13. The operation of the second current mirror circuit is controlled by a transistor Q9 which is turned on and off by the output of the comparator.

Note that the mirror ratio of the first current mirror circuit is such that the current flowing through the resistor R14 is I0, and the current flowing through the transistors Q4 to Q6 is IQ4 to IQ6.
In this case, IQ4=IQ5=IQ6=I0. Moreover, the mirror ratio of the second current mirror circuit is such that the current flowing through the transistors Q7 and Q8 is
In the case of Q7 and IQ8, IQ7=2IQ8+IX. Here, since IQ8=I0, IQ
7=2I0+IX.

The operation of this astable multivibrator 5 will be explained below. Now, assuming that the output of the comparator is at a high level, transistor Q3 is off,
Transistor Q9 is on. Therefore, the reference voltage of the comparator becomes 2Vcc/3, and the second current mirror circuit is controlled to be inoperative. Therefore, capacitor C5 is charged with current I0.

Then, the voltage across the capacitor C5 is 2
When Vcc/3 is reached, the output of the comparator is inverted from high level to low level. When the output of the comparator becomes low level in this way, the transistor Q3 is turned on, the reference voltage becomes Vcc/3, and the transistor Q9 is turned off, so that the second current mirror circuit operates. Therefore, the charge in the capacitor C5 is increased by the current 2I0 supplied to the second current mirror circuit.
It is discharged with a current I0 +IX obtained by subtracting the current I0 supplied from the first current mirror circuit from +IX.

Then, the voltage across the capacitor C5 is V
When cc/3 is reached, the output of the comparator is inverted to high level, thereby operating the oscillation. In other words,
Although the present embodiment differs in circuit configuration from the astable multivibrator 5 of the first embodiment, it operates in exactly the same way. Here, by adjusting the value of the current IX, the low level period TL of the output of the astable multivibrator 5 is set so as to satisfy both equations (1) and (2) above.

(Embodiment 3) FIG. 4 shows another embodiment of the present invention. In the case of the above-mentioned embodiment, the low level period TL of the astable multivibrator 5 is determined by equations (1) and (2), regardless of whether or not there is a voltage fluctuation of the AC power supply e.
was set to satisfy. However, in the case of this embodiment, the settings are made so that the above equations (1) and (2) are satisfied when a voltage fluctuation or the like of the AC power supply e occurs.

In this embodiment, when there is a voltage fluctuation of the AC power supply e, the low level period TL of the astable multivibrator 5 is set to satisfy the above equations (1) and (2). explain. In this embodiment, transistors Q10, A third current mirror circuit consisting of Q11 and resistor R16 is added, and this third current mirror circuit connects the transistor Q8 of the second current mirror circuit.
It is designed to control the current flowing to the

The mirror ratio of this third current mirror circuit is such that the current flowing through transistors Q10 and Q11 is
If Q10 and IQ11, IQ10 = IQ11 = I1
=
(E-VBE(Q11) )/R6
=(E-0.6)/
R6...(3). However, E indicates the output voltage of the voltage doubler rectifier circuit 2 when the rated power is supplied to the voltage doubler rectifier circuit 2 from the AC power source e.

In the case of this embodiment, the mirror ratio of the first current mirror circuit is IQ4=IQ6=I0, IQ5=I0+I1
It is as follows. The operation of this embodiment will be explained below. Now, when the rated output is being supplied from the voltage doubler rectifier circuit 2 (the output voltage is E), the transistor Q5
Current I1 supplied to transistor Q10 of the third current mirror circuit from current I0 +I1 supplied from
The current minus I0, that is, I0, is the current flowing through transistor Q8.
Therefore, the current supplied to the transistor Q7 of the second current mirror circuit becomes 2I0 +IX, and therefore the capacitor C5 satisfies equations (1) and (2) as explained in Example 2. The low level period TL of the output of the astable multivibrator 5 is set.

Here, even when the AC power source e is rated, the low level period TL of the output of the astable multivibrator 5
The reason why is made to satisfy equations (1) and (2) is as follows.
This is done in consideration of variations in the amplification factor (hFE) of the transistor Q1, changes in ambient temperature, etc. In the above case, the rated power is being supplied from the AC power supply e, but when the voltage of the AC power supply e decreases, E in equation (3) becomes smaller, so the transistors Q10 and Q11 The flowing current becomes lower than the current I1. In other words, IQ10 = IQ11 < I1. Therefore, the current I flowing through the transistor Q8
Q8 is IQ8=IQ5-IQ10 =I0 +I1 -IQ1
0>I0. Therefore, the current flowing through transistor Q7 increases, and the discharge current of capacitor C5 increases. Therefore, the low level period TL of the output of the astable multivibrator 5 can be further shortened in accordance with fluctuations in the AC power source e, and an even better simultaneous-on prevention effect can be expected. In this case, as far as the voltage fluctuation of the AC power source e is concerned, there is no need to shorten the low level period TL of the output of the astable multivibrator 5 at the rated time.

By the way, in the above case, when the voltage of the AC power source e rises above the rated voltage, the low level period TL of the output of the astable multivibrator 5 becomes longer, but in this case, the on period T1 of the transistor Q1 becomes longer. is also long, so formula (1) is satisfied and there is no problem. Furthermore, in the above case, only the fluctuations in the AC power source e are fed back to the control circuit 3 to control the low level period TL of the output of the astable multivibrator 5, but the amplification factor (hFE) of the transistor Q1 The output is fed back to the control circuit 3 according to variations in the temperature or changes in the ambient temperature, etc.
Low level period T of the output of the astable multivibrator 5
It goes without saying that L may be controlled.

[0050]

Effects of the Invention As described above, in the present invention, the control circuit enables the second switching element to be turned on before the oscillating current in the load circuit is reversed after the first switching element is turned off. Even if the first switching element turns off earlier, the second switching element turns on when the oscillating current in the load circuit is reversed, and simultaneous turning on does not occur.

[0051] Furthermore, the control circuit performs control to enable the second switching element to be turned on before the oscillating current in the load circuit is reversed after the first switching element is turned off.
By varying the on-state of the first switching element, switching of the second switching element can be appropriately controlled.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of the same operation as above.

FIG. 3 is a circuit diagram of another embodiment.

FIG. 4 is a circuit diagram of still another embodiment.

FIG. 5 is a circuit diagram of a conventional example.

FIG. 6 is an explanatory diagram of the same operation as above.

FIG. 7 is an explanatory diagram of the problem same as above.

[Explanation of symbols]

1 Inverter circuit 3 Control circuit e　AC power supply La discharge lamp Q1 Transistor Q2 FET T1 Drive transformer C3, C4 capacitor

Claims (2)

[Claims] Claim 1: A DC power supply, first and second switching elements connected in series to the DC power supply, and an LC resonant circuit connected to both ends of the first switching element via a DC cut capacitor. It is equipped with a load circuit consisting of a discharge lamp, and a control circuit that controls on/off the second switching element, and the voltage induced in the secondary winding provided in the choke coil of the LC resonant circuit is controlled by the first switching element. In the discharge lamp lighting device, the first switching element returns to a control terminal of the switching element to turn it on and off, detects the off state of the first switching element, and turns on and off the second switching element using a control circuit. A discharge lamp lighting device characterized in that a control circuit enables a second switching element to be turned on before an oscillating current in a load circuit is reversed after the element is turned off. 2. The control circuit performs control to enable the second switching element to be turned on before the oscillating current in the load circuit is reversed after the first switching element is turned off. 2. The discharge lamp lighting device according to claim 1, wherein the discharge lamp lighting device is variable depending on the state.