JPH0434965A - Semiconductor device - Google Patents

Abstract

PURPOSE:To achieve high inductance and to reduce the area of a chip by arranging a wiring layer which is surrounded with a multilayered structure around a material having a high permeability which is formed in a wiring layer, and forming at least one solenoid in the vertical direction. CONSTITUTION:A material having a high permeability is vertically formed based on the positional relationship between the direction of a current flowing through a wiring when a DC power supply is applied across electrodes 11 and 12 and the material having the high permeability. A wiring is formed around the material. Thus, a coil element having the small element occupying area and the high dielectric coefficient can be formed. When the coil having a high inductance is formed by constituting the coil element in three dimensions in the semiconductor device, the occupying area of the element can be made smaller than a conventional coil element, and the area of the chip can be reduced. Therefore, the yield rate associated with the chip area is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a coil element included in a circuit thereof.

[Conventional technology]

2. Description of the Related Art A coil element is a circuit element of a semiconductor device, and its structure has heretofore been arranged in a plane along an insulating film, as shown in the example of FIG.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, the coil element is configured in a planar manner along the insulating film.

In this case, when forming a coil with a high induction coefficient, the length between the electrodes increases and the area of the coil element increases. Therefore, in the conventional coil structure, the coil element occupies a large area and the chip area also becomes large, so there is a drawback that the yield related to the chip area is low.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that has a high induction coefficient and can occupy a small element area, thereby reducing the chip area.

[Means to solve the problem]

In the semiconductor device of the present invention, in a semiconductor device having a coil element, a wiring layer is formed around a high-permittivity material.
It is characterized by having wiring layers surrounded by a multilayer structure and forming at least one solenoid in the vertical direction.

〔Example〕

Next, the present invention will be explained with reference to the drawings. 1st
The figure is a cross-sectional view of one embodiment of the present invention, FIG. 2(a) is a plan view of the first wiring layer, FIG. 2(b) is a plan view of the second wiring layer, and FIG.
) is a plan view of the third wiring layer.

FIG. 3 is a diagram showing the direction of current flowing through the wiring when a DC power is applied to the electrodes 11 and 12, and the positional relationship with the high-permittivity material.

These drawings show that by forming a high-permittivity material perpendicularly on a wiring layer and forming wiring around it, a coil element can be formed that occupies a small area and has a high dielectric constant.

〔Effect of the invention〕

As explained above, the present invention enables the formation of a coil with a high induction coefficient by three-dimensionally refining the coil element in a semiconductor device, and the area occupied by the element can be smaller than that of conventional coil elements, and the chip area can also be reduced. This has the effect of improving the yield in terms of chip area.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG.
Figures (a) to (c) show the first layer wiring of an embodiment of the present invention,
The plan view of the second layer wiring and the third layer wiring, and FIG. FIG. 5 shows the positional relationship with the conventional coil element.
FIG. 5 is a plan view of FIG. 4. DESCRIPTION OF SYMBOLS 1... First wiring layer, 2... Second wiring layer, 3... Third wiring layer, 4... High dielectric constant material, 5... Interlayer film, 6
Interlayer film between middle cylinder 3 wiring layer and upper layer, 7... Glabella film 1, 8 between third wiring layer and second wiring layer... Interlayer film between second wiring layer and first wiring layer, 9 ...Interlayer film between the first wiring layer and the lower layer, 10...Substrate, 11.12...Electrode, 13...
1st layer wiring - 2nd layer wiring through hole, 14...2nd layer wiring
Layer wiring - 3rd layer wiring through hole.

Claims (1)

[Claims] A semiconductor device having a coil element, characterized in that a wiring layer surrounded by a multilayer structure is arranged around a high-permittivity material formed in the vertical direction of the wiring layer, and at least one solenoid is formed in the vertical direction. semiconductor device.