JPH0434962A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0434962A JPH0434962A JP2140827A JP14082790A JPH0434962A JP H0434962 A JPH0434962 A JP H0434962A JP 2140827 A JP2140827 A JP 2140827A JP 14082790 A JP14082790 A JP 14082790A JP H0434962 A JPH0434962 A JP H0434962A
- Authority
- JP
- Japan
- Prior art keywords
- type
- oxide film
- field oxide
- junction
- diffused region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 abstract description 9
- 230000002093 peripheral effect Effects 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 13
- 239000010410 layer Substances 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に半導体チップ上のメモ
リー内容書込み時に高電圧を必要とするメモリーの基準
電圧制御用として逆方向に挿入されるPN接合型ダイオ
ードの構造に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor devices, and in particular to a PN inserted in the reverse direction for controlling the reference voltage of a memory that requires high voltage when writing memory contents on a semiconductor chip. Regarding the structure of a junction diode.
従来、メモリー内容書込み用高電圧の制御は、P型半導
体基板を低電位側に接続し、そのP型半導体基板上に形
成したソースあるいはドレイン形成用のN型領域をメモ
リー内容書込み用高電圧側に接続してPN接合ダイオー
ドを形成し、そのブレークダウン電圧で書込用電圧の上
限を抑制している。Conventionally, the control of high voltage for writing memory contents has been achieved by connecting a P-type semiconductor substrate to the low potential side, and connecting an N-type region formed on the P-type semiconductor substrate for forming a source or drain to the high voltage side for writing memory contents. is connected to form a PN junction diode, and its breakdown voltage suppresses the upper limit of the write voltage.
第2図は従来の半導体装置の断面図である。FIG. 2 is a sectional view of a conventional semiconductor device.
第2図に示すように、P型シリコン基板1の表面にP+
型のチャネルストッパ層3及び厚いフィールド酸化膜2
を選択的に形成した後にフィールド酸化膜2をマスクと
してソースあるいはドレインを形成するものと同等の濃
度のN型不純物イオンを注入して形成する為、薄い熱酸
化膜1の下にのみメモリー内容書込み用電圧制御用のダ
イオードのN1型拡散領域5が存在している。As shown in FIG. 2, P+
type channel stopper layer 3 and thick field oxide film 2
After selectively forming the field oxide film 2, the field oxide film 2 is used as a mask to implant N-type impurity ions at the same concentration as that for forming the source or drain, so memory contents can be written only under the thin thermal oxide film 1. There is an N1 type diffusion region 5 of a diode for voltage control.
そのPN接合ダイオードのPN接合は、フィールド酸化
膜2を厚く成長させる前にP型シリコン基板9の表面に
形成された、P型シリコン基板9より濃度の濃いP1型
チャネルストッパ層3とN“型拡散領域5で形成される
為、そのPN接合部は薄い熱酸化膜1と厚いフィールド
酸化膜2の境界の下に存在している。The PN junction of the PN junction diode is formed between a P1 type channel stopper layer 3 having a higher concentration than the P type silicon substrate 9, which is formed on the surface of the P type silicon substrate 9 before the field oxide film 2 is grown thickly, and an N" type channel stopper layer 3. Since it is formed in the diffusion region 5, the PN junction exists under the boundary between the thin thermal oxide film 1 and the thick field oxide film 2.
この従来の半導体装置は、PN接合部が薄い熱酸化膜と
厚いフィールド酸化膜の境界の下に存在している為、そ
の部分のP+型チャネルストッパ層や、N+型拡散領域
の濃度のバラツキや、薄い熱酸化膜へのキャリアのトラ
ップによる表面濃度の変調により、PN接合型ダイオー
ドの逆バイアスのブレークダウン電圧の安定性が悪くな
り、メモリー書込み試験の前と後、或いは熱ストレスを
加える前と後でメモリー内容書込み基準高電圧が大きく
変動してしまう為に、メモリー内容書込みの信頼性が低
くなるという問題点があった。In this conventional semiconductor device, since the PN junction exists under the boundary between the thin thermal oxide film and the thick field oxide film, there are variations in the concentration of the P+ type channel stopper layer and the N+ type diffusion region in that part. , the stability of the breakdown voltage of the reverse bias of the PN junction diode deteriorates due to the modulation of the surface concentration due to the trapping of carriers in the thin thermal oxide film. There is a problem in that the reliability of memory content writing becomes low because the reference high voltage for writing memory content changes greatly afterwards.
本発明の半導体装置は、メモリー内容書込み時に高電圧
を必要とするメモリーの基準高電圧制御用として逆方向
に挿入されるP型半導体基板上のPN接合型ダイオード
のN型拡散領域を厚いフィールド酸化膜を形成させる前
にソースあるいはドレインを形成するものと同等の濃度
のN型不純物を成長させる前のフィールド酸化腰下まで
注入して形成することにより、P+型チャネルストッパ
層と接するダイオードのPN接合の周縁部を厚いフィー
ルド酸化膜の下に延在して形成される。In the semiconductor device of the present invention, thick field oxidation is applied to the N-type diffusion region of a PN junction diode on a P-type semiconductor substrate inserted in the reverse direction for controlling a reference high voltage of a memory that requires a high voltage when writing memory contents. Before forming the film, N-type impurities with a concentration equivalent to that for forming the source or drain are implanted to the bottom of the field oxidation layer before the film is grown, thereby forming a PN junction of the diode in contact with the P+ type channel stopper layer. is formed by extending the peripheral edge of the field under a thick field oxide film.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of one embodiment of the present invention.
第1図に示すように、P型シリコン基板9の表面にソー
スあるいはドレインを形成するものと同等の濃度のN型
拡散領域4を選択的に設け、次に、チャネルストッパ層
3及びフィールド酸化膜2の一部がN型拡散領域4に重
なるように選択的に形成する。次に、フィールド酸化膜
2をマスクとしてN型不純物をイオン注入し、N型拡散
領域4と接続するN1型拡散領域5を形成する。As shown in FIG. 1, an N-type diffusion region 4 with a concentration equivalent to that forming a source or drain is selectively provided on the surface of a P-type silicon substrate 9, and then a channel stopper layer 3 and a field oxide film are formed. 2 is selectively formed so as to partially overlap with the N-type diffusion region 4. Next, using the field oxide film 2 as a mask, N type impurities are ion-implanted to form an N1 type diffusion region 5 connected to the N type diffusion region 4.
ここで、PN接合型ダイオードのPN接合は、チャネル
ストッパ層3とN型拡散領域4で形成され、PN接合の
周縁部は厚いフィールド酸化膜2の下に延在して形成さ
れる。Here, the PN junction of the PN junction diode is formed by the channel stopper layer 3 and the N type diffusion region 4, and the peripheral portion of the PN junction is formed extending under the thick field oxide film 2.
以上説明したように本発明は、メモリー内容書込み時に
高電圧を必要とするメモリーの基準高電圧制御用として
逆方向に挿入されるPN接合型ダイオードのPN接合の
周縁部を厚いフィールド酸化膜の下に延在して形成する
ことにより、PN接合部が薄い熱酸化膜や、薄い熱酸化
膜と厚いフィールド酸化膜の境界部の影響を受けない様
にして、PN接合部での21型チヤネルストツパ領域や
N型拡散領域の濃度のばらつきを生じにくくし、薄い熱
酸化膜へのキャリアのトラップによる表面濃度の変調を
なくす事で、信頼性や耐久性の高い安定したメモリーの
基準高電圧が得られる効果がある。As explained above, the present invention provides a method for attaching the periphery of the PN junction of a PN junction diode inserted in the reverse direction under a thick field oxide film to control the reference high voltage of a memory that requires a high voltage when writing memory contents. By forming the 21-type channel stopper region at the PN junction so that the PN junction is not affected by the thin thermal oxide film or the boundary between the thin thermal oxide film and the thick field oxide film, By making it difficult to cause variations in concentration in the N-type and N-type diffusion regions and eliminating surface concentration variations due to carrier trapping in the thin thermal oxide film, a stable reference high voltage for memory with high reliability and durability can be obtained. effective.
又、本発明によるPN接合型ダイオードをメモリー以外
の部分の電圧制御として使用しても、同様の効果が得ら
れる。Further, the same effect can be obtained even if the PN junction diode according to the present invention is used for voltage control of parts other than memory.
第1図は本発明の一実施例の断面図、第2図は従来の半
導体装置の一例の断面図である。
1・・・薄い熱酸化膜、2・・・フィールド酸化膜、3
・・・P+型チャネルストッパ層、4・・・N型拡散領
域、5・・・N+型拡散領域、6・・・コンタクトホー
ル、7・・・接地電位あるいは低電位の金属導体、8・
・・基板コンタクト用P+型拡散領域、9・・・P型シ
リコン基板、10・・・高電位の金属導体、11・・・
層間絶縁膜。FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional semiconductor device. 1... Thin thermal oxide film, 2... Field oxide film, 3
P+ type channel stopper layer, 4... N type diffusion region, 5... N+ type diffusion region, 6... Contact hole, 7... Ground potential or low potential metal conductor, 8...
...P+ type diffusion region for substrate contact, 9...P type silicon substrate, 10...high potential metal conductor, 11...
Interlayer insulation film.
Claims (1)
基準高電圧制御用として逆方向に挿入されるPN接合型
ダイオードを有する半導体装置において、前記ダイオー
ドのPN接合の周縁部が厚いフィールド酸化膜の下に延
在して形成されたことを特徴とする半導体装置。In a semiconductor device having a PN junction diode inserted in the opposite direction for controlling a reference high voltage of a memory that requires a high voltage when writing memory contents, the periphery of the PN junction of the diode is located under a thick field oxide film. A semiconductor device characterized in that it is formed in an extended manner.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2140827A JPH0434962A (en) | 1990-05-30 | 1990-05-30 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2140827A JPH0434962A (en) | 1990-05-30 | 1990-05-30 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0434962A true JPH0434962A (en) | 1992-02-05 |
Family
ID=15277644
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2140827A Pending JPH0434962A (en) | 1990-05-30 | 1990-05-30 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0434962A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019189579A1 (en) | 2018-03-30 | 2019-10-03 | 三井化学株式会社 | Polymerizable composition for dental material, and dental material obtained from said composition |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01260863A (en) * | 1988-04-12 | 1989-10-18 | Citizen Watch Co Ltd | P-n junction diode |
-
1990
- 1990-05-30 JP JP2140827A patent/JPH0434962A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01260863A (en) * | 1988-04-12 | 1989-10-18 | Citizen Watch Co Ltd | P-n junction diode |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019189579A1 (en) | 2018-03-30 | 2019-10-03 | 三井化学株式会社 | Polymerizable composition for dental material, and dental material obtained from said composition |
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