JPH04349549A - Correction bit position information output method in memory system with ecc - Google Patents

Abstract

PURPOSE:To eliminate the need of an exclusive bus for outputting correction bit position information, and to contain the number of times of correction in the contents of the outputted correction bit position information. CONSTITUTION:A correction bit position information storage part 13 stores data contained in a memory 14 and correction bit position information having a correction frequency counter corresponding to a position of each bit of a check bit. An error correcting circuit 12 checks whether a bit change exists in the data inputted from the memory 14 and the check bit or not, and in the case the bit change exists, the data in which the bit change is corrected is outputted and by reflecting its correction, the correction bit position information in the correction bit position information storage part 13 is updated. A selecting circuit 15 selects one of an output of the correction bit position information from the correction bit position information storage part 13 and an output of the data from the error correcting circuit 12 as an output to a data bus 21, based on a signal on a system bus 20.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention detects and corrects bit garbled bits in stored data and outputs the corrected data.
Corrected bit position information output method in a memory system with ECC that outputs corrected bit position information (the contents of the corrected bit position information will be described later) from a memory system with ECC (memory system with ECC connected to a system bus) Regarding.

0002

[Background Art] In recent memory systems, program processing results become meaningless due to bit corruption caused by soft errors (soft errors have a low probability of occurrence, but inevitably occur randomly). In order to avoid this, it is becoming essential to configure a memory system with ECC. In addition, in general, E
SEC-DE is used for check bit generation and error correction (including detection) in memory systems with CC.
D (Single Error Correct-
Double Error Detect) Hamming code system is used. When this coding system is used, it is possible to correct 1-bit garbled bits in 1-word data stored in memory and its check bits, and 2-bit garbled bits can be corrected. can be detected when it occurs.

[0003] In such a memory system with ECC, correction bit position information (bits in each bit of data and check bits in memory) is used as a guideline for replacing memory elements where soft errors occur frequently. Information indicating the position of a bit that has been corrupted and is subject to correction.In addition, in the corrected bit position information output method in the memory system with ECC of the present invention, the number of times that the bit has been subject to correction (number of corrections) is also indicated. It is desirable to output the following information periodically.

Therefore, a method for outputting corrected bit position information in a memory system with ECC is required.

FIG. 4 is a block diagram showing the structure of an example of a corrected bit position information output method in a conventional memory system with ECC of this type. Referring to this figure, the operation of the corrected bit position information output method in the conventional memory system with ECC will be described.

■ Operation when data write is instructed from the system bus 40 (data bus 41 and address bus 42) to the memory system 30 with ECC

The check bit generation circuit 31 receives data from the data bus 41, and the memory 34 receives data from the address bus 4.
2, input the address of the area where the data is to be stored.

The check bit generation circuit 31 generates check bits for data input from the data bus 41, and outputs both the input data and the generated check bits to the memory 34.

The memory 34 stores the data and check bits input from the check bit generation circuit 31 in the area of the address input from the address bus 42.

■ Operation when the memory system 30 with ECC is instructed to read data from the system bus 40

The memory 34 receives from the address bus 42 the address of an area in which data to be outputted to the data bus 41 is stored, and outputs the data and check bits in the area of that address to the error correction circuit 32.

The error correction circuit 32 checks whether the data input from the memory 34 and the check bits are garbled. If no bit corruption has occurred in this check, the data is output to the data bus 41 as is. If bit garbled occurs in the above check, the bit garbled is corrected and the data is output to the data bus 41, and information indicating the position of the corrected bit is stored in the corrected bit position information storage unit 33. Output.

When the corrected bit position information storage unit 33 receives information indicating the corrected bit position, it sets the corrected bit flag corresponding to the corrected bit position to 1, and stores the stored corrected bit position information ( A set of correction bit flags corresponding to each bit position of data and check bits is updated.

■ Operation when the memory system 30 with ECC is instructed to output corrected bit position information from the service bus 43

The corrected bit position information storage section 33 receives an instruction from the service bus 43, outputs the stored corrected bit position information to the service bus 43, and after outputting the stored content (corrected bit position information) (set all correction bit flags to 0).

[0016] The corrected bit position information output method in such a conventional memory system with ECC requires a dedicated bus (such as a service bus) for outputting corrected bit position information in addition to the system bus. This method could only be used in large information processing systems that could have their own dedicated bus.

[0017]

[Problem to be solved by the invention] The above-mentioned conventional ECC
The corrected bit position information output method in memory systems with fixed bits requires a dedicated bus to output the corrected bit position information, so it is only adopted in large information processing systems that can provide such a dedicated bus. I couldn't. Therefore, in a small information processing system that does not have a dedicated bus, it is not possible to output corrected bit position information, and it is not possible to recognize the position of the corrupted bit (bit that is the target of correction). There was a drawback.

Furthermore, since the content of the corrected bit position information that is output is only information indicating the position of the bit targeted for correction, there is a drawback that the number of corrections cannot be recognized (the number of corrections cannot be recognized). In order to do this, it was necessary to perform counting processing based on corrected bit position information at regular intervals using a specific program).

In view of the above points, it is an object of the present invention to make it possible to output corrected bit position information even in a small information processing system without requiring a dedicated bus for outputting corrected bit position information. An object of the present invention is to provide a method for outputting corrected bit position information in a memory system with ECC that can include the number of corrections in the contents of corrected bit position information.

[0020]

[Means for Solving the Problems] A correction bit position information output method in a memory system with ECC of the present invention includes a memory for storing data and check bits, and a correction number counter corresponding to the position of each bit of data and check bits. a corrected bit position information storage unit that stores corrected bit position information having a corrected bit position information; a check bit generation circuit that generates check bits for data input from the system bus and outputs the data and the check bits to the memory; It is checked whether or not the input data and check bits have garbled bits, and if there is garbled bits, the data with the garbled bits corrected is output, and the corrected bit position information in the corrected bit position information storage unit is reflected by the correction. an error correction circuit that updates the error correction circuit, and outputs either the correction bit position information from the correction bit position information storage unit or the data output from the error correction circuit to the data bus based on the signal on the system bus. and a selection circuit for selecting the selected one.

[0021]

[Operation] In the corrected bit position information output method in the memory system with ECC of the present invention, the memory stores data and check bits, and the corrected bit position information storage section stores the number of corrections corresponding to the position of each bit of the data and check bits. A check bit generating circuit generates a check bit for data input from the system bus and outputs the data and the check bit to the memory, and an error correction circuit stores the data input from the memory and the check bit position information having a counter. Check whether or not there is bit garble in the check bit, and if there is bit garble, output data with the bit garble corrected, and update corrected bit position information in the corrected bit position information storage unit to reflect the correction; A selection circuit selects either the output of corrected bit position information from the corrected bit position information storage unit or the output of data from the error correction circuit as output to the data bus based on the signal on the system bus.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a corrected bit position information output method in a memory system with ECC according to the present invention.

The corrected bit position information output method in the ECC-equipped memory system of this embodiment is configured to include an ECC-equipped memory system 10 and a system bus 20.

The memory system 10 with ECC includes a check bit generation circuit 11, an error correction circuit 12, a correction bit position information storage section 13, a memory 14, and a selection circuit 15.

The system bus 20 includes a data bus 21 and
It is configured to include an address bus 22 and an output selection signal line 23.

FIG. 2(a) is a diagram showing the configuration of the memory 14. The memory 14 includes a data section for storing data in which one word consists of a certain number of bits (in this case, 8 bits), and a section for detecting and correcting bit garbled bits of the corresponding data and itself. and a check bit section that stores check bits.

FIG. 2(b) is a diagram showing the configuration of the corrected bit position information storage section 13. The corrected bit position information storage unit 13 stores corrected bit position information consisting of data section counter information and check bit section counter information. The data section counter information has a correction number counter corresponding to the position of each bit of the data section in the memory 14,
The check bit section counter information has a correction number counter corresponding to the position of each bit of the check bit section in the memory 14. The correction number counter is a counter that is incremented by 1 every time a bit in the memory 14 located at a corresponding position is garbled.
(Initial value is 0), the counter indicates the position of the bit to be corrected and the number of corrections.

FIGS. 3A to 3C are diagrams for explaining address spaces in an information processing system in which a plurality of memory systems 10 with ECC are connected to a system bus 20.

Next, the E of this embodiment configured as described above
The operation of the corrected bit position information output method in the memory system with CC will be explained.

■ Operation when data write is instructed from the system bus 20 to the memory system 10 with ECC

The check bit generation circuit 11 receives data from the data bus 21, and the memory 14 receives data from the address bus 2.
2, input the address of the area where the data is to be stored.

The check bit generation circuit 11 generates check bits for data input from the data bus 21, and outputs both the input data and the generated check bits to the memory 14.

The memory 14 stores the data and check bits input from the check bit generation circuit 11 in the area of the address input from the address bus 22.

■ Operation when the memory system 10 with ECC is instructed to read data from the system bus 20

The memory 14 receives from the address bus 22 the address of an area in which data to be output to the system bus 20 is stored, and outputs the data and check bits in the area of that address to the error correction circuit 12.

The selection circuit 15 also connects the output selection signal line 2
3, an output selection signal (hereinafter referred to as a data output selection signal) indicating "designation of output of data stored in the data section in the memory 14" is input.

The error correction circuit 12 checks whether the data input from the memory 14 and the check bits are garbled. If no bit corruption has occurred in this check, the data is output to the selection circuit 15 as is. If bit garbled occurs in the above check, the bit garbled is corrected and the data is output to the selection circuit 15, and information indicating the position of the corrected bit is stored in the corrected bit position information storage section 13.
Output to.

When the corrected bit position information storage section 13 receives information indicating the corrected bit position, it adds 1 to the correction number counter corresponding to the corrected bit position, and stores the stored corrected bit position information. Update.

The selection circuit 15 selects "data output (reading)" based on the designation of the data output selection signal input from the output selection signal line 23 and transfers the data input from the error correction circuit 12 to the data bus 21. Output.

■ Operation when the memory system 10 with ECC is instructed to output corrected bit position information from the system bus 20

The correction bit position information storage section 13 stores the address of the area in which the information to be output to the system bus 20 (either the data section counter information or the correction number counter in the check bit section counter information) is stored. Input from bus 22.

The selection circuit 15 also outputs an output selection signal (hereinafter referred to as a correction bit position information output selection signal) indicating "designation of output of the correction bit position information stored in the correction bit position information storage unit 13". It is input from the selection signal line 23.

The correction bit position information storage unit 13 stores the address input from the address bus 22 in the ECC to which it belongs.
(Generally, a plurality of memory systems 10 with ECC are connected to the system bus 20 (see FIG. 3(a))), and the correction bit position is confirmed to be the address assigned to the memory system 10 with ECC. Which correction number counter in the information should be output is selected based on the address, and the corresponding correction number counter is output to the selection circuit 15.

The corrected bit position information storage section 13 that has outputted the predetermined correction number counter in the corrected bit position information clears the outputted content (correction number counter) (sets it to 0).

The selection circuit 15 selects "output of corrected bit position information" based on the specification of the corrected bit position information output selection signal input from the output selection signal line 23, and selects "output of corrected bit position information" based on the specification of the corrected bit position information output selection signal input from the output selection signal line 23 The value of the correction number counter is output to the data bus 21.

Next, a plurality of ECC equipped memory systems 1
The address space (address space when viewed from the system bus 20) in the information processing system in which 0 is connected to the system bus 20 will be described.

As shown in FIG. 3(a), a plurality of memory systems 10 with ECC (memory system 10 with ECC)
-1 and 10-2, etc.) are connected to the system bus 20, and the addresses of the memory system 10-1 with ECC are "0000 to 0FFF (16
Shown in base numbers. (Same below)” address is assigned,
As the address of the memory system 10-2 with ECC, "
It is assumed that addresses 1000 to 1FFF are assigned.

In the information processing system as shown in FIG. 3(a), the address space for each ECC-equipped memory system 10 is determined as shown in FIG. 3(b) or (c) depending on the content of the output selection signal on the output selection signal line 23. It becomes as shown in .

■ When a data output selection signal is applied to the output selection signal line 13 (see FIG. 3(b))

005
1] In this case, the address “0000 to 0FFF” is memory 1 in the ECC memory system 10-1.
4, and the addresses "1000 to 1FFF" correspond to the address space of the memory 14 in the memory system 10-2 with ECC.

■ When the correction bit position information output selection signal is applied to the output selection signal line 13 (the number of correction count counters in the correction bit position information is 13 as shown in FIG. 2(b)). ) (see Figure 3(c))

[0053] In this case, "0000~000C"
The address of the address corresponds to the address space of the correction bit position information storage section 13 in the memory system with ECC 10-1, and each correction number counter in the data section counter information and check bit section counter information is set to "0000 to 000."
C" addresses are sequentially assigned.

Further, the addresses "1000 to 100C" correspond to the address space of the correction bit position information storage section 13 in the memory system with ECC 10-2, and each address in the data section counter information and check bit section counter information Addresses "1000 to 100C" are sequentially assigned to the correction number counter.

[0055] Note that the mode as shown in Fig. 3 (the same EC
Regarding the memory system 10 with C, the address space of the memory 14 and the address space of the corrected bit position information storage unit 13 are shared (a mode in which addresses are shared between the address space of the memory 14 and the address space of the corrected bit position information storage unit 13). It is also possible to configure the present invention by allocating different addresses to the address space. In that case, as shown by the broken arrow in FIG. make a choice between. In this case, the output selection signal line 23
becomes unnecessary.

[0056]

[Effects of the Invention] As explained above, the present invention eliminates the need for a dedicated bus for outputting corrected bit position information, thereby enabling small-sized information processing that does not have such a dedicated bus other than a system bus. The system also has the advantage of being able to output corrected bit position information and recognizing the position of bits where garbled bits have occurred.

[0057] Furthermore, by providing a correction number counter in the correction bit position information, the number of corrections can be easily recognized. This has the effect that the number of corrections can be recognized without having to do so.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

2(a) is a diagram showing the configuration of a memory in FIG. 1, and FIG. 2(b) is a diagram showing the configuration of a correction bit position information storage unit in FIG. 1. FIG.

FIG. 3 is a diagram for explaining an address space in an information processing system in which a plurality of memory systems with ECC shown in FIG. 1 are connected to a system bus.

FIG. 4 is a block diagram showing the configuration of an example of a corrected bit position information output method in a conventional memory system with ECC.

[Explanation of symbols]

10, 10-1, 10-2 Memory system with ECC 11 Check bit generation circuit 12 Error correction circuit 13 Correction bit position information storage section 14 Memory 15 Selection circuit 20 System bus 21 Data bus 22 Address bus 23 Output selection signal line

Claims (1)

[Claims] 1. A memory for storing data and check bits, a correction bit position information storage unit for storing correction bit position information having a correction number counter corresponding to the position of each bit of the data and check bits, and a correction bit position information storage section for storing correction bit position information; a check bit generation circuit that generates a check bit for input data and outputs the data and the check bit to the memory; and a check bit generation circuit that checks whether or not the data and check bit input from the memory have garbled bits. an error correction circuit that outputs data with corrected bit garbled bits and updates corrected bit position information in the corrected bit position information storage unit to reflect the correction; Correction in a memory system with ECC, comprising a selection circuit that selects either the output of corrected bit position information from a position information storage unit or the output of data from the error correction circuit as output to a data bus. Bit position information output method.