JPH04349516A - Microcomputer - Google Patents

Abstract

PURPOSE:To obtain a microcomputer which can use properly a power saving reset state that oscillation is stopped, and an oscillatable reset state in accordance with the state. CONSTITUTION:A first reset signal 1 and a second reset signal 2 are connected to an internal reset signal generating part 6 and an oscillation stopping signal generating part 3. While the first reset signal 1 or the second reset signal 2 is being generated, the internal reset signal generating part 6 generates an internal reset signal 7, and sets the connected internal circuit to the reset state. The oscillation stopping signal generating part 3 controls an oscillating circuit 5 by an oscillation stopping signal 4, makes it oscillatable by the generation of a first reset signal 1 and stops the oscillation by the generation of a second reset signal 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in microcomputers, and particularly relates to the operation of an oscillation circuit using a reset signal.

0002

[Prior Art] Conventionally, when a microcomputer is reset, general circuits are reset, and oscillation is started in order to shorten the oscillation stabilization time, or oscillation is stopped in order to save power. One of these methods was used.

0003

In the conventional microcomputer described above, the oscillation circuit is fixed to either perform oscillation operation or stop oscillation during the reset period. However, in the reset operation of a microcomputer, it is desired to use the above two types of operations depending on the situation, and there is a drawback that it is impossible to meet this request.

An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide two types of reset signals for different operations of the oscillation circuit upon reset, a power-saving reset state in which oscillation is stopped and a reset state in which oscillation is possible. The object of the present invention is to provide a microcomputer that can be used depending on the situation.

[0005]

[Means for Solving the Problems] The present invention provides a microcomputer equipped with an oscillation circuit that generates a clock signal and stops the generation of the clock signal by an oscillation stop signal. first and second reset signals, and an oscillation that stops generating the oscillation stop signal when the first reset signal is generated and starts generating the oscillation stop signal when the second reset signal is generated. comprising a stop signal generation section and an internal reset signal generation section that generates an internal reset signal for resetting an internal circuit when at least one of the first reset signal and the second reset signal is generated. It is characterized by

[0006]

[Operation] The oscillation stop signal generating section stops generating the oscillation stop signal when the first reset signal is generated, and starts generating the oscillation stop signal when the second reset signal is generated. On the other hand, the internal reset signal generating section generates an internal reset signal when either the first reset signal or the second reset signal is generated.

Therefore, by controlling the generation of the first and second reset signals in response to the rise and fall of the power supply, the power-saving reset state in which oscillation is stopped and the reset state in which oscillation is possible can be changed depending on the situation. It becomes possible to use them properly.

[0008]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention.

This embodiment is a microcomputer 10 equipped with an oscillation circuit that generates a clock signal 8 and stops the generation of the clock signal 8 by an oscillation stop signal 4. The first and second reset signals 1 and 2 are generated in response to the downlink, and when the first reset signal 1 is generated, the generation of the oscillation stop signal 4 is stopped, and when the second reset signal 2 is generated. An oscillation stop signal generator 3 that starts generating the oscillation stop signal 4, and an internal reset signal 7 that resets an internal circuit (not shown) when at least one of the first and second reset signals 1 and 2 is generated. The internal reset signal generating section 6 generates an internal reset signal.

The oscillation circuit 5 includes MOS transistors M1 and M2, inverters I1, I2 and I3,
The oscillation stop signal generating section 3 includes a NOR gate G1 and a flip-flop (F/F) F1, and the internal reset signal generating section 6 includes a NOR gate G2 and an inverter I4.

Next, the operation of this embodiment will be explained with reference to the timing diagram of FIG.

First, the first reset signal 1 is generated at the initial rise of the power supply voltage. As a result, the internal reset signal generating section 6 generates the internal reset signal 7 and puts the internal circuits except the oscillation circuit 5 into a reset state. Further, the oscillation stop signal generating section 3 does not generate the oscillation stop signal 4, and the oscillation circuit 5 starts oscillating and enters the first reset state. and,
In synchronization with the release of the first reset signal 1, the internal reset signal generator 6 releases the internal reset signal 7 and enters the normal operating state.

Next, a second reset signal 2 is generated when the power supply voltage falls. As a result, the internal reset signal generating section 6 generates the internal reset signal 7 and puts the internal circuits except the oscillation circuit 5 into a reset state. Further, the oscillation stop signal generating section 3 generates an oscillation stop signal 4, and the oscillation circuit 5 stops oscillation and enters a second reset state.

While the microcomputer 10 maintains the second reset state, if the power supply voltage rises to a voltage that allows normal operation, the first reset signal 1 is generated and the oscillation stop signal is activated. The generator 3 cancels the oscillation stop signal 4 and enters the first reset state, and thereafter shifts to the normal operating state in the same manner as when the initial power supply voltage rises.

[0016]

As explained above, the present invention has a simple circuit that generates the first reset signal and the second reset signal, thereby controlling the oscillation or oscillation of the oscillation circuit depending on which reset signal is in the reset state. This has the effect of making it possible to use different stops.

Therefore, according to the present invention, it is possible to save power by using a reset state in which oscillation is stopped in a microcomputer when the power supply of a set equipped with a microcomputer is momentarily cut off or during a power outage, and when the set is powered on. By using a reset state that allows oscillation to initialize a microcomputer, it is possible to simultaneously reduce unnecessary oscillation stabilization time, which is highly effective.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing main parts of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation.

[Explanation of symbols]

1 First reset signal 2 Second reset signal 3 Oscillation stop signal generation section 4 Oscillation stop signal 5 Oscillation circuit 6 Internal reset signal generation section 7 Internal reset signal 8 Clock signal 10 Microcomputer F1 Flip-flop (F/F) G1, G2 Noah Gate I1 to I4 Inverter M1, M2 MOS transistor R1 resistance X1, X2 terminal

Claims (1)

[Claims] 1. In a microcomputer equipped with an oscillation circuit that generates a clock signal and stops the generation of the clock signal by an oscillation stop signal, first and second reset signals are generated in response to rising and falling of a power supply. an oscillation stop signal generating section that stops generating the oscillation stop signal when the first reset signal is generated and starts generating the oscillation stop signal when the second reset signal is generated; A microcomputer comprising: an internal reset signal generating section that generates an internal reset signal for resetting an internal circuit when at least one of the first reset signal and the second reset signal is generated.