JP3665624B2 - Microcontroller - Google Patents

Description

[0001]
[Field of the Invention]
The present invention relates to a microcontroller, and more particularly to a microcontroller having a clock signal supply / stop function.
[0002]
[Prior art]
A conventional microcontroller (hereinafter referred to as a microcomputer) includes a master block such as a CPU, a slave block controlled by the master block, and a clock signal control means for controlling supply / stop of a clock signal to the slave block. Is done. The clock signal control means controls supply / stop of the clock signal in response to a clock control signal (clock stop request signal) output from the master block. As described above, in the conventional microcomputer, power consumption is reduced by stopping the supply of the clock signal to the slave block that does not need to supply the clock signal. In the conventional microcomputer, when the access is completed, the slave block outputs a response signal indicating that the access to the master block is completed, and the master block receives the response signal and terminates the access operation. It was.
[0003]
[Problems to be solved by the invention]
However, in the conventional microcomputer, when the master block accesses the slave block for which the supply of the clock signal is stopped, the slave block which is inactive cannot output the response signal. The master block remains in the access operation. For this reason, the entire microcomputer consumes wasted power because only the master block maintains the access operation without performing predetermined processing, and there has been a problem that it is not possible to reduce power consumption.
[0004]
[Means for Solving the Problems]
The microcontroller according to the present invention is made in order to solve the above-mentioned problem, and a typical example is that when access is made to a functional block for which supply of a clock signal is stopped, Instead of the function block, response means for outputting a response signal indicating that the access to the function block is abnormal is provided.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0006]
(First embodiment)
FIG. 1 is a circuit block diagram showing a configuration of a microcontroller (hereinafter referred to as a microcomputer) according to a first embodiment of the present invention. The microcomputer according to the present embodiment selectively supplies a master block 101 that controls the entire microcomputer, a plurality of functional blocks (slave blocks 102 and 103) that execute predetermined functions, and a clock signal CLOCK to each functional block. Clock signal control means 106 and 107, and response means (default slave block 104) for outputting a response signal RESP in place of the functional block for which the supply of the clock signal is stopped. The master block 101 and the slave blocks 102 and 103 are connected by an address signal line 112, a data signal line 113, a read / write signal line 108, and a response signal line 109. The master block 101 and the default slave block 104 are connected by an address signal line 112 and a response signal line 109.
[0007]
The master block 101 is, for example, a central processing unit (CPU). The master block 101 generates an address signal ADDR associated with each functional block, and transmits the address signal ADDR to each functional block via the address signal line 112. At this time, the address signal ADDR is also transmitted to the default slave block 104 via the address signal line 112. Further, the master block 101 exchanges data signals DATA with each functional block via the data signal line 113. Further, the master block 101 generates a read / write signal W / R that indicates a read cycle or a write cycle, and transmits the read / write signal W / R to each functional block via the read / write signal line 108. Further, the master block 101 generates clock control signals (clock stop request signals) CKSTOP1 and CKSTOP2 for instructing supply / stop of the clock signal, and sends them to the clock signal control means 106 and 107 via the clock control signal lines 110 and 111. Send. In this embodiment, the clock signal supply is instructed when the logical values of the clock control signals CKSTOP1 and CKSTOP2 are “0”, and the clock signal is supplied when the logical values of the clock control signals CKSTOP1 and CKSTOP2 are “1”. Instruct to stop. Here, the logical value “1” of the clock control signal corresponds to a high level (hereinafter, “H”) potential, and the logical value “0” of the clock control signal is low (hereinafter, “L”). ).
[0008]
The functional block (slave blocks 102 and 103) is, for example, a memory. The slave blocks 102 and 103 output a response signal RESP indicating the completion status of the bus access to the master block 101 via the response signal line 109. Here, the response signal RESP will be described with reference to FIG. FIG. 2 is a table showing the relationship between the logical value of the response signal RESP and the bus access completion state. In the present embodiment, the response signal RESP is composed of 2 bits. The response signal RESP indicates “no access“ NO ”” when the logical value is “00”, indicates “normal termination“ OK ”” when the logical value is “01”, and indicates “normal” “10” when the logical value is “10”. Abnormal termination “ERR” is indicated, and “reserved” is indicated when the logical value is “11”.
[0009]
The clock signal control means 106 and 107 (both shown in FIG. 1) control the supply / stop of the clock signal to the slave blocks 102 and 103 in response to the clock control signals CKSTOP1 and CKSTOP2 generated by the master block 101. To do. The clock signal control means 106 and 107 are composed of OR circuits (OR circuits). Hereinafter, the clock signal control means 106 and 107 are referred to as OR circuits 106 and 107. The clock control signal CKSTOP1 is input to one of the two input terminals of the OR circuit 106, and the clock signal CLOCK is input to the other input terminal. The output signal CK1 of the OR circuit 106 is supplied to the slave block 102. The OR circuit 106 outputs the clock signal CK1 having the same waveform as the clock signal CLOCK when the clock control signal CKSTOP1 is “L” (logic value “0”), that is, when the supply of the clock signal is instructed. When the signal CKSTOP1 is “H” (logic value “1”) (when the stop of the supply of the clock signal is instructed), a signal of “H” (logic value “1”) is output. That is, when the clock control signal CKSTOP1 is “H” (logic value “1”), the supply of the clock signal to the slave block 102 is stopped.
[0010]
The clock control signal CKSTOP2 is input to one input terminal of the two input terminals of the OR circuit 107, and the clock signal CLOCK is input to the other input terminal. The output signal CK2 of the OR circuit 107 is supplied to the slave block 103. The OR circuit 107 outputs the clock signal CK2 having the same waveform as the clock signal CLOCK when the clock control signal CKSTOP2 is “L” (logical value “0”), that is, when the supply of the clock signal is instructed. When the signal CKSTOP2 is “H” (logic value “1”) (when the stop of the supply of the clock signal is instructed), a signal of “H” (logic value “1”) is output. That is, when the clock control signal CKSTOP2 is “H” (logic value “1”), the supply of the clock signal to the slave block 103 is stopped.
[0011]
The default slave block 104 outputs a response signal RESP to the master block 101 based on the address signal ADDR and the clock control signal CKSTOP1 or CKSTOP2. When the supply of the clock signal CK1 to the slave block 102 is stopped, that is, when the clock control signal CKSTOP1 is “H” (logical value “1”), the default slave block 104 responds instead of the slave block 102. RESP “10” (abnormal end “ERR”) is output to the master block 101. The default slave block 104 replaces the slave block 103 when the supply of the clock signal CK2 to the slave block 103 is stopped, that is, when the clock control signal CKSTOP2 is “H” (logical value “1”). The response signal RESP “10” (abnormal end “ERR”) is output to the master block 101.
[0012]
Here, the default slave block 104 will be described in more detail with reference to FIG. FIG. 3 is a circuit block diagram showing a configuration of default slave block 104 of the microcomputer shown in FIG. The default slave block 104 includes decoding means (decoding unit 301) for decoding the address signal ADDR, and a logic circuit unit 302 for outputting a SELECT signal based on the clock control signals CKSTOP1 and CKSTOP2 and the output signals sel0 to sel2 of the decoding unit 301. And a functional block 303 that outputs a response signal RESP in response to the SELECT signal.
[0013]
The decoding unit 301 includes decoding circuits 304, 305, and 306. In the present embodiment, the decode circuit 304 outputs a sel1 signal of “H” (logical value “1”) when the address signal ADDR corresponds to the slave block 102 (FIG. 1), and the address signal ADDR is When not corresponding to the slave block 102, the sel1 signal of “L” (logic value “0”) is output. When the address signal ADDR corresponds to the slave block 103, the decode circuit 305 outputs a signal of “H” (logic value “1”) as the sel2 signal, and the address signal ADDR does not correspond to the slave block 103. The sel2 signal of “L” (logic value “0”) is output. The decode circuit 306 outputs a sel0 signal of “H” (logical value “1”) when the address signal ADDR does not correspond to either the slave block 101 or 102, and the address signal ADDR is output from the slave block 101 (FIG. When it corresponds to either 1) or 102 (FIG. 1), the sel0 signal of “L” (logical value “0”) is output.
[0014]
The logic circuit unit 302 includes AND circuits (AND circuits) 307 and 308 and an OR circuit (OR circuit 309). The AND circuit 307 receives the clock control signal CKSTOP1 and the sel1 signal, and the AND circuit 308 receives the clock control signal CKSTOP2 and the sel2 signal. The OR circuit 309 receives the output signal of the AND circuit 307, the output signal of the AND circuit 308, and the output sel0 signal of the decode circuit 306, and outputs the result of the logical sum operation to the functional block 303 as a SELECT signal. . The SELECT signal is generated when the clock control signal CKSTOP1 is “H” (logic value “1”) and the signal sel1 is “H” (logic value “1”), or the clock control signal CKSTOP2 is “H” (logic value “1”). 1 ”) and the signal sel2 is“ H ”(logic value“ 1 ”) or the signal sel0 is“ H ”(logic value“ 1 ”). “1”), and “L” (logical value “0”) when none of them apply. That is, the SELECT signal is used when the slave block 102 (FIG. 1) in which the supply of the clock signal CK1 is stopped is accessed or in the slave block 103 (FIG. 1) in which the supply of the clock signal CK2 is stopped. ), Or when there is no functional block corresponding to the address signal ADDR, it becomes “H” (logical value “1”), and it does not correspond to either “L” (logical value “0”). The functional block 303 outputs a response signal RESP “10” (abnormal termination “ERR”) when the SELECT signal is “H” (logical value “1”).
[0015]
Next, the operation of the microcontroller according to the present embodiment will be described with reference to FIG. FIG. 4 is an operation waveform diagram showing the operation of the microcontroller according to the first embodiment. FIG. 4 shows the clock signal CLOCK in order from the top, the input / output signal of the master block 101 (denoted as “A” in the figure), the input / output signal of the slave block 102 (denoted as “B” in the figure), and the default slave block. 104 shows an internal signal (denoted as “C” in the figure). The horizontal direction in FIG. 4 indicates time. The clock control signal CKSTOP1 is “L” (logical value “0”) until time t4, and becomes “H” (logical value “1”) from time t4. In other words, the clock signal CK2 is supplied to the slave block 102 until time t4, and the supply of the clock signal CK2 to the slave block 102 is stopped from time t4 (CK1). Here, a case where the access of the master block 101 to the slave block 102 is normally completed (time t1 to time t3) and a case where the access of the master block 101 to the slave block 102 is abnormally terminated (time t5 to time t7) will be described. To do.
[0016]
At time t1, the master block 101 outputs an address signal ADDR corresponding to the slave block 102 and a read / write signal W / R instructing “read access”, and enters a read cycle for the master block 102. At this time, the clock control signal CKSTOP1 is “L” (logical value “0”), and the slave block 102 is supplied with the clock signal CK1. The master block 102 is in an operating state because the clock signal CK1 is supplied.
[0017]
The sel1 signal of the default slave block 104 is “H” (logical value “1”) because the address signal ADDR is an address corresponding to the slave block 102, but the clock control signal CKSTOP1 is “L” (logical value “1”). Therefore, the SELECT signal remains “L” (logical value “0”).
[0018]
At time t2, when the data is normally output from the slave block 102, the slave block 102 outputs a response signal RESP of “01” (normal end “OK”). At time t3, the read cycle ends normally.
[0019]
At time t4, the master block 101 outputs a clock control signal CKSTOP1 of “H” (logic value “1”). When the clock control signal CKSTOP1 becomes “H” (logic value “1”), the output signal CK1 of the OR circuit 106 maintains “H” (logic value “1”). That is, when the clock control signal CKSTOP1 becomes “H” (logic value “1”), the supply of the clock signal CK1 to the slave block 102 is stopped. When the supply of the clock signal is stopped, the slave block 102 becomes inactive (not operating).
[0020]
At time t5, the master block 101 outputs an address signal ADDR corresponding to the slave block 102 and a read / write signal W / R instructing “write access”. However, since the slave block 102 is in an inactive state, it not only fetches data but also outputs a response signal RESP of “10” (abnormal termination “ERR”) indicating that the write access is abnormal. I can't. At this time, in the default slave block 104, since the address signal ADDR corresponds to the slave block 102, the sel1 signal becomes “H” (logical value “1”). The AND circuit 307 generates “H” (logic value “1”) based on the sel1 signal of “H” (logic value “1”) and the clock control signal CKSTOP1 of “H” (logic value “1”). A SELECT signal is output.
[0021]
At time t6, the functional block 303 outputs a response signal RESP of “10” (abnormal end “ERR”) in response to the SELECT signal of “H” (logical value “1”). As described above, the default slave block 104 outputs the response signal RESP indicating that the write access is abnormal (error) to the master block 101 instead of the slave block 102 in which the supply of the clock signal CK2 is stopped.
[0022]
At time t7, in response to the response signal RESP of “10” (abnormal end “ERR”) output from the default slave block 104, the master block 101 ends the write access to the slave block.
[0023]
As described above, when the microcontroller according to the present embodiment accesses a functional block (for example, the slave block 102) for which the supply of the clock signal is stopped, instead of the functional block, When access is made to a function block for which supply of a clock signal is stopped because it has response means (default slave block 104) for outputting a response signal RESP indicating that access to the function block is abnormal However, the access operation of the master block (CPU or the like) can be stopped. That is, since the microcontroller according to the present embodiment has the response means (default slave block 104) described above, the master block is accessed when access is made to the functional block for which the supply of the clock signal is stopped. However, it is possible to prevent power consumption due to maintaining the access operation and to reduce power consumption.
[0024]
(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 5 is a circuit block diagram showing a configuration of a microcontroller (hereinafter referred to as a microcomputer) according to the second embodiment of the present invention. The microcomputer according to the present embodiment differs from the microcomputer according to the first embodiment shown in FIG. 1 in that the supply of a clock signal is stopped for each functional block (slave blocks 502 and 503). However, response means capable of outputting the response signal RESP is provided. The default slave block 504 outputs a response signal RESP indicating that the access is abnormal (error) only when there is no functional block corresponding to the address signal ADDR output from the master block 101.
[0025]
Here, the slave block 502 will be described in detail with reference to FIG. FIG. 6 is a circuit diagram showing a configuration of a slave block of the microcontroller according to the second embodiment of the present invention. Note that the slave block 503 has the same configuration as the slave block 502. The slave block 502 is obtained by further adding a stop control unit 600 to the slave block 102 of the first embodiment, and includes a decode circuit 611 that decodes the address signal ADDR, a circuit block 610 that executes a predetermined function, Instead of the circuit block 610, a stop control unit 600 that outputs a response signal RESP is configured. The stop control unit 600 generates a selection signal sel based on the clock control signal CKSTOP1 and the decoding result (SELECT signal) of the address signal ADDR output from the decoding circuit 611, and responds to the selection signal sel. Then, the selection circuit 602 selects and outputs either a fixed value (in this case, “abnormal termination“ ERR ””) indicating the bus access completion state or a bus access completion state “no access“ NO ””. And a response signal output circuit 607 that outputs a response signal RESP.
[0026]
The selection signal generator 601 includes an inverter 603 that inverts and outputs the clock control signal CKSTOP1, an OR circuit (OR circuit) 604 that performs an OR operation between the clock signal CLOCK and the output signal of the inverter 603, and an address signal ADDR. A flip-flop circuit (hereinafter referred to as an F / F circuit) 605 that outputs a signal based on the SELECT signal that is the decoding result of the signal and the output signal of the OR circuit 604, and the SELECT signal and the output signal of the F / F circuit 605 And a logical product circuit (AND circuit) 606 that performs a logical product operation based on the result and outputs the result to the selection circuit 602 as a selection signal sel.
[0027]
When the master block 101 accesses the slave block 502 to which the supply of the clock signal CK1 is stopped, the selection signal generation unit 601 sends a signal indicating the completion state of access to the selection circuit 602 (here, “ The selection signal sel instructing to output the abnormal end “ERR” ”is output. In other cases, the selection signal sel instructing the selection circuit 602 to output the access completion state “no access“ NO ”” is output. Specifically, the clock control signal CKSTOP1 is “H” (logical value “1”), and the address signal ADDR corresponds to the slave block 102 (that is, the SELECT signal is “H” (logical value). When “1”), the selection signal sel of logical value “1” is output. When (clock stop request signal CKSTOP1, SELECT signal) = (0, 0), (0, 1), (1, 0), a selection signal sel having a logical value “0” is output.
[0028]
The selection circuit 602 outputs “abnormal termination“ ERR ”” when the selection signal sel is the logical value “1”, and outputs “no access“ NO ”” when the selection signal sel is the logical value “0”. The OR circuit 607 performs an OR operation between the output signal of the selection circuit 602 and the RESP1 signal of the memory 610, and outputs the result as a response signal RESP.
[0029]
Next, the operation of the microcomputer according to the present embodiment will be described with reference to FIG. FIG. 7 is an operation waveform diagram showing the operation of the microcomputer according to the second embodiment of the present invention. FIG. 7 shows a clock signal CLOCK in order from the top, an input / output signal of the master block 101 (represented as “A” in the figure), an input / output signal of the slave block 502 (represented as “B” in the figure), and a stop control unit. Each signal (denoted as “C” in the figure) is shown. The horizontal direction in FIG. 7 indicates time. The clock control signal CKSTOP1 is “L” (logic value “0”) until time t1, and becomes “H” (logic value “1”) from time t1. That is, the clock signal CK1 is supplied to the circuit block 610 until time t1, and the supply of the clock signal CK1 to the circuit block 610 is stopped from time t1. Here, a case where the master block 101 accesses the circuit block 610 when the supply of the clock signal to the circuit block 610 is stopped (time t1 to time t4) will be described.
[0030]
At time t1, the master block 101 outputs a clock control signal CKSTOP1 of “H” (logic value “1”). When the clock control signal CKSTOP1 becomes “H” (logic value “1”), the output signal CK1 of the OR circuit 106 maintains “H”. That is, when the clock control signal CKSTOP1 becomes “H” (logical value “1”), the supply of the clock signal CK1 to the circuit block 610 is stopped. The circuit block 610 enters an inactive state (non-operating state) when the supply of the clock signal CK1 is stopped. At this time, the output signal SCK1 of the OR circuit 604 is a signal having the same waveform as the clock signal CLOCK because the clock control signal CKSTOP1 is inverted by the inverter 603.
[0031]
At time t2, the master block 101 outputs an address signal ADDR corresponding to the slave block 502 and a write / read signal W / R instructing “write access”. However, since the memory 610 is in an inactive state, the response signal RESP ““ 10 ”(abnormal end“ ERR ”)” indicating that the write access is abnormal is output in addition to the data capture. I can't. At this time, the SELECT signal (decoded result of the address signal ADDR) input to the stop control unit 600 is “H” (logical value “1”).
[0032]
At time t 3, the SRESP signal “10” (abnormal termination “ERR”) is output from the selection circuit 602. Here, this operation will be described in detail. The clock control signal CKSTOP1 of “H” (logic value “1”) is inverted by the inverter 603 and input to the OR circuit 604 as a signal of “L” (logic value “0”). The OR circuit 604 performs a logical OR operation between the output signal of the inverter 603 and the clock signal CLOCK, and outputs a signal SCK 1 having the same waveform as the clock signal CLOCK to the F / F circuit 605. Here, the SELECT signal of “H” (logic value “1”) is input to the F / F circuit 605. The F / F circuit 605 takes in the SELECT signal of “H” (logic value “1”) at the rising edge of the SCK1 signal, and outputs the signal of “H” (logic value “1”) to the AND circuit 606. The AND circuit 606 performs an AND operation on the output signal of the F / F circuit 605 and the SELECT signal of “H” (logical value “1”), and selects the selection signal sel of “H” (logical value “1”). Is output to the selection circuit 602. The selection circuit 602 outputs a SRESP signal of “10” (abnormal termination “ERR”) in response to a selection signal of “H” (logical value “1”). The OR circuit 607 outputs the SRESP signal of “10” (abnormal termination “ERR”) output from the selection circuit 602 as the response signal RESP.
[0033]
At time t 4, the master block 101 responds to the response signal RESP “10” (abnormal termination “ERR”) output from the stop control unit 600, and the address signal ADDR and write signal corresponding to the slave block 502 are written. The output of the read signal W / R is stopped, and the write access to the slave block 502 is ended.
[0034]
As described above, the microcontroller according to the present embodiment replaces the circuit block when access is made to the functional block (for example, the circuit block 610) for which the supply of the clock signal is stopped, Since there is a response means (stop control unit 600) that outputs a response signal RESP indicating that the access is abnormal, the master block 101 is accessed when access is made to a functional block for which the supply of the clock signal is stopped. However, it is possible to prevent power consumption due to maintaining the access operation and to reduce power consumption. Further, since the microcontroller according to the present embodiment has a response means for each functional block (slave blocks 102 and 103), a different response signal can be set for each functional block, and the degree of freedom of microcomputer control can be set. Increase.
[0035]
Here, another configuration of the stop control unit of the microcontroller according to the present embodiment will be described. FIG. 8 is a circuit diagram showing another configuration of a stop control unit of a microcontroller (hereinafter referred to as a microcomputer) according to the second embodiment of the present invention. The microcomputer according to the present embodiment is different from the stop control unit shown in FIG. 6 in that the input signal of the selection circuit 602 is changed to be supplied from the circuit block 610. A signal input to the circuit block 602 is output from the RESP_REG terminal of the circuit block 610. A signal input to the selection circuit 602 can be set in the circuit block 610 by an external program input.
[0036]
【The invention's effect】
As described above in detail, according to a representative example of the present invention, when access is made to a functional block for which the supply of the clock signal is stopped, the functional block is replaced with the functional block. By having a response means for outputting a response signal indicating that the access is abnormal, the access can be terminated even when access is made to the functional block for which the supply of the clock signal is stopped. Low power consumption can be achieved for the entire controller.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing a configuration of a microcontroller according to a first embodiment of the present invention.
FIG. 2 is a table showing a relationship between a logical value of a response signal RESP and a bus access completion state.
3 is a circuit block diagram showing a configuration of a default slave block 104 of the microcomputer shown in FIG.
FIG. 4 is an operation waveform diagram showing the operation of the microcontroller according to the first embodiment.
FIG. 5 is a circuit block diagram showing a configuration of a microcontroller according to a second embodiment of the present invention.
FIG. 6 is a circuit diagram showing a configuration of a slave block of a microcontroller according to a second embodiment of the present invention.
FIG. 7 is an operation waveform diagram showing the operation of the microcomputer according to the second embodiment of the present invention.
FIG. 8 is a circuit diagram showing another configuration of the stop control unit of the microcontroller according to the second embodiment of the present invention;
[Explanation of symbols]
101 Master block
102 Slave block
103 Slave block
104 Default slave block
105 Clock signal line
106 Clock signal control means
107 Clock signal control means
108 Write / Read signal line
109 Response signal line
110 Clock control signal line
111 Clock control signal line
112 Address signal line
113 Data signal line
CLOCK clock signal
ADDR address signal
DATA data signal
W / R write / read signal
RESP response signal
CKSTOP1 clock control signal
CKSTOP2 clock control signal

Claims (1)

A plurality of functional blocks which are supplied with a clock signal and execute a predetermined function;
Clock signal control means for selectively supplying the clock signal to the functional block in response to a clock control signal;
When the supply of the clock signal is the access to the functional blocks is stopped is performed, instead of the function blocks, and outputs a response signal indicating that access to the functional block is abnormal, each Response means provided for each functional block ,
A selection circuit for selecting and outputting either the first signal set in advance or the second signal set in advance in response to the selection signal;
A selection signal generating circuit that generates the selection signal based on an address signal input to the functional block and the clock control signal;
A microcontroller comprising: a response signal output circuit that outputs the response signal based on one of the first signal and the second signal.

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