JPH04348678A - Video detection circuit - Google Patents

Abstract

PURPOSE:To attain circuit integration by implementing video detection without use of a tank circuit 14 comprising an L and a C in the video detection circuit for a TV receiver. CONSTITUTION:A video intermediate frequency signal from an input terminal 1 is converted into a 2nd video intermediate frequency signal by a frequency converter 2 and inputted to a synchronization detector 3 and a phase comparator 7. Moreover, the video intermediate frequency signal is frequency-divided by a frequency divider 8 to obtain two output signals having a phase difference of 90 deg. and they are fed to the phase comparator 7 and the synchronization detector 3. The output signal of the frequency divider 8 and the 2nd video intermediate frequency signal inputted to the phase comparator 7 are fed to a PLL loop comprising the phase comparator 7, an LPF 6, a VCO 5 and the frequency converter 2, in which the phase difference is always kept to be 90 deg.. Thus, the other output signal and the 2nd video intermediate frequency signal are in phase and the video detection is attained by the synchronization detector.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video detection circuit in a TV receiver.

0002

[Prior Art] A conventional video detection circuit is shown in FIG.
), (b) as shown in block diagrams and circuit diagrams. For example, see "NHK Color Television Textbook (Part 1)" edited by Japan Broadcasting Corporation, published by Japan Broadcasting Corporation, April 20, 1986, pp. 124-127.

As shown in the figure, this video detection circuit includes a synchronous detector 3 which receives a video intermediate frequency signal from an input terminal 1 and is constructed of a double-balanced differential circuit and outputs an output from an output terminal 4.
It is composed of an amplitude limiting amplifier circuit 13 to which a tank circuit 4 is connected.

Next, the operation of this circuit will be explained. The amplitude control circuit 13 is a circuit that creates a carrier wave with a constant amplitude based on the video intermediate frequency signal, and slices the amplitude changing portion of the video intermediate frequency signal using a differential amplifier circuit consisting of transistors Q1 and Q2. is a parallel resonant circuit composed of a coil 11 and a capacitor C1, and exhibits characteristics as shown in FIG. That is, it functions to tune to the frequency f0 of the video intermediate frequency signal and extract the carrier wave. Note that the diodes D1 and D2 are diodes for converting the carrier wave appearing in the tank circuit 14 into a square wave with the head clipped.

In the synchronous detector 3, the video intermediate frequency signal applied to the base of the transistor Q9 is connected to the transistors Q9,
It is amplified by a differential amplifier circuit composed of Q10, and the bases of transistors Q5 and Q6 and the transistor Q7
, Q8 are applied with the carrier wave generated by the amplitude limiting amplifier circuit 13, so that transistors Q5, Q6 and transistors Q7, Q8 perform switching operations.

A collector current shown in FIG. 5 flows through the collector of the transistor Q9, and a carrier wave signal shown in the drawing is applied to the base of the transistor Q5, and a collector current shown in the drawing flows through the collector of the transistor Q5. On the other hand, since the illustrated collector current flows through the collector of the transistor Q10, and the illustrated carrier wave is applied to the base of the transistor Q8, the illustrated collector current flows through the collector of the transistor Q8. Therefore, the current shown in the figure flows through the output terminal 4b every half cycle through the resistor R7 and the capacitor C.
3, harmonic components are removed and the video signal voltage shown in the figure can be extracted.

Similarly, this is also carried out between transistors Q5 and Q6, and since transistors Q5 and Q6 and Q7 and Q8 each operate differentially, the output terminal 4a receives the inverted video signal of the output terminal 4b shown in the figure. Voltage can be taken out.

[0008]

In this conventional video detection circuit, a tank circuit 14 is used in the amplitude control circuit 13, and as shown in FIG.
Adjustment is required in order to tune to the video intermediate frequency with a high Q. Generally, it is difficult to incorporate such a tank circuit consisting of a coil and a capacitor into an IC, and this results in an increase in the number of external parts and pins, which is undesirable when integrated into an IC.

An object of the present invention is to provide a video detection circuit which solves these problems, eliminates the need for a tank circuit consisting of L and C, and allows the circuit to be integrated into an IC.

0010

[Means for Solving the Problems] The configuration of the video detection circuit of the present invention includes a frequency converter that inputs a video intermediate frequency signal and a control oscillation signal and converts it into a second video intermediate frequency signal; a frequency divider that divides a signal by at least 2 or more and outputs two frequency-divided signals each having a phase difference of 90 degrees;
a synchronous detector that inputs the video intermediate frequency signal and extracts a synchronous component; a phase comparator that compares the phase of the second video intermediate frequency signal and the second output signal of the frequency divider; an LPF that extracts a DC component from the output signal of the comparator;
The present invention is characterized by comprising a voltage controlled oscillator that is controlled by the output voltage of the LPF and outputs the controlled oscillation signal.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of a video detection circuit according to the present invention. In the figure, the frequency converter 2 is
The video intermediate frequency signal from the input terminal 1 is converted into a second video intermediate frequency using the output signal of the VCO 5 as a carrier wave, and the limiter circuit 9 slices the amplitude changing portion of the video intermediate frequency signal from the input terminal 1 to increase the amplitude. Outputs a constant carrier wave.

D-type flip-flops (hereinafter referred to as D-type F/F) 10 to 12 have their respective inverted Q outputs and D inputs connected to form a frequency dividing circuit, and the T input of the D-type F/F 10 is connected to the limiter circuit 9. The T input of D type F/F11 is applied with the Q output of D type F/F10, and the T input of D type F/F12 is applied.
The input is a frequency divider 8 by applying the inverted Q output of a D-type F/F 10. The phase comparator 7 compares the phase of the second video intermediate frequency signal converted by the frequency converter 12 and the Q output signal of the D-type F/F 12, and the low-pass filter (LPF) 6 compares the phase of the second video intermediate frequency signal converted by the frequency converter 12 with the Q output signal of the D-type F/F 12. Extract only the DC component from VC
Output to O5. Furthermore, the VCO 5 is controlled by the output voltage of the LPF 6, and the video intermediate frequency is set to fIF, the frequency divider 8.
The VCO oscillates at a frequency of fIF{1+(1/n)} or fIF{1-(1/n)}, where n is the frequency division of .

The video intermediate frequency signal is converted into a second video intermediate frequency signal by the frequency converter 2 from the input terminal 1,
The video intermediate frequency signal applied to the synchronous detector 3 and, on the other hand, applied from the input terminal 1 is sliced by the limiter circuit 9 into its amplitude changing portion, and outputs a carrier wave with a constant amplitude.
It is applied to the T input of type F/F10. The Q and inverted Q outputs whose polarities are inverted, respectively, which are frequency-divided by the D-type F/F 10, are applied to the T inputs of the D-type F/Fs 11 and 12, respectively, and are frequency-divided. Figure 2 shows the Q and inverted Q outputs of D-type F/Fs 11 and 12.
If the waveforms from (d) to (g) are output and Fig. 2(d) is the reference phase (0°), Fig. 2(e) is +180°,
FIG. 2(f) has a phase of +90°, and FIG. 2(g) has a phase of +270°.

The phase comparator 7 compares the phase of the second video intermediate frequency signal converted by the frequency converter 2 and the Q output of the D-type F/F 12, and outputs a voltage corresponding to the phase difference to the LPF 6.
It is fed back to the VCO 5 via. Therefore, the oscillation output of the VCO 5 is applied to the other input of the frequency converter 2, and the phase difference between the second video intermediate frequency signal converted by the frequency converter 2 and the Q output of the D-type F/F 12 is kept constant. controlled to maintain The controlled second video intermediate frequency signal and D
Input the Q output signal of the type F/F 11 to the synchronous detector 3,
A video signal output is obtained and outputted to the output terminal 4.

Generally, the phase difference between the two signals input to the phase comparator 7 is 90°, but the phase difference between the two signals input to the synchronous detector 3 must be the same phase or the opposite phase. It won't happen. In this case, since the Q output signals of D-type F/Fs 11 and 12 always have a phase difference of 90°, D-type F/F1
The phase difference between the first Q output signal and the second video intermediate frequency signal converted by the frequency converter 2 is always in phase, and therefore, in this block diagram, a video signal can be obtained from the video intermediate frequency signal.

[0016]

[Effects of the Invention] As explained above, according to the present invention, a video signal can be obtained from a video intermediate frequency signal.
This eliminates the need for the tank circuit that was conventionally required, which eliminates the need for adjustment man-hours, reduces the number of external parts and pins, and facilitates IC implementation.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating the operation of each part in FIG. 1;

FIG. 3 is a block diagram and a circuit diagram of an example of a conventional video detection circuit.

4 is a characteristic diagram illustrating the operation of the tank circuit 14 in FIG. 3. FIG.

FIG. 5 is a waveform diagram illustrating the operation of each part in FIG. 3;

[Explanation of symbols]

1 Input terminal 2 Frequency converter 3 Synchronous detector 4, 4a, 4b Output terminal 5 VCO 6 LPF 7 Phase comparator 8 Frequency divider 9 Limiter circuit 10, 11, 12 D-type flip-flop 13
Amplitude limiting amplifier circuit 14 Tank circuit 15 Low potential terminals C1, C2, C3 Capacitors D1, D2 Diodes I1 to I4 Constant current source L1 Coils R1 to R9 Resistors Q1 to Q10 Transistors

Claims (1)

[Claims] 1. A frequency converter that inputs a video intermediate frequency signal and a control oscillation signal and converts it into a second video intermediate frequency signal, and a frequency converter that divides the video intermediate frequency signal by at least 2 or more, and divides the frequency of the video intermediate frequency signal by 90 degrees. A frequency divider that outputs two divided signals with different phases, and a synchronous detector that uses the first output signal of this frequency divider as a synchronization signal and inputs the second video intermediate frequency signal to extract a synchronization component. a phase comparator that compares the phases of the second video intermediate frequency signal and the second output signal of the frequency divider; and L that extracts a DC component from the output signal of the phase comparator.
A video detection circuit comprising: a PF; and a voltage controlled oscillator that is controlled by the output voltage of the LPF and outputs the control oscillation signal.