JPH04348587A - Circuit board and manufacture thereof - Google Patents
Circuit board and manufacture thereofInfo
- Publication number
- JPH04348587A JPH04348587A JP12097791A JP12097791A JPH04348587A JP H04348587 A JPH04348587 A JP H04348587A JP 12097791 A JP12097791 A JP 12097791A JP 12097791 A JP12097791 A JP 12097791A JP H04348587 A JPH04348587 A JP H04348587A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- silver
- layer
- layer electrode
- glass substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000011521 glass Substances 0.000 claims abstract description 30
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 229910000679 solder Inorganic materials 0.000 claims abstract description 18
- 238000005476 soldering Methods 0.000 claims abstract description 11
- 230000002093 peripheral effect Effects 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 30
- 229910052709 silver Inorganic materials 0.000 claims description 26
- 239000004332 silver Substances 0.000 claims description 26
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- 229910052802 copper Inorganic materials 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 18
- 229920001187 thermosetting polymer Polymers 0.000 claims description 17
- 239000011347 resin Substances 0.000 claims description 14
- 229920005989 resin Polymers 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000000843 powder Substances 0.000 claims description 12
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 claims description 11
- 239000000203 mixture Substances 0.000 claims description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims 2
- 229910052763 palladium Inorganic materials 0.000 claims 1
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000012459 cleaning agent Substances 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は電子機器、特にハイブリ
ッドICに使用する回路基板およびその製造方法に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board used in electronic equipment, particularly a hybrid IC, and a method for manufacturing the same.
【0002】0002
【従来の技術】図4は従来の回路基板の断面図である。
図4において11は上面に導体配線12を施したガラス
基板である。13はガラス基板11上の導体配線12に
接続され、周縁部がオーバーコート14に重合されるよ
うに設けた電極である。15は電極13の上面に設けら
れた半田層である。2. Description of the Related Art FIG. 4 is a sectional view of a conventional circuit board. In FIG. 4, reference numeral 11 is a glass substrate on which conductor wiring 12 is provided. Reference numeral 13 denotes an electrode connected to the conductor wiring 12 on the glass substrate 11 and provided so that its peripheral edge overlaps the overcoat 14. 15 is a solder layer provided on the upper surface of the electrode 13.
【0003】以下、上記従来の回路基板の製造方法につ
いて説明する。まず、ガラス基板11をアルカリ洗浄剤
で超音波洗浄した後、十分に乾燥させたガラス基板11
上に銅、銀、または、インジウムテインオキサイドのい
ずれかよりなる導体配線12を印刷し焼成して形成する
。[0003] Hereinafter, a method for manufacturing the above-mentioned conventional circuit board will be explained. First, the glass substrate 11 is ultrasonically cleaned with an alkaline cleaning agent, and then the glass substrate 11 is sufficiently dried.
A conductor wiring 12 made of copper, silver, or indium tein oxide is printed thereon and fired.
【0004】次に、導体配線12の一部と接続されるよ
うに銀、銅のいずれかを印刷し焼成して電極13を形成
する。[0004] Next, either silver or copper is printed and fired to form an electrode 13 so as to be connected to a portion of the conductor wiring 12.
【0005】次に、電極13の周縁部と重合するように
オーバーコート14を印刷し焼成する。Next, an overcoat 14 is printed so as to overlap the peripheral edge of the electrode 13 and fired.
【0006】最後に、電極13の上面に半田層15を設
けて回路基板を製造していた。Finally, a solder layer 15 is provided on the upper surface of the electrode 13 to manufacture a circuit board.
【0007】[0007]
【発明が解決しようとする課題】しかしながら上記従来
の構成では、半田層15、電極13、ガラス基板11の
それぞれにおける熱膨張係数が大きく異なるため、特に
一番密着力の弱い電極13とガラス基板11の界面に応
力が集中して、剥離しやすくガラス基板11との密着強
度が劣化しやすいという課題を有していた。However, in the above-mentioned conventional configuration, the coefficients of thermal expansion of the solder layer 15, the electrode 13, and the glass substrate 11 are significantly different, so that the electrode 13 and the glass substrate 11 have the weakest adhesion. Stress is concentrated at the interface between the glass substrate 11 and the glass substrate 11, resulting in easy peeling and deterioration of adhesion strength with the glass substrate 11.
【0008】また、電極13の周縁部と重合するように
オーバーコート14を印刷し、焼成して形成することに
より、オーバーコート14が電極13に浸透して、電極
13の表面での半田ぬれ性が損なわれ、半田球ができや
すくなり、半田層15を介して他の電子部品を実装した
際に剥離しやすいという課題を有していた。[0008] Furthermore, by printing and baking the overcoat 14 so as to overlap the peripheral edge of the electrode 13, the overcoat 14 penetrates into the electrode 13 and improves solder wettability on the surface of the electrode 13. This has led to problems in that the solder layer 15 is easily damaged, solder balls are easily formed, and other electronic components are easily peeled off when mounted via the solder layer 15.
【0009】本発明は上記従来の課題を解決するもので
、電極とガラス基板の界面において応力を分散させるこ
とにより界面剥離を防ぎ、かつ、電極表面での半田ぬれ
性の向上した回路基板およびその製造方法を提供するこ
とを目的とする。The present invention solves the above-mentioned conventional problems, and provides a circuit board and its circuit board that prevents interfacial peeling by dispersing stress at the interface between an electrode and a glass substrate, and improves solderability on the electrode surface. The purpose is to provide a manufacturing method.
【0010】0010
【課題を解決するための手段】この目的を達成するため
に本発明の回路基板は、上面に導体配線を施したガラス
基板と、このガラス基板上の前記導体配線に接続される
ように少なくとも銅、銀、銀ーパラジウムのいずれかの
金属粉体と熱硬化系樹脂を混合してなる第1層の電極と
、前記第1層の電極の周縁部に重合するように基板上に
形成したオーバーコートと、前記第1層の電極の上面に
電気的に接続されるように少なくとも銅、銀、銀−パラ
ジウムのいづれかの金属粉体と熱硬化系樹脂を混合して
なる第2層の電極を備え、前記第2層の電極の上面に他
の電子部品を半田実装する半田層を有した構成であり、
その製造方法は、ガラス基板の上面に導体配線を印刷し
焼成して形成する工程と、前記導体配線に接続されるよ
うに少なくとも銅、銀、銀−パラジウムのいずれかの金
属粉体と熱硬化系樹脂を混合してなるペーストで第1層
の電極を形成する工程と、前記第1層の電極の周縁部に
重合するようにガラス基板上にオーバーコートを印刷し
硬化して形成する工程と、前記第1層の電極の上面に電
気的に接続されるように少なくとも銅、銀、銀−パラジ
ウムのいずれかの金属粉体と熱硬化系樹脂を混合して第
2層の電極を形成する工程と、前記第2層の電極の上面
に他の電子部品を半田実装する半田層を形成する工程と
を有している。[Means for Solving the Problems] In order to achieve this object, the circuit board of the present invention includes a glass substrate having a conductor wiring on the upper surface, and at least a copper plate connected to the conductor wiring on the glass substrate. , a first layer electrode made of a mixture of metal powder of either silver or silver-palladium and a thermosetting resin, and an overcoat formed on the substrate so as to polymerize on the peripheral edge of the first layer electrode. and a second layer electrode made of a mixture of at least a metal powder of copper, silver, or silver-palladium and a thermosetting resin so as to be electrically connected to the upper surface of the first layer electrode. , having a solder layer for soldering other electronic components on the upper surface of the second layer electrode,
The manufacturing method includes a step of printing and baking a conductor wiring on the upper surface of a glass substrate, and a step of forming a metal powder of at least copper, silver, or silver-palladium and thermosetting it to be connected to the conductor wiring. a step of forming a first layer electrode with a paste made by mixing a base resin, and a step of printing and curing an overcoat on a glass substrate so as to polymerize on the peripheral edge of the first layer electrode. , forming a second layer electrode by mixing at least a metal powder of copper, silver, or silver-palladium with a thermosetting resin so as to be electrically connected to the upper surface of the first layer electrode; and a step of forming a solder layer to solder-mount other electronic components on the upper surface of the second layer electrode.
【0011】[0011]
【作用】従って本発明によれば、少なくとも銅、銀、銀
−パラジウムのいずれかの金属粉体と熱硬化系樹脂を混
合してなる第1層の電極および第2層の電極との電極2
層構造にすることにより、この相互で応力を受けとめ、
緩衝し、分散させる。そして、ガラス基板上の第1層の
電極に熱硬化系樹脂を混入して形成することにより、耐
熱および耐湿特性に優れ、ガラス基板との密着性が増す
。[Function] Therefore, according to the present invention, the electrode 2 is composed of a first layer electrode and a second layer electrode made of a mixture of metal powder of at least copper, silver, or silver-palladium and a thermosetting resin.
By creating a layered structure, stress can be absorbed by each other,
Buffer and disperse. By mixing a thermosetting resin into the first layer of electrodes on the glass substrate, the electrodes have excellent heat resistance and moisture resistance, and increase adhesion to the glass substrate.
【0012】また、上面に半田層を設ける第2層の電極
は、オーバーコートと重合する部分がないので、オーバ
ーコートを吸収し浸透させることはない。[0012] Furthermore, since the second layer electrode, on which the solder layer is provided, has no portion that polymerizes with the overcoat, the overcoat will not be absorbed or penetrated.
【0013】[0013]
(実施例1)以下本発明の一実施例について、図面を参
照しながら説明する。(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.
【0014】図1は本発明の回路基板の断面図である。
図1において、1は上面に導体配線2を施したガラス基
板で、この導体配線2に接続されるように少なくとも銅
、銀、銀−パラジウムのいずれかの金属粉体と熱硬化系
樹脂を混合してなる第1層の電極3が設けてある。さら
に、この第1層の電極3の周縁部に重合するようにガラ
ス基板1上にオーバーコート4が設けてある。5は第1
層の電極3の上面に電気的に接続された少なくとも銅、
銀、銀−パラジウムのいずれかの金属粉体と熱硬化系樹
脂を混合してなる第二層の電極で、その第二層の電極5
の上面に他の電子部品を半田実装する半田層6が設けて
ある。FIG. 1 is a sectional view of a circuit board according to the present invention. In FIG. 1, 1 is a glass substrate with conductor wiring 2 on its upper surface, and a thermosetting resin is mixed with at least metal powder of copper, silver, or silver-palladium so as to be connected to the conductor wiring 2. A first layer electrode 3 is provided. Further, an overcoat 4 is provided on the glass substrate 1 so as to overlap the peripheral edge of the first layer electrode 3. 5 is the first
at least copper electrically connected to the top surface of the electrode 3 of the layer;
A second layer electrode made of a mixture of metal powder of silver or silver-palladium and a thermosetting resin, and the second layer electrode 5
A solder layer 6 on which other electronic components are soldered is provided on the top surface.
【0015】以上のように構成された回路基板の製造方
法について説明する。まず、図2(a)に示すように、
ガラス基板1をアルカリ洗浄剤で超音波洗浄した後、十
分に乾燥させたガラス基板1上に銀で導体配線2を印刷
し焼成して形成する。A method of manufacturing the circuit board configured as described above will be explained. First, as shown in Figure 2(a),
After the glass substrate 1 is ultrasonically cleaned with an alkaline cleaning agent, conductor wiring 2 is printed with silver on the sufficiently dried glass substrate 1 and is formed by baking.
【0016】次に、図2(b)に示すように、導体配線
2の一部と接続されるようにフェノール系熱硬化型銀ペ
ースト(ELECTRO−SCIENCE LABO
RATORIES,INC.社製1109−S)をスク
リーン印刷し、温度220℃で2時間、熱硬化して第1
層の電極3を形成する。このとき、第1層の電極3の面
積抵抗を低くすることや、未硬化部分を完全になくして
硬化後の樹脂の経時変化や、熱的に不安定な要素を取り
除く必要があるので、比較的高温(製造元推奨温度:1
50℃)で硬化しなければならない。Next, as shown in FIG. 2(b), a phenolic thermosetting silver paste (ELECTRO-SCIENCE LABO
RATORIES, INC. 1109-S) made by Co., Ltd., and heat cured at 220℃ for 2 hours.
Form the layer electrode 3. At this time, it is necessary to lower the sheet resistance of the first layer electrode 3, completely eliminate uncured parts, and eliminate changes in the resin after curing over time and thermally unstable elements. target high temperature (manufacturer's recommended temperature: 1
50°C).
【0017】次に、図2(c)に示すように、オーバー
コート4を印刷し硬化する。これは、導体配線2で用い
た銀配線の銀移行を防止するために施すものである。Next, as shown in FIG. 2(c), an overcoat 4 is printed and cured. This is done to prevent silver migration from the silver wiring used in the conductor wiring 2.
【0018】次に、図2(d)に示すように、半田付け
電極部としてフェノール系熱硬化型銅ペーストを第1層
の電極3と電気的に接続されるように印刷して、温度1
50℃で30分間、熱硬化して第2層の電極5を形成す
る。この第2層の電極5と第1層の電極3とは、物理的
かつ化学的なアンカー効果で結合されているため、接続
界面で電極剥離を生じることはない。Next, as shown in FIG. 2(d), a phenolic thermosetting copper paste is printed as a soldering electrode part so as to be electrically connected to the first layer electrode 3.
The second layer electrode 5 is formed by thermosetting at 50° C. for 30 minutes. Since the second layer electrode 5 and the first layer electrode 3 are bonded by a physical and chemical anchor effect, no electrode separation occurs at the connection interface.
【0019】最後に、図1に示すように第2層の電極3
の上面に他の電子部品を半田実装する半田層6を設けて
回路基板が完成する。Finally, as shown in FIG.
A solder layer 6 for soldering other electronic components is provided on the upper surface of the circuit board to complete the circuit board.
【0020】また、下記にこの製造方法で作られた回路
基板の耐候性に関するプレッシャークッカー試験(13
3℃、3気圧、5時間)の結果を図3に示す。[0020] Also, a pressure cooker test (13
3°C, 3 atm, 5 hours) are shown in Figure 3.
【0021】図3より明らかなように、本発明の回路基
板は、従来に比べて明らかに耐候性が優れていることが
わかる。As is clear from FIG. 3, the circuit board of the present invention clearly has better weather resistance than the conventional circuit board.
【0022】(実施例2)以下本発明の他の実施例の回
路基板について説明する。(Embodiment 2) A circuit board according to another embodiment of the present invention will be described below.
【0023】実施例2の構成は実施例1と同様のため説
明は省略する。本実施例2の製造方法は、実施例1の図
2(d)で示したように、半田付け電極部としてフェノ
ール系熱硬化型銅ペーストを第1層の電極3と電気的に
接続されるように印刷して、温度150℃で30分間、
熱硬化して第2層の電極5を形成したが、ここで用いた
銅電極は半田付けが良好である反面、酸化しやすく、基
板のままでの長期保存ができず、両面実装基板の場合リ
フロー半田付けの際に半田のない面の銅電極が酸化して
しまう等の問題があり、それを解決するためになされた
ものである。本第2の実施例では、第2層の電極5をフ
ェノール系熱硬化型銀ペースト(ELECTRO−SC
IENCE LABORATORIES,INC.社
製1110−S)を第1層の電極3と電気的に接続され
るように印刷して、温度150℃で30分間熱硬化して
形成し、前述した問題点である電極表面の酸化を防止し
た。この第2層の電極5と第1層の電極3とは、物理的
かつ化学的なアンカー効果で結合されたいるため、接続
界面で電極剥離を生じることはない。しかし、この第2
層の電極5に用いた銀ペーストは、第1層の電極3に用
いた銀ペーストよりも銀含有量が多いため銀拡散(銀と
スズの共晶現象)が生じるため半田付けが良好であると
はいえないが、銀拡散防止用半田(千住金属工業株式会
社製SPT73−E120−M10)を用いることによ
り改善することができる。The configuration of the second embodiment is similar to that of the first embodiment, so the explanation will be omitted. In the manufacturing method of Example 2, as shown in FIG. 2(d) of Example 1, a phenolic thermosetting copper paste is electrically connected to the first layer electrode 3 as a soldering electrode part. Print as shown and print at a temperature of 150℃ for 30 minutes.
The second layer electrode 5 was formed by heat curing, but although the copper electrode used here has good soldering, it is easily oxidized and cannot be stored as a board for a long period of time. This was done to solve problems such as oxidation of copper electrodes on non-solder surfaces during reflow soldering. In this second embodiment, the second layer electrode 5 is made of phenolic thermosetting silver paste (ELECTRO-SC).
IENCE LABORATORIES, INC. 1110-S), which is electrically connected to the first layer electrode 3, and is thermally cured at a temperature of 150°C for 30 minutes to avoid oxidation of the electrode surface, which is the problem mentioned above. Prevented. Since the second layer electrode 5 and the first layer electrode 3 are bonded by a physical and chemical anchor effect, no electrode separation occurs at the connection interface. However, this second
The silver paste used for the electrode 5 of the layer has a higher silver content than the silver paste used for the electrode 3 of the first layer, so silver diffusion (eutectic phenomenon of silver and tin) occurs, resulting in good soldering. However, it can be improved by using solder for preventing silver diffusion (SPT73-E120-M10, manufactured by Senju Metal Industry Co., Ltd.).
【0024】[0024]
【発明の効果】以上のように本発明は、ガラス基板上の
導体配線に接続されるように形成した少なくとも銅、銀
、銀−パラジウムのいずれかの金属粉体と熱硬化系樹脂
を混合してなる第1層の電極と、第1層の電極の上面に
電気的に接続されように少なくとも銅、銀、銀−パラジ
ウムのいずれかの金属粉体と熱硬化系樹脂を混合してな
る第2層の電極とによる電極の2層構造とすることによ
り、電極とガラス基板の界面で剥離しにくく、ガラス基
板との密着強度を向上させ、耐候性および半田ぬれ性の
優れた回路基板およびその製造方法を提供することがで
きる。Effects of the Invention As described above, the present invention mixes a thermosetting resin with at least a metal powder of copper, silver, or silver-palladium formed to be connected to conductor wiring on a glass substrate. a first layer electrode consisting of a first layer; The two-layer structure of the electrode makes it difficult to peel off at the interface between the electrode and the glass substrate, improves the adhesion strength with the glass substrate, and provides circuit boards with excellent weather resistance and solderability. A manufacturing method can be provided.
【図1】本発明の回路基板の一実施例を示す断面図FIG. 1 is a sectional view showing an embodiment of the circuit board of the present invention.
【図
2】(a)〜(d)は同回路基板の製造方法の一実施例
を示す各工程の断面図[Fig. 2] (a) to (d) are cross-sectional views of each process showing an example of the method for manufacturing the same circuit board.
【図3】本発明と従来の回路基板の耐候性特性比較図[Figure 3] Comparison diagram of weather resistance characteristics of the present invention and conventional circuit board
【
図4】従来の回路基板の断面図[
Figure 4: Cross-sectional view of a conventional circuit board
【符号の説明】 1 ガラス基板 2 導体配線 3 第1層の電極 4 オーバーコート 5 第2層の電極 6 半田層[Explanation of symbols] 1 Glass substrate 2 Conductor wiring 3 First layer electrode 4 Overcoat 5 Second layer electrode 6 Solder layer
Claims (2)
のガラス基板上の前記導体配線に接続されるように形成
した少なくとも銅、銀、銀ーパラジウムのいずれかの金
属粉体と熱硬化系樹脂を混合してなる第1層の電極と、
前記第1層の電極の周縁部に重合するように基板上に形
成したオーバーコートと、前記第1層の電極の上面に電
気的に接続されるように少なくとも銅、銀、銀ーパラジ
ウムのいずれかの金属粉体と熱硬化系樹脂を混合してな
る第2層の電極を備え、前記第2層の電極の上面に他の
電子部品を半田実装する半田層を有することを特徴とす
る回路基板。1. A glass substrate having conductor wiring on its upper surface, a metal powder of at least one of copper, silver, and silver-palladium formed to be connected to the conductor wiring on the glass substrate, and a thermosetting system. a first layer electrode made of a mixture of resin;
an overcoat formed on the substrate so as to overlap the peripheral edge of the first layer electrode; and at least one of copper, silver, and silver-palladium so as to be electrically connected to the upper surface of the first layer electrode. A circuit board comprising a second layer electrode made of a mixture of metal powder and thermosetting resin, and a solder layer for soldering other electronic components on the upper surface of the second layer electrode. .
して形成する工程と、前記導体配線に接続されるように
少なくとも銅、銀、銀−パラジウムのいずれかの金属粉
体と熱硬化系樹脂を混合してなるペーストを印刷し硬化
して第1層の電極を形成する工程と、前記第1層の電極
の周縁部に重合するようにガラス基板上にオーバーコー
トを印刷し硬化して形成する工程と、前記第1層の電極
の上面に電気的に接続されるように少なくとも銅、銀、
銀−パラジウムのいずれかの金属粉体と熱硬化系樹脂を
混合してなるペーストを印刷し硬化して第2層の電極を
形成する工程と、前記第2層の電極の上面に他の電子部
品を半田実装する半田層を形成する工程とからなる回路
基板の製造方法。2. A step of printing and baking a conductor wiring on the upper surface of a glass substrate, and thermally curing at least one of copper, silver, and silver-palladium metal powder so as to be connected to the conductor wiring. A step of printing and curing a paste made by mixing a system resin to form a first layer electrode, and printing and curing an overcoat on the glass substrate so as to polymerize on the peripheral edge of the first layer electrode. a step of forming at least copper, silver,
A step of printing and curing a paste made by mixing metal powder of either silver or palladium and a thermosetting resin to form a second layer electrode, and adding another electronic layer to the top surface of the second layer electrode. A method for manufacturing a circuit board, which includes the step of forming a solder layer for soldering components.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3120977A JP2855882B2 (en) | 1991-05-27 | 1991-05-27 | Circuit board and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3120977A JP2855882B2 (en) | 1991-05-27 | 1991-05-27 | Circuit board and method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04348587A true JPH04348587A (en) | 1992-12-03 |
JP2855882B2 JP2855882B2 (en) | 1999-02-10 |
Family
ID=14799728
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3120977A Expired - Fee Related JP2855882B2 (en) | 1991-05-27 | 1991-05-27 | Circuit board and method of manufacturing the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2855882B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000005933A1 (en) * | 1998-07-22 | 2000-02-03 | Ibiden Co., Ltd. | Printed-circuit board and method of manufacture thereof |
JP2008300792A (en) * | 2007-06-04 | 2008-12-11 | Fuji Electric Device Technology Co Ltd | Semiconductor device, and manufacturing method thereof |
WO2009081929A1 (en) * | 2007-12-26 | 2009-07-02 | Fujikura Ltd. | Mounted board and method for manufacturing the same |
-
1991
- 1991-05-27 JP JP3120977A patent/JP2855882B2/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000005933A1 (en) * | 1998-07-22 | 2000-02-03 | Ibiden Co., Ltd. | Printed-circuit board and method of manufacture thereof |
US6809415B2 (en) | 1998-07-22 | 2004-10-26 | Ibiden Co., Ltd. | Printed-circuit board and method of manufacture thereof |
JP2008300792A (en) * | 2007-06-04 | 2008-12-11 | Fuji Electric Device Technology Co Ltd | Semiconductor device, and manufacturing method thereof |
WO2009081929A1 (en) * | 2007-12-26 | 2009-07-02 | Fujikura Ltd. | Mounted board and method for manufacturing the same |
US8039760B2 (en) | 2007-12-26 | 2011-10-18 | Fujikura Ltd. | Mounting board and method of producing the same |
JP5220766B2 (en) * | 2007-12-26 | 2013-06-26 | 株式会社フジクラ | Mounting board |
Also Published As
Publication number | Publication date |
---|---|
JP2855882B2 (en) | 1999-02-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5383093A (en) | Hybrid integrated circuit apparatus | |
JP3633136B2 (en) | Printed wiring board | |
JPS63310581A (en) | Film body for electric connection | |
JPH04348587A (en) | Circuit board and manufacture thereof | |
JPS6127089Y2 (en) | ||
JPS60108822A (en) | Terminal connecting method of liquid crystal display element | |
JPH0210571B2 (en) | ||
US5219607A (en) | Method of manufacturing printed circuit board | |
WO1997030461A1 (en) | Resistor network in ball grid array package | |
JP2000022070A (en) | Electronic part having bump and its manufacture | |
JP2961859B2 (en) | Multilayer ceramic substrate | |
JPH11177016A (en) | Composite integrated circuit device | |
JP3719806B2 (en) | Wiring board | |
JPH0982835A (en) | Circuit substrate and multilayer circuit substrate | |
JPH09260822A (en) | Structure for connecting/fixing electronic part to board with solder | |
JP2002083841A (en) | Mounting structure and its manufacturing method | |
JPH06124850A (en) | Laminated composite electronic component | |
JPH0636601Y2 (en) | Circuit board | |
EP0375954B1 (en) | Method of manufacturing printed circuit board | |
JPH0543311B2 (en) | ||
JPH06224203A (en) | Semiconductor device | |
JP2004031814A (en) | Wiring board and electronic device using the same | |
JPH0588560B2 (en) | ||
JPH11274347A (en) | Semiconductor package and method for forming the same | |
JPS63202987A (en) | Circuit board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |