JPH04347748A - Multi-port ram and picture display controller - Google Patents

Abstract

PURPOSE:To change a display content without rewriting the storage content of a RAM part included in a multi-port RAM. CONSTITUTION:A data transfer mode from the RAM part 10 to a data register 21 and a data transfer mode from a ROM 5 storing prescribed dummy picture data for changing content to the register 21 are switched by providing a transfer mode switching means 2 including a switch signal generation part 6 and an invertor 7 inverting the output. Thus, the display content of a CRT display can be changed.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides a multi-port R having a random access port and a serial access port.
The present invention relates to an AM and an image display control device including the same, and relates to a technique that is effective when applied to, for example, a data processing device.

0002

[Prior Art] In a display controller that performs display control for a CRT (cathode ray tube) display device and address control for a bitmap memory such as a frame buffer, the drawing process for changing the contents of the display screen is performed by a microprocessor. However, as described in "LSI Handbook" P556 published by Ohmsha on November 30, 1980, when relatively complex processing is required on a pixel-by-pixel basis, such as graphics. , leaving everything to the processing of a microprocessor is not necessarily a good idea in terms of processor usage efficiency and speeding up image processing, so processing such as drawing basic figures, filling in figures, and even rotating and moving figures is not necessarily a good idea. A method has been adopted in which image processing is entrusted to a device dedicated to image processing, such as a display controller. A device dedicated to image processing, such as a display controller, manages an image memory called a frame buffer. This image memory has randomly accessible R
A multiport RAM is applied, which is formed by combining an AM (random access memory) section and a SAM (serial access memory) section that enables serial data output. In multi-port RAM, SA from the RAM section
Data transfer to the M section is performed for each row of the RAM section, and the data is serially output from the SAM section in synchronization with the serial clock. The display controller performs drawing by writing image data into the RAM section of such a multiport RAM, and also performs image display based on the serial output of the SAM section.

0003

By the way, in image display control, there are cases where a dummy image different from the image currently displayed on a display device such as a CRT display is displayed, and then it is desired to return to the original display image. In graphics processing, etc., there are cases where it is desired to change only the color while leaving the display pattern unchanged. Such processing is possible by changing the serial output of the SAM section, but according to the conventional device, R
By rewriting the memory contents of the AM section, the serial output is changed as described above. In other words, if you want to temporarily change the display content and return to the original display image, the RAM
After saving the data in the RAM section to another memory area, the stored contents of the RAM section are updated, and when returning to the original display image again, the above-mentioned saved data is written into the RAM section. However, after saving the data in the RAM section to another memory area, when updating the RAM section and returning to the original display image, writing the above saved data to the RAM section takes time to change the display contents. At the same time,
The present inventor has discovered that there is a problem in that the display controller must perform complicated processing.

[0004] An object of the present invention is to provide a multi-port RAM that allows the above-mentioned display contents to be changed without rewriting the memory contents of the RAM section, and an image display control device equipped with the multi-port RAM. be.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0006]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

[0007] That is, randomly accessible RAM
and a data register that operates in synchronization with a serial clock to enable serial data output, a storage means for storing predetermined data for changing display contents is provided, and further , a transfer mode switching means is provided for controlling switching between a first transfer mode for transferring data from the RAM section to the data register and a second transfer mode for transferring data from the storage means to the data register. . Further, an image display control device is formed using such a multiport RAM as a frame buffer. At this time, in order to smoothly change the display contents, it is preferable to perform the mode switching in synchronization with the serial clock. As a more specific embodiment, display dummy image data or color change data may be stored in the storage means. Furthermore, in order to prevent the storage contents from being lost due to a power cut in the case where it is unnecessary to change the storage contents of the storage means, the storage means can be replaced with a ROM (ROM).
It is better to use read-only memory).

[0008]

[Operation] According to the above-described means, the transfer mode switching means selects a data transfer mode from the RAM section to the data register and from the storage means for storing predetermined data for changing the display contents to the data register. This makes it possible to switch between the data transfer modes of the above RA.
To make it possible to change the display contents as described above without rewriting the storage contents of the M section.

[0009]

Embodiment FIG. 8 shows a data processing apparatus according to an embodiment of the present invention. In the figure, a system address bus SAB and a system data bus SDB include a microprocessor 51 and a system memory 5, which are representatively shown.
2 are combined. The graphic display processor 53 functions as a display controller that supports display control functions and drawing control functions in a system including a CRT display device 56 as an example of display means, although this is not particularly limited. It has an interface section for SDB, and an interface section for local data bus LDB1 and local address bus LAB1. A local data bus LDB1 and a local address bus LAB1 are coupled to one access port of a frame buffer 54 having dual ports, and a CRT display device 56 is coupled to the other access port of the frame buffer 54 via a dot shifter 55. are combined. As will be described in detail later, the frame buffer 54 is a multi-port RAM that has a function of quickly changing the display content temporarily without rewriting the memory content of the RAM section.

Furthermore, in this embodiment, a drawing-only buffer 50 is provided, which has a smaller storage capacity than the frame buffer 54 and can be accessed faster than the image memory. It is coupled to a graphic display processor 53 via a data bus LDB2 and a local address bus LAB2. Although such a drawing-only buffer 50 is not particularly limited, it can be relatively easily realized by applying a static RAM. The information stored in the drawing-only buffer 50 can be transferred to the frame buffer 54 at a predetermined timing. The graphic display processor 53 interprets commands supplied from the microprocessor 51 via the system data bus SDB, and performs predetermined figure drawing, figure filling, figure enlargement, reduction, rotation, etc. a transfer control function to transfer such drawing information to the frame buffer 54, and a display control function to display the image data stored in the frame buffer 54 on the CRT display device 56. support.

FIG. 9 shows a detailed configuration of the local bus side, centering on the frame buffer 54 and drawing buffer 50 in FIG. 8.

As shown in FIG. 9, the frame buffer 54 is a multi-port RAM, which includes a randomly accessible RAM section 10 and a serially accessible SA section.
It has an M section 20. The serial clock SC supplied to the SAM section 20 is generated in the clock generation section 15. Although not particularly limited, this clock generation section 15 divides the reference clock CLK by frequency-dividing the reference clock CLK.
By selecting the frequency dividing circuit 9 that outputs serial clocks of MHz and 21 MHz and the output terminal of this frequency dividing circuit 9, the serial clock SC transmitted to the SAM section 20 can be switched between 33 MHz and 21 MHz. It includes a changeover switch SW. Switching control of this switch SW is performed by the graphic display processor 53.

FIG. 1 shows the detailed structure of the frame buffer 54.

In FIG. 1, the RAM section 10 includes a memory cell array 11 including a plurality of dynamic memory cells arranged in a matrix, although this is not particularly limited. Addressing of memory cells is done by X (row) address decoder 1.
The operation of driving one predetermined word line to a selected level based on the output of Y (column) address decoder 12
This is performed based on the operation of a switch circuit that selectively connects a pair of complementary data lines to the complementary common data line based on the output of the.

The SAM unit 20 includes, although not particularly limited to, one system of data registers 21 coupled to the data input/output system of the RAM unit 10 via the transfer gate 3;
It includes a shift register 23 for controlling the address of the data register 21 based on the serial clock SC transmitted from the clock generation section 15. With such a configuration, each time the serial clock SC is input, the pointer indicated by the shift register 23 is shifted, thereby making it possible to address the data register 21. Such addressing allows writing of serial data into the data register 21 and output of serial data from the data register 21. The transfer gates 3 and 4 are, but are not particularly limited to, a plurality of N-channel MOSFETs that are controlled on/off by the output of the transfer mode switching means 2.
can be formed by

Furthermore, in this embodiment, the CRT display 56 can be rewritten without rewriting the memory contents of the RAM section 10.
In order to make it possible to temporarily change the display contents of the
only memory) 5 and the above RA as shown in FIG.
A first transfer mode in which data is transferred from the M section 10 to the data register 21, and as shown in FIG.
Transfer mode switching means 2 is provided for controlling switching between a second transfer mode and a second transfer mode for transferring data from M5 to the data register 21. This transfer mode switching means 2 is
Although not particularly limited, there is a switching signal generation unit 6 that generates a switching signal between the two types of transfer modes based on a transfer mode control signal output from the graphic display processor 53, and an output of this switching signal generation unit 6 is inverted. and an inverter 7 for transmitting the signal to the transfer gate 3. The change timing of the output logic state of the switching signal generating section 6 is synchronized with the serial clock SC in order to smoothly switch the transfer mode. For example, when the output logic state of the switching signal generation section 6 is at a low level, the transfer gate 4 on the ROM 5 side is turned off in response to this, thereby blocking data transfer from the ROM 5 to the data register 21. At this time, the transfer gate 3 on the RAM section 10 side is turned on by the output of the inverter 7 being set to a high level, thereby making it possible to transfer data row by row from the RAM section 10 to the data register 21. Ru. In this manner, the transfer gates 3 and 4 are set to the data passing state in a complementary manner based on the output of the transfer mode switching means 2, thereby making it possible to switch the transfer mode to the data register 21. Here, dummy image data for display is stored in the ROM 5, although this is not particularly limited. Storing such data in the ROM 5 is considered to be advantageous in that the stored data is not lost even if the power of the device of this embodiment is turned off, although it is said that it is difficult to change the contents.

Next, the operation of the apparatus of this embodiment will be explained.

[0018] Data transfer to the RAM 10 section is performed by the corresponding RAM.
This can also be done via the random access port of the M section 10, but in this embodiment, when the output of the inverter 7 is set to high level and the transfer gate 3 on the RAM section 10 side is turned on, the following procedure is performed. SAM section 2
Data transfer using the serial input function of 0 is possible. Furthermore, when such data transfer is performed, the RO
The transfer gate 4 on the M5 side is turned off.

Graphic display processor 53
When receiving a command from the MPU 51, it performs the drawing process specified by the command on the drawing buffer 50. For example, if the above command is "CRCL",
The graphic display processor 53 draws a circle according to a built-in circle algorithm. Generally, a drawing operation is executed according to such an algorithm, and drawing access is made to the frame buffer (corresponding to 54) immediately after the coordinates for placing a dot are obtained. In other words, drawing is performed for each pixel. Therefore, depending on the command or the figure drawn in accordance with the command, the same word may be accessed multiple times for drawing. In such a method, consider the case where a circle as shown in FIG. 7 is drawn, for example, even though pixels P1 and P2 belong to the same word, pixels P1 and P2 are drawn at least twice. Drawing access is performed, causing a delay in drawing processing. Therefore, the area 50 of one raster at a certain Y coordinate
If we focus on A and first calculate the drawing coordinates belonging to that area according to the algorithm, that is, pixels P1,
If you draw P2 in one access,
As described above, duplicate access to the same word can be eliminated, and the speed of drawing processing can be increased. In this embodiment, the graphic display processor 53 performs the drawing arithmetic processing for each raster as described above, and such drawing access is performed not to the frame buffer 54 but to the drawing-dedicated buffer 5, which can be accessed faster than the frame buffer 54.
0, and the resulting drawing information for one raster is transferred to the frame buffer 54 in serial format. Such drawing calculation processing and drawing information transfer processing are executed for all rasters including pixels whose coordinate values are changed by drawing according to commands from the MPU 51. Specifically, it is performed as follows.

[0020] That is, 33MHz by switch SW.
The serial clock is selected, and the information stored in the drawing buffer 50 is sequentially transferred to the SAM unit 20 in synchronization with the serial clock. Information transfer in this case is performed using the blanking period of the CRT display 56 so as not to interfere with image display on the CRT display 56. After all of the stored information in the drawing buffer 50 has been transferred to the SAM unit 20, information is transferred from the SAM unit 20 to the RAM unit 10. Transfer in that case is done in parallel format. On the other hand, in display access, serial output from the SAM unit 20 must be performed in synchronization with the dot clock of the CRT display 56. Therefore, at the time of display access, the 21 MHz serial clock is selected by the switch SW, and serial data is transferred from the SAM section 20 to the dot shifter 55 in synchronization with it, thereby making it possible to display images on the CRT display 56. Ru.

Next, a case will be described in which the content displayed on the CRT display 56 is temporarily changed at high speed without rewriting the content stored in the RAM section 10.

In the first transfer mode, data is transferred line by line from the RAM unit 10 to the data register 21, and CR is transferred based on the serial output from the data register 21.
It is assumed that, for example, a graphic pattern as indicated by DP1 in FIG. 4 is displayed on the T-display 56. When it is desired to temporarily change the display contents of the CRT display 56, for example, by inputting a command to that effect from a keyboard, etc., the output logic state of the switching signal generation section 6 is inverted, and the second transfer mode is thereby changed. selected. That is, the transfer gate 4 on the ROM 5 side is turned on instead of the transfer gate on the RAM section 10 side, and thereby the display change data in the ROM 5 is transferred to the data register 21. The data in the data register 21 is serially output in the same way as in the above case, and based on the data, a dummy image as shown by DP2 in FIG. 5, for example, is displayed on the CRT display 56. In such a dummy image display, R
The contents stored in the AM unit 10 will not be changed unless there is a specific instruction to rewrite the contents. Therefore, a command is input to return the display contents to their original state, and the first transfer mode is selected thereby.
The image DP1 is transferred to the CRT based on the data stored in the AM section 10.
It can be quickly displayed on the display 56.

According to this embodiment, the following effects can be obtained.

(1) Transfer mode switching means 2 including a switching signal generating section 6 and an inverter 7 for inverting its output
By providing a data transfer mode (first transfer mode) from the RAM unit 10 to the data register 21, and a data transfer mode from the ROM 5 storing predetermined dummy image data for changing display contents to the data register 21. It is possible to switch between the data transfer mode (second transfer mode), and by switching the transfer mode, the above-mentioned RA
It is possible to temporarily change the display content of the CRT display 56 without rewriting the memory content of the M unit 10. In this case, the display content can be changed by switching the data transfer mode to the data register 21, that is, by switching the data transfer route, as described above, and is not done by rewriting the memory content of the RAM unit 10 as in conventional devices. , the display images on the CRT display 56 can be switched at high speed, and the processing of the display controller can be reduced.

(2) Furthermore, a drawing buffer 50 which has a smaller storage capacity than the frame buffer 54 as an image memory and which can be accessed at high speed is provided as a drawing-only memory, and is asynchronous with the write/read operations of the frame buffer 54. The graphic display processor 53 functionally realizes the drawing control means for drawing on the drawing buffer 50 and the transfer control means for transferring this drawing information from the drawing buffer 50 to the frame buffer 54, so that display access can be performed as a drawing access. Under conditions where priority is given to the above, drawing calculation processing can be performed using the drawing buffer 50 even during display access, so there is no interruption of drawing, and the cycle time between display access and drawing access is reduced. Even though they are different, there is no need to adjust the cycle of the drawing access to the display access, which has a longer cycle time, so it is possible to improve the drawing speed.

(3) A single SAM unit 20 is used for both taking in drawing information from the drawing buffer 50 and outputting display data to the dot shifter 55. In this case,
When transferring drawing information from the drawing buffer 50 to the frame buffer 54, a 33 MHz serial clock is selected by the switch SW, and in synchronization with this, the storage information of the drawing buffer 50 is sequentially transferred to the SAM unit 20, and in display access, A 21 MHz serial clock is selected by the switch SW, and serial data is transferred from the SAM unit 20 to the dot shifter 55 in synchronization with the serial clock, thereby enabling high-speed transfer of drawing information without interfering with display access. be done.

(4) As shown in FIG. 7, 1 of the Y coordinate
By first calculating the drawing coordinates belonging to the raster area 50A according to the algorithm, in other words, the pixel P1,
Taking advantage of the fact that by drawing P2 in one access, it is possible to eliminate duplicate accesses to the same word as in the past, the graphic display processor 53 performs drawing calculation processing in units of one raster, and such drawing access is performed. , not to the frame buffer 54, but to the drawing-dedicated buffer 50, which can be accessed at a higher speed, and by transferring one raster's worth of drawing information obtained thereby to the frame buffer 54 in serial format. , drawing calculation processing and drawing information transfer processing can be performed at high speed.

Although the invention made by the present inventor has been specifically explained based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof. stomach.

For example, in the above embodiment, dummy image information is stored in the ROM 5, but color change data may be stored instead. In this way, as shown in FIG.
The display color of the entire display screen DP3 of CRT display 56 can be changed as shown in DP4, and as shown in FIG. Colors, DP7 and D respectively
It can be changed as shown in P8. Such display color changes can be made by changing the R, G, B signals corresponding to the three primary colors of light and the luminance signal Y.
When the ROM 5 has the same bit configuration as the data register 21, the color change data in the ROM 5 is as follows.
For example, all "1" or "0" may be used.

In the above embodiment, the SAM unit 20 includes one system of data registers, but the SAM unit 20 may include two or more systems of data registers. For example, if there are two systems of data registers, the output of one data register is selected and information can be written to the other data register during a period when the data held in that register is being output to the dot shifter 21. , it is possible to transfer drawing information from the drawing buffer 50 to the data register even during the display access period. Further, a memory having a storage capacity for a plurality of images can be used as the frame buffer 54, and a memory having a storage capacity for a plurality of rasters can be used as the drawing buffer 50. Furthermore, R
A plurality of types of dummy image data or color change data may be stored in the OM 5, and when data is transferred from the ROM 5 to the data register 21, the plurality of types of data may be appropriately selected by a selector or the like. Although the ROM 5 is used in the above embodiment, if a readable/writable RAM or an EEP (Electrically Erasable and Programmable) ROM is used in place of the ROM 5, the contents of the dummy image data or color change data can be changed. is possible.

[0031] In place of the CRT display 56, a liquid crystal display or a plasma display can also be used.

[0032] In the above explanation, the invention made by the present inventor was mainly applied to a data processing device, which is the background field of application, but the present invention is not limited thereto; for example, It can be widely applied to graphic terminal devices and various display devices.

The present invention can be applied to conditions that include at least a data register that enables serial data output.

[0034]

Effects of the Invention The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, by making it possible to switch between the data transfer mode from the RAM section to the data register and the data transfer mode from the storage means for storing predetermined data for changing display contents to the data register, R.A.
Display contents can be changed without rewriting the storage contents of the M section.

[Brief explanation of drawings]

FIG. 1 shows a multiport R according to an embodiment of the present invention.
FIG. 2 is a block diagram of the main parts of AM.

FIG. 2 is an explanatory diagram of a first transfer mode in the device of this embodiment.

FIG. 3 is an explanatory diagram of a second transfer mode in the device of this embodiment.

FIG. 4 is an explanatory diagram of temporary change of a display image in the device of this embodiment.

FIG. 5 is an explanatory diagram of display color change in the device of this embodiment.

FIG. 6 is an explanatory diagram of display color change in the device of this embodiment.

FIG. 7 is an explanatory diagram of the drawing principle in the apparatus of this embodiment.

FIG. 8 is an overall configuration block diagram of a data processing device according to an embodiment of the present invention.

9 is a block diagram illustrating the main components of the data processing device shown in FIG. 8; FIG.

[Explanation of symbols]

2 Transfer mode switching means 3 Transfer gate 4 Transfer gate 5 ROM 6 Switching signal generation section 7 Inverter 10 RAM section 11 Memory cell array 12 Y decoder 13 X decoder 21 Data register 23 Shift register 41 DMA control circuit 50 Drawing buffer 51 Microprocessor 52 System Memory 53 Graphic display processor 54
Frame buffer 55 Dot shifter 56 CRT display

Claims (5)

[Claims] [Claim 1] A randomly accessible RAM section;
In a multi-port RAM that includes a data register that operates in synchronization with a serial clock to enable serial data output, and that is capable of transferring data from the RAM section to the data register, predetermined data for changing display content is provided. storage means for storing the data, a first transfer mode for transferring data from the RAM section to the data register, and a second transfer mode for transferring data from the storage means to the data register. A multi-port RAM comprising: means. 2. The multi-port RAM according to claim 1, wherein said transfer mode switching means controls switching between said first transfer mode and said second transfer mode in synchronization with said serial clock. 3. The storage means according to claim 1, wherein display dummy image data or color change data is stored.
Or the multiport RAM described in 2. 4. The multi-port RA according to claim 1, 2 or 3, wherein the storage means is a read-only memory.
M. 5. An image display control device comprising the multiport RAM according to claim 1, 2, 3, or 4 as a frame buffer.