JPH04346268A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To make the best use of a device area by laying out a part of a photodiode which serves as a light receiving section under a vertical CCD register which is a signal charge transfer section. CONSTITUTION:The signal charges accumulated in a photodiode are transferred to vertical CCD register 2 in vertical planking. The transferred signal charge is charge voltage-converted by a built-in amplifier by way of a transfer route 7 and output from a terminal 5 to the outside. In this fashion, the CCD register and the photodiode are doubled. This construction makes it possible to increase a photodiode occupancy area and make the best use of its device area. It is, therefore, possible increase an accumulation capacity of a photodiode and the amount signal charge that can be accumulated.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high-density solid-state imaging devices used in VTR cameras and the like.

0002

[Prior Art] Fig. 7 shows the element configuration of a conventional CCD solid-state image sensor (for example, from the Technical Report Vol. 14 of the Society of Television Engineers,
No. 16, pp. 39-44, 1990.2). The signal charges accumulated in the photodiode 1 are transferred to the vertical CCD register 2 via the transfer path 8 during the vertical blanking period, and the transferred signal charges are transferred row by line to the horizontal CCD register 3 via the transfer path 6. transferred to this horizontal CCD
The signal charge transferred to the register is converted into a charge voltage by a built-in amplifier 4 via a transfer path 7, and is outputted from a terminal 5 to the outside.

FIG. 8 shows a cross-sectional structural diagram of this image sensor. Here, 20 is an N-type semiconductor substrate, 21 is a P-type impurity layer, 22 is an N-type impurity region that becomes a photodiode, 2
5 is a P provided to suppress dark current on the semiconductor surface.
This is a type impurity region. 24 is an N-type impurity region forming a channel of the vertical CCD register, and 23 provided on the outside thereof is a P-type impurity region for confining a depletion layer extending from 24 toward the substrate. Gates 27 and 28 formed through the oxide film 26 are for driving the vertical CCD register.

0004

[Problems to be Solved by the Invention] In recent years, there has been a strong demand for higher resolution in such solid-state imaging devices. However, as shown in the same figure, since the photodiode as the light receiving section and the vertical CCD register as the signal charge transfer section are provided in the same plane, when the resolution is increased, that is, the integration is increased, the photodiode Since the area is reduced and the signal charge that can be accumulated in the photodiode is reduced, good image quality cannot be obtained. As described above, it has been difficult to improve the degree of integration in conventional solid-state imaging devices.

[0005]

Means for Solving the Problems A part of the photodiode, which is a light receiving section, is arranged below a vertical CCD register, which is a signal charge transfer section.

[0006]

[Operation] By arranging a portion of the photodiode, which is the light receiving section, under the vertical CCD register, which is the signal charge transfer section, the area occupied by the photodiode can be increased, and the device area can be used effectively. This increases the storage capacitance (junction capacitance) of the photodiode, making it possible to increase the amount of signal charge that can be stored.

[0007]

[Embodiments] Hereinafter, embodiments of the present invention will be explained using FIGS. 1 to 6. FIG. 1 shows an element configuration diagram of a CCD solid-state image sensor. The signal charge accumulated in the photodiode 1 is transferred to the vertical CCD register 2 during vertical blanking, and the transferred signal charge is transferred to the horizontal CCD register 2 via the transfer path 6 row by row.
The signal charge transferred to the CD register 3 and the horizontal CCD register is converted into a charge voltage by a built-in amplifier 4 via a transfer path 7, and is output from a terminal 5 to the outside. In this way, the vertical CCD register and the photodiode overlap in the plan view.

FIG. 2 shows a cross-sectional structural view of the portion indicated by the dashed line A-A' in the figure. Here, 20 is an N-type semiconductor substrate, 21 is a P-type impurity layer, 22 is an N-type impurity region that becomes a photodiode, and 25 is a P-type impurity region provided to suppress dark current on the semiconductor surface. . 24 is an N-type impurity region forming a channel of the vertical CCD register, and 23 provided on the outside thereof is a P-type impurity region for confining a depletion layer extending from 24 toward the substrate. 27 and 28 formed through the oxide film 26
is a polysilicon gate for driving the vertical CCD register. Here, horizontally adjacent N-type impurity regions 22 may partially overlap each other due to lateral diffusion of impurities.

FIG. 3 shows a cross-sectional structural diagram of a portion indicated by a dashed line along line B-B' in FIG. Here, 20 is an N-type semiconductor substrate, 21 is a P-type impurity layer, 22 is an N-type impurity region that becomes a photodiode, and 25 is a P-type impurity region provided to suppress dark current on the semiconductor surface. . 24 is an N-type impurity region forming a channel of the vertical CCD register, and 23 provided on the outside thereof is a P-type impurity region for confining a depletion layer extending from 24 toward the substrate. 27 and 28 formed through the oxide film 26 are polysilicon gates for driving the vertical CCD register. If the N-type impurity region 22 that becomes a photodiode is discontinuously formed in the N-type impurity region that forms the channel of the vertical CCD register, the channel potential becomes non-uniform at the boundary, which reduces the transfer efficiency of the vertical CCD register. cause deterioration. Therefore, the boundaries of the N-type impurity regions 22 that become vertically adjacent photodiodes are as follows:
By matching the boundary between the polysilicon gates 27 and 28 where the transfer electric field is maximum, deterioration of the transfer efficiency of the vertical CCD register is prevented.

Next, the principle of operation of this element will be explained using FIGS. 4 to 6.

FIG. 4 is a partial cutout of the cross-sectional view of the element shown in FIG. 2, and FIGS. 5 and 6 show potential diagrams corresponding to FIG. 4. In FIG. 4, 20 to 27 are the same as in FIG.

As shown in FIG. 5, during the signal accumulation period, signal charges are accumulated in the shaded area as shown by the solid line. This corresponds to region 22 in FIG. Next, by applying a high voltage to the gate 27, the signal charges accumulated in the photodiode 22 can be transferred to the channel region 24, as shown by the dotted line. Once transferred, the signal charge is transferred within the channel of the vertical CCD register and read out to the outside via the horizontal CCD register and output amplifier.

FIG. 6 shows driving conditions for changing the signal accumulation time. By applying a high voltage to the N-type substrate during an arbitrary signal accumulation period, the signal charge indicated by the solid hatched area can be swept out toward the substrate.

In this way, signal charges can be read out even if part of the photodiode, which is the light receiving section, is placed below the vertical CCD register, which is the signal charge transfer section. Therefore, the area of the photodiode can be increased, and the device area can be used effectively.

Another embodiment of the present invention will be described with reference to a cross-sectional view of the device shown in FIG. Here, 20 to 28 are the same as in FIG. Reference numeral 29 denotes a P-type impurity region provided to ensure electrical isolation between the N-type impurity regions 22 of the photodiode. Especially when the lateral diffusion of the N-type impurity region 22 becomes large, the N-type impurity region 2 of the photodiode
Mixing of signal charges between the two can be prevented.

Another embodiment of the present invention will be explained using the cross-sectional structure diagram of the device shown in FIG. Here, 20 to 28 are the same as in FIG. 30 is a P-type impurity region provided to ensure electrical isolation between the photodiodes 22.

Another embodiment of the present invention will be described with reference to a cross-sectional view of the device shown in FIG. Here, 20 to 28 are the same as in FIG. On the top surface of this element, 32 color filters, 3
By forming microlenses through the protective film described in step 3, it is also possible to obtain a color image sensor with even higher sensitivity.At this time, if the positional relationship between the color filter and the microlens is shifted by half a pitch from each other, color mixing occurs. can be prevented.

[0018]

As described above, according to the present invention, by arranging a part of the photodiode as the light receiving section below the vertical CCD register as the signal charge transfer section, it is possible to effectively utilize the device area.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an element according to the present invention (first embodiment).

FIG. 2 A of a planar configuration diagram of an element of the present invention (first embodiment)
-A sectional view of part A'.

FIG. 3 B of a planar configuration diagram of an element of the present invention (first embodiment)
- A sectional view of the B' section.

FIG. 4 A of a planar configuration diagram of an element of the present invention (first embodiment)
- Part of a cross-sectional view of section A'.

FIG. 5 A of a planar configuration diagram of an element of the present invention (first embodiment)
- Potential diagram (readout of signal charge) for a part of the cross-sectional view of section A'.

FIG. 6 A of a planar configuration diagram of an element of the present invention (first embodiment)
- Potential diagram (sweeping out of signal charges) for a part of the cross-sectional view of section A'.

FIG. 7 is a plan view of a conventional element.

FIG. 8 is a sectional view of a conventional element.

FIG. 9 is a sectional view of an element of the present invention (second embodiment).

FIG. 10 is a cross-sectional view of an element according to the present invention (third embodiment).

FIG. 11 is a sectional view of an element of the present invention (fourth embodiment).

[Explanation of symbols]

1... Photodiode, 2... Vertical CCD register, 20...
N-type semiconductor substrate, 21...P-type impurity layer, 22...N-type impurity layer of photodiode, 23...P-type impurity layer, 24...N
type impurity diffusion layer, 25...P type impurity layer, 27...polysilicon gate.

Claims (1)

[Claims] 1. A solid-state imaging device comprising a plurality of photodiodes formed on the same semiconductor substrate, a means for transferring signal charges from each photodiode, and a built-in circuit for detecting the signal charges from the transfer means. A solid-state imaging device characterized in that a portion of a photodiode extends below a transfer means.