JPH04344964A - Data transfer controller - Google Patents

Abstract

PURPOSE:To easily perform loop back transmission processing, active transmission processing, and inter-transmission line transfer processing. CONSTITUTION:The data transfer controller is provided with a data buffer 5 storing data received from a transmission line and free buffers 15 and 16 for transmission only to be used when an active data transmission is required by the generation of an event other than a data buffer 6. It is also provided with a transmission queue capable of setting plural pairs of information such as the transmission destination of data or information on from which buffer or to which transmission line the data should be transmitted. A transmission demand is performed by enqueuing each information to the transmission queue, and the transmission processing is performed according to the enqueued order.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission control device.

0002

[Prior Art] Figure 4 shows, for example, "C-bus input/output control mechanism manual" published by Mitsubishi Electric Corporation (November 2, 1986).
FIG. 0 is a block diagram showing the configuration of a conventional data transmission control device described in .

In FIG. 4, reference numeral 1 is a microprocessor that controls data transmission; 2 is a memory in which programs necessary for control by the microprocessor 1, transmitted and received data, etc. are stored; 3 and 4 are transmission lines; 5 is a data buffer for buffering received data from transmission line 3; 6 is a data buffer for buffering transmission data for transmission line 3; 7 is a driver/receiver for transmission line 3; 8 is a driver/receiver for transmission line 4. , 9 to 14 are gates.

[0004] Each of the gates 9 to 14 is controlled to open and close by the microprocessor 1, and the gate 9 is connected between the data buffer 5 and the driver/receiver 7, and the gate 10 is connected between the data buffer 5 and the gate 14. 11 is located between the data buffer 6 and the driver/receiver 7, the gate 12 is located between the data buffer 6 and the gate 14, and the gate 14 is located between the gates 10 and 12 and the driver/receiver 8. . Gate 13 is located between gates 10, 12, and 14 and microprocessor 1, and is opened and closed for inputting and outputting data between microprocessor 1 and data buffer 5, data buffer 6, and transmission line 4. controlled.

Next, the operation of the conventional data transmission control device as described above will be explained. Data received from the transmission path 3 is stored in the data buffer 5 via the driver/receiver 7 and gate 9. Next, according to an instruction from the microprocessor 1, the data stored in the data buffer 5 is transferred from the data buffer 5 to gate 10 and gate 1.
4. Transmission to transmission line 4 via driver/receiver 8 is attempted. As a result, data is transferred from transmission line 3 to transmission line 4.

On the other hand, the data received from the transmission path 4 is
The signal is stored in the data buffer 6 for the transmission line 3 via the driver/receiver 8, gate 14, and gate 12. Further, when the data stored in the data buffer 6 is started to be sent to the transmission line 3 by a command from the microprocessor 1, the data is transferred to the gate 11 and the driver/receiver 7.
Sent via . As a result, data is transferred from transmission line 4 to transmission line 3.

As described above, in the conventional data transmission control device, the data buffer that buffers the data received from the transmission path and the data buffer that buffers the data transmitted to the transmission path 3 are designated by reference numerals 5 and 6, respectively. These data buffers 5,
Data transfer between transmission lines 3 and 4 is realized at 6.

[0008]

[Problems to be Solved by the Invention] Conventional data transmission control devices have the above-mentioned configuration, so when data received from a transmission path is looped back and sent to the same transmission path, or when the device itself is actively In cases such as when it is necessary to send data to the other side, it is necessary to use the existing data buffer 5 and data buffer 6, and the loopback transmission process, the active transmission process, the reception process from the transmission path, and the other It is necessary to control contention for the transmission process for the transmission path. However, conventional devices have problems such as not having such a function.

The present invention has been made in view of the above-mentioned circumstances, and it facilitates the return transmission processing, active transmission processing, and inter-transmission line transfer processing, and also improves the priority of these for contention control. The purpose of the present invention is to provide a data transmission control device that can be easily changed.

0010

[Means for Solving the Problems] A data transmission control device according to the present invention has a buffer dedicated to transmission in addition to a data buffer for transmitting and receiving data to and from a transmission path, and also has a buffer for transmitting data from any of the buffers. information on whether to send the data, information on which transmission path to send the data to,
and a transmission queue in which a plurality of sets of data transmission destination information can be set.

[0011]

[Operation] In the data transmission control device of the present invention, the transmission request includes information on which buffer to send data to the transmission queue, information on which transmission path to send the data to, and information on the data transmission destination. The transmission process is performed by enqueuing the data as a set, and the transmission process is performed according to the order and contents enqueued in this transmission queue.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the configuration of a data transmission control device according to the present invention. In FIG. 1, the same reference numerals as those in FIG. 4 referred to in the description of the conventional example above indicate the same or corresponding parts.

In FIG. 1, reference numeral 1 is a microprocessor that controls data transmission, 2 is a memory in which programs necessary for control by the microprocessor 1, transmitted and received data, etc. are stored, 3 and 4 are transmission lines; 5 is a data buffer for buffering received data from transmission line 3; 6 is a data buffer for buffering transmission data for transmission line 3; 7 is a driver/receiver for transmission line 3; 8 is a driver/receiver for transmission line 4. , 9 to 14 are gates, and 15 is a free buffer dedicated to transmission to the transmission line 3, which is attached to the data buffer 5. Further, reference numeral 16 denotes a free buffer dedicated to transmission to the transmission path 4, which is attached to the data buffer 6.

Each of the gates 9 to 14 is controlled to open and close by the microprocessor 1, and the gate 9 is connected between the data buffer 5 and the driver/receiver 7, and the gate 10 is connected between the data buffer 5 and the gate 14. 11 is located between the data buffer 6 and the driver/receiver 7, the gate 12 is located between the data buffer 6 and the gate 14, and the gate 14 is located between the gates 10 and 12 and the driver/receiver 8. . Gate 13 is located between gates 10, 12, and 14 and microprocessor 1, and is opened and closed for inputting and outputting data between microprocessor 1 and data buffer 5, data buffer 6, and transmission line 4. controlled.

Next, the operation of the data transmission control device of the present invention having the above-described configuration will be explained.

Data received from the transmission path 3 is stored in the data buffer 5 via the driver/receiver 7 and gate 9. If the data stored in the data buffer 5 is for a certain device connected to the transmission path 4, the data is sent from the data buffer 5 via the gates 10, 14, and driver/receiver 8 according to instructions from the microprocessor 1. Then, transmission to the transmission line 4 is activated. As a result, data is transferred from the transmission path 3 to the transmission path 4.

On the other hand, data received from the transmission line 4 is stored in the data buffer 6 for the transmission line 3 via the driver/receiver 8, gate 14, and gate 12. If the data stored in the data buffer 6 is for a certain device connected to the transmission line 3,
According to the instructions of the microprocessor 1, the data buffer 6
From there, a transmission activation is applied to the transmission line 3 via the gate 11 and the driver/receiver 7. As a result, data is transferred from the transmission path 4 to the transmission path 3.

By the way, in the data transmission control device of the present invention, as shown in FIG. 1, a free buffer 15 is provided in the data buffer 5 for the transmission path 3, and a free buffer 16 is provided in the data buffer 6 for the transmission path 3. It is being In addition, from the free buffer 15, the transmission line 4
Assume that it is possible to transmit only to the transmission path 3 from the free buffer 16.

[0020] Data buffer 5, free buffer 15,
When transmitting data, the data buffer 6 and the free buffer 16 perform transmission processing only by enqueuing data into a transmission queue.

FIG. 2 shows an example of the configuration of a transmission queue. In the embodiment shown in FIG. 2, the transmit queues are A, B, C,
Four blocks D are provided, and each block is configured with information indicating the type of buffer, destination transmission path, and destination address, respectively. Further, in the transmission queue, blocks A and B in the upper half are transmission queues for the transmission path 3, and blocks C and D in the lower half are transmission queues for the transmission path 4. Note that in this embodiment, each transmission line 3, 4
The number of transmission queues for this is two, and no priority is set between them.

In FIG. 1, for example, when data received from transmission path 3 is to be transmitted to transmission path 4, the information necessary for block C of the transmission queue in FIG. Enqueue is performed by setting the transmission path 4 as the transmission path and setting the address of another device connected to the transmission path 4 as the destination address.

Now, the microprocessor 1 transmits data to the transmission line according to the information enqueued as described above, but if a transmission error occurs at that time,
It becomes necessary to notify other devices connected to the transmission path 3 and transmission path 4 of the occurrence of an error, that is, to perform active data transmission. In such a case, the microprocessor 1 sets error occurrence reporting data in the free buffer 15 and the free buffer 16 shown in FIG. Similarly, necessary information is set in block A of the transmission queue shown in FIG. As a result, error occurrence reporting data is transmitted to both transmission paths 3 and 4, respectively.

[0024] In the above embodiment, transmission queues are allocated to a queue composed of blocks A and B and a queue composed of blocks C and D, respectively, corresponding to each transmission direction. Although a configuration in which the transmission queue is uniquely set has been described, a configuration having only one transmission queue configured to allow transmission in any direction can also produce the same effects as in the above embodiment.

For example, as shown in FIG. 3, while blocks E, F, G, and H all set transmission queues that can transmit to both transmission paths 3 and 4,
The buffer can be transmitted from any of the data buffer 5, data buffer 6, free buffer 15, and free buffer 16 shown in FIG. 1 to any of the transmission paths 3 and 4.

By defining in this way, the transmission line 3
After storing the data received from the data buffer 5,
Assume that necessary information is set in block E of the transmission queue in FIG. 3 and transmitted to the transmission path 4, but a transmission error occurs at this time. In this case, it is necessary to report the occurrence of a transmission error to the devices connected to the transmission line 3 and the transmission line 4, but the microprocessor 1 sends the error occurrence reporting data for the transmission line 3 to the data buffer 5 and the free buffer 15. The error occurrence report data for the transmission line 4 is set respectively in the block F of the queue shown in FIG.
, G may be set with the necessary information.

Furthermore, in the above embodiment, the transmission queue does not have a priority set between each block that is a queue component, but the priority may be included in the necessary information of the queue components. .

[0028]

[Effects of the Invention] As detailed above, according to the present invention,
In addition to the conventional sending data buffer for the transmission path, a free buffer exclusively for sending is added, and a queue is also provided to allow both the conventional sending data buffer and the free buffer to perform sending processing efficiently. This has the effect of making the functions of the equipment more intelligent.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration example of a data transmission control device according to the present invention.

FIG. 2 is a schematic diagram illustrating the contents of a transmission queue provided in the data transmission control device according to the present invention.

FIG. 3 is a schematic diagram illustrating the contents of a transmission queue provided in the data transmission control device according to the present invention.

FIG. 4 is a block diagram showing a configuration example of a conventional data transmission control device.

[Explanation of symbols]

3 Transmission line 4 Transmission line 5 Data buffer 6 Data buffer 15 Free buffer 16 Free buffer

Claims (1)

[Claims] [Claim 1] At least two capable of transmitting and receiving data
A data transmission control device having a data transmission/reception buffer connected to a transmission path and capable of transmitting/receiving data to each of the transmission paths, a buffer dedicated to data transmission, a buffer dedicated to data transmission, and the data transmission/reception buffer. and a transmission control queue capable of setting a plurality of sets of information specifying which of the transmission paths data should be sent from, information specifying which of the transmission paths data should be sent to, and information specifying destinations. A data transmission control device characterized by: