JPH04343587A - Method for driving solid-state image pickup device - Google Patents

Abstract

PURPOSE:To increase the transfer speed of signal charge to twice the convensional value without changing the frequency of a transfer clock. CONSTITUTION:Three phase clocks, i.e., a clock phi1 consisting of the repeats of high and low levels, a clock phi2 having an opposite phase to the phase of the clock phi1 and a clock phi3 having an intermediate DC level, are used and clocks consisting of the repeats of clocks phi1, phi3, phi2, phi3, phi1 are impressed to the 1st and 2nd polysilicone electrodes 5, 6 to attain the rapid transfer of signal charge.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to solid-state imaging devices, and more particularly to a charge transfer method.

0002

[Prior Art] A solid-state imaging device usually includes a photoelectric conversion device that converts incident light into an electrical signal, and a charge transfer device that sequentially transfers and outputs the electrical signals (charges) obtained by the photoelectric conversion device. ing.

FIG. 3A shows a cross-sectional view of a charge transfer device of a conventional solid-state imaging device. The charge transfer device includes a first charge transfer device on an N-type well 3 on a P-type well 2 formed in an N-type semiconductor substrate 1.
It has a two-layer polysilicon structure in which polysilicon electrodes 5 and second polysilicon electrodes 6 are alternately arranged, and a P-type region 4 is formed under the second polysilicon electrode. The same clock φ1 is applied to the adjacent first polysilicon electrode and second polysilicon electrode, and a clock φ2 having an opposite phase to φ1 is applied to the next first polysilicon electrode and second polysilicon electrode. are repeated alternately to transfer charge.

FIG. 3B shows a clock applied to the charge transfer device. φ1 consists of high level VH and low level VL, and φ2 has the opposite phase to φ1. The potential of the charge transfer device and the state of signal charge transfer at times t1, t2, and t3 in FIG. 3B are shown in FIGS. 4A, 4B, and 4C, respectively. Figure 4(A)
(t=t1), the signal charge at position D is 1/2
In FIG. 4(B) (t=t2) after a cycle, 1 bit has been transferred and is at position E, and after another 1/2 cycle, in FIG. 4(C)(
At t=t3), it is at the position of F, where one bit has been further transferred. As a result, the signal charge is 2 during one clock cycle.
Bits are transferred.

[0005]

[Problems to be Solved by the Invention] In the conventional charge transfer method using a two-phase clock, there is an upper limit frequency fmax for the clock frequency for completely transferring signal charges, and it is necessary to transfer signal charges faster than fmax. There was a problem that it could not be transferred.

[0006]

[Means for Solving the Problems] In the charge transfer method of the present invention, in addition to a clock φ1 consisting of a high level VH and a low level VL, and a clock φ2 having the opposite phase of φ1, a clock VH
A constant intermediate potential φ3 that is smaller than VL and larger than VL
By using these three clocks, signal charges are transferred.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1(A) is a cross-sectional view of the charge transfer device of the present invention. The connection of the wiring for supplying the driving clock to the polysilicon electrode is different from the conventional example, and the other parts are the same as the conventional example shown in FIG. 3(A). It has a structure. FIG. 1(B) shows a clock used in this charge transfer device. The present invention differs from conventional solid-state imaging devices in the clock applied to the first polysilicon electrode 5 and the second polysilicon electrode 6 of the charge transfer device.
Charge transfer is performed using a three-phase clock using a clock φ1 consisting of a high level VH and a low level VL, a clock φ2 having the opposite phase of φ1, and a DC level φ3 having an intermediate potential VM smaller than VH and larger than VL. The same clock is applied to the adjacent first polysilicon electrode and second polysilicon electrode, and φ1,
φ3 , φ2 , φ3 , φ1 , φ3 , φ2 , φ
3. It is applied repeatedly.

Time t1, t2, t3 in FIG. 1(B)
The potential of the charge transfer device and the state of charge transfer are shown in FIGS. 2A, 2B, and 2C, respectively. The signal charge that was at position A in Figure 2 (A) (t = t1) is transferred by 2 bits and is located at position B in Figure 2 (B) (t = t2) 1/2 period later, and further Figure 2 after 1/2 cycle
(C) At (t=t3), two more bits are transferred and placed at the C position. As a result, four bits of signal charge are transferred during one clock cycle, and the charge transfer speed is twice as high as that of the conventional technology while using the same frequency clock.

0010

Effects of the Invention As explained above, the present invention transfers signal charges using a three-phase clock in which an intermediate potential is added to the conventional two-phase clock. It becomes possible to transfer signal charges at a speed of . Since the frequency of the clock used is the same as in the past, it has the advantage that the power consumption of the device is also the same as in the past.

[Brief explanation of drawings]

FIG. 1 (A) is a sectional view of the present invention, and (B) is a clock diagram used in the present invention.

FIG. 2 is a potential diagram showing the state of charge transfer according to the present invention.

FIG. 3A is a cross-sectional view of a conventional example, and FIG. 3B is a clock diagram used in the conventional example.

FIG. 4 is a potential diagram showing the state of conventional charge transfer.

[Explanation of symbols]

1 N-type semiconductor substrate 2 P-type well 3 N type well 4 P-type region 5 First polysilicon electrode 6 Second polysilicon electrode

Claims (1)

[Claims] 1. A solid-state imaging device comprising a photoelectric conversion device that converts incident light into an electrical signal and a charge transfer device that transfers the electrical signal obtained by the photoelectric conversion device, a driving clock applied to the charge transfer device. In addition to the two-phase clocks φ1 and φ2 that are in opposite phases to each other, a DC signal between the high level and the low level of the clocks is added.
Using a 3-phase clock with a level clock φ3 added,
Adjacent electrodes of the charge transfer device are grouped into one set, and the drive clocks applied to each set of electrodes are sequentially φ1, φ3,
A method for driving a solid-state imaging device, characterized in that φ2 and φ3 are applied repeatedly.