JPH09148562A - Solid state image sensing element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce transfer time of signal charges from a vertical transfer register to a horizontal transfer register. SOLUTION: Two gate parts are formed between a vertical transfer register 23 and a horizontal transfer register 26. One gate part on the vertical transfer register 23 side is driven by a clock pulse ϕV1 of any one phase of a vertical transfer clock pulse for driving the vertical transfer register 23. The other gate part on the horizontal transfer register 16 side is driven by an independent clock pulse ϕVH.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a CCD solid-state imaging device.

[0002]

Prior Art and Problems to be Solved by the Invention FIG.
FIG. 7 shows an example of a conventional interline transfer system (IT system) CCD solid-state imaging device. As shown in FIG. 5, in this CCD solid-state image pickup device 1, a plurality of light receiving parts 2 are arranged in a matrix, and a vertical transfer register 3 having a CCD structure is formed on one side of each light receiving part row. Three
The horizontal transfer register 4 of CCD structure is connected to the final stage of
An output unit 5 is connected to the final stage of the horizontal transfer register 4. In this example, the vertical transfer register 3 is driven by four-phase vertical transfer clock pulses φV ₁ , φV ₂ , φV ₃ and φV ₄ , and the horizontal transfer register 4 is driven by two-phase horizontal transfer clock pulses φH ₁ and φH ₂ . Driven.

In this CCD solid-state image sensor 1, the light receiving section 2
Signal charges corresponding to the amount of received light are accumulated, the signal charges of the light receiving unit 2 are read out to the vertical transfer register 3 through the read gate unit during the vertical blanking period, and the signal of one horizontal line is output during the horizontal blanking period. The charges are transferred from the vertical transfer register 3 to the horizontal transfer register 4. Then, the signal charge is transferred to the horizontal transfer register 4 in one horizontal scanning period.
It is transferred inside, and converted into electric charge-voltage through the output unit 5 and output.

In the vertical transfer register 3, as shown in FIG. 7, first transfer electrodes to which four-phase clock pulses φV _{1 to} φV ₄ are respectively applied on a transfer region 6 made of a semiconductor region through an insulating film 8. 71, the second transfer electrode 72, the third transfer electrode 73, and the fourth transfer electrode 74 are sequentially and repeatedly formed,
The third transfer electrode 73 is arranged at the final stage of the vertical transfer register 3. Reference numeral 9 denotes a transfer electrode of the horizontal transfer register 4.

Four-phase vertical transfer clock pulses φV _{1 to} φ
V ₄ is applied to each of the transfer electrodes 71 to 74 at the timing shown in FIG.
Is applied to The signal charge e is transferred from the vertical transfer register 3 to the horizontal transfer register 4 as shown in the potential diagram of FIG. That is, the signal charges e accumulated under the first and second transfer electrodes 71 and 72 at the time T ₀ are changed from the time T ₁ to the time T ₆ within the horizontal blanking period by the vertical transfer clock pulses φV _{1 to} φV ₄ . After that, it is transferred to the horizontal transfer register 4. That is, the vertical-horizontal transfer is completed at time T ₆ . Then, at time T ₈ , the next signal charge is accumulated under the first and second transfer electrodes 71 and 72.

By the way, a high-definition television (HDT
In the case of a CCD solid-state image pickup device having two horizontal transfer registers such as a solid-state image pickup device for V), signal charges are distributed so as to be distributed from the vertical transfer register to the two horizontal transfer registers during a limited horizontal blanking period. I have to transfer.

The transfer of signal charges between the two horizontal transfer registers (that is, horizontal-horizontal transfer) is performed after the vertical-horizontal transfer is completed. In particular, in the solid-state image pickup device for HDTV, the horizontal blanking period is also shortened. Therefore, it is desired to shorten the time required for vertical-horizontal transfer as much as possible.

On the other hand, frame interline transfer (FI
In the T) type CCD solid-state image pickup device, as shown in FIGS. 8 to 10, a configuration is proposed in which the vertical-horizontal transfer is completed more quickly. As shown in FIG. 8, this frame interline transfer CCD solid-state imaging device 10 has a plurality of light receiving parts 2 arranged in a matrix, and a vertical transfer register 3 having a CCD structure is provided on one side of each light receiving part row. The image pickup section 11, a storage section 13 having a plurality of vertical transfer registers 12 of CCD structure corresponding to the vertical transfer register 3 of the image pickup section 11, a horizontal transfer register section 4 of CCD structure, and its final stage. And an output unit 5 connected to the.

The vertical transfer register 3 of the image pickup section 11 has four phases of vertical transfer clock pulses φIV ₁ , φIV ₂ , φIV.
Driven by ₃ and φIV ₄ , the vertical transfer register 12 of the accumulator 13 has a 4-phase vertical transfer clock pulse φMV.
_The horizontal transfer register 4 is driven by ₁ , φMV ₂ , φMV ₃ and φMV ₄ , and the horizontal transfer register 4 is driven by two-phase horizontal transfer clock pulses φH ₁ and φH ₂ .

And, in particular, in this case, FIGS.
2, two gate units 14 and 15 are provided between the final stage of the vertical transfer register 12 of the storage unit 13 and the horizontal transfer register 4, and the first gate unit 14 and the second gate unit 15 have Vertical transfer clock pulses φMV _{1 to} φM, respectively
Clock pulses φVH ₁ and φVH ₂ independent of V ₄ are applied.

In the CCD solid-state image pickup device 10, the signal charges of the light receiving portion 2 are read out to the vertical transfer register 3 of the image pickup portion 11 within the vertical blanking period, and the vertical transfer register of the storage portion 13 is also read from the vertical transfer register 3. Signal transferred to the vertical register 12 at a high speed and then accumulated in the vertical register 12 during the first and second signal charges within the horizontal blanking period.
Is transferred to the horizontal transfer register 4 via the gate units 14 and 15. Then, the signal charges are transferred to the horizontal transfer register 4 in one horizontal scanning period, converted into charges by the output unit 5, and output.

In the vertical transfer register 12 of the storage unit 13,
As shown in FIG. 10, the transfer region 17 formed of a semiconductor region
The first transfer electrodes 16 to which the four-phase vertical transfer clock pulses φIV _{1 to} φIV ₄ are respectively applied via the insulating film 18
1, second transfer electrode 162, third transfer electrode 163 and fourth
The transfer electrodes 164 are sequentially and repeatedly formed, and the fourth electrode at the final stage is formed.
The gate electrodes 191 and 192 of the two gate portions 14 and 15 are arranged downstream of the transfer electrode 164. Reference numeral 9 is a transfer electrode of the horizontal transfer register 4.

Four-phase vertical transfer clock pulses φMV _{1 to} φMV applied to the transfer electrodes 161 to 164 of the storage section 13.
_The independent clock pulses φVH ₁ and φVH ₂ given to ₄ and the two gate electrodes 191 and 192 are applied at the timing shown in FIG. The transfer of the signal charge from the vertical transfer register 12 of the storage unit 13 to the horizontal transfer register 4 is performed as shown in the potential diagram of FIG.

That is, the signal charge e accumulated under the first gate portion 14 at the time point T ₀ is converted into the vertical transfer clock pulse φ.
Independent clock pulse φV synchronized with MV _{1 to} φMV ₄
It is transferred to the horizontal transfer register 4 through the time points T _{1 to} T ₃ within the horizontal blanking period by H ₁ and φVH ₂ .
That is, the vertical-horizontal transfer is completed at time T ₃ . Then, at time T ₈ , the next signal charge e is accumulated under the first gate portion 14.

In this configuration, four-phase clock pulses φM
First and second gate electrodes 191 and 192 are provided separately from the transfer electrodes 161 to 164 to which V _{1 to} φMV ₄ are applied, and the signal charge e before being sent to the horizontal transfer register 4 is provided under the first gate electrode 191. By accumulating and transferring charges through the second gate electrode 192 between the first gate electrode 191 and the horizontal transfer register 4, CC of FIG.
Compared with the D solid-state image pickup device 1, the time for vertical-horizontal transfer can be shortened.

By the way, the transfer electrode of the CCD solid-state image pickup device is usually formed of polycrystalline silicon. In the CCD solid-state image pickup device for HDTV, a metal such as Al is formed on the transfer electrode of the polycrystalline silicon to prevent propagation delay. A so-called shunt wiring, which is a backing wiring made of a material, is formed. The shunt wiring has a buffer layer made of polycrystalline silicon interposed between the transfer electrode and the shunt wiring in order to prevent the potential from being disturbed by the Al-Si alloy with the transfer electrode of polycrystalline silicon. Contact is made between the shunt wiring and the transfer electrode via. In this case, one of the buffer layers
The transfer electrode and the buffer layer are in contact with each other, and the buffer layer and the shunt wiring are in contact with each other in the other position of the buffer layer.

The shunt wiring including the buffer layer is formed in the vertical direction along the vertical transfer register 3 in the image pickup section 11 and in the horizontal direction in the storage section so as to be orthogonal to the vertical transfer register 12. Usually, the transfer electrodes 161 to 164 and the gate electrodes 191 to 192 of the vertical transfer register are formed of the first and second layers of polycrystalline silicon, and the buffer layer is formed of the third layer of polycrystalline silicon. The transfer electrode 9 is formed of second-layer and third-layer polycrystalline silicon.

First and second gate electrodes 191 and 19
2 is formed very thin, but since the vertical transfer register 12 and the shunt wirings of the first and second gate portions are formed horizontally in the storage portion 13, the first and second portions are formed.
It is possible to process the shunt wiring on the gate part.

However, it has been difficult to apply the structure of the first and second gate portions 14 and 15 to the interline transfer (IT) type CCD solid-state image pickup device of FIG. The reason is that the shunt wiring and the buffer layer of the vertical transfer register 3 are formed in the vertical direction, the shunt wiring and the buffer layer of the two gate portions 14 and 15 are arranged in the horizontal direction, and the buffer layer is the third layer. Since it is made of polycrystalline silicon, the shunt wiring including the vertical transfer register 3 and the second buffer layer, which is made of polycrystalline silicon of the third and third layers and includes two buffer layers parallel to a narrow region with the horizontal transfer register, is processed. It was extremely difficult to manufacture and it was substantially impossible to manufacture.

In view of the above points, the present invention provides a solid-state image pickup device which solves the problem of shunt wiring and shortens the time for vertical-horizontal transfer.

[0021]

In the solid-state image pickup device according to the present invention, two gate sections are provided between a vertical transfer section and a horizontal transfer section, and one gate section on the vertical transfer section side is a vertical transfer section. Is driven by a clock pulse of any one phase of the vertical transfer clock pulse for driving, and the other gate section on the side of the horizontal transfer section is driven by a clock pulse independent of the vertical transfer clock pulse.

In this structure, by having two gate sections between the vertical transfer section and the horizontal transfer section, it is possible to shorten the time for transferring the signal charges from the vertical transfer section to the horizontal transfer section. In addition, one of the two gate sections is driven by the clock pulse of the vertical transfer section, and the other gate section is driven by an independent clock pulse.
Only one independent clock pulse is required, making the timing generator easier to create. Furthermore, the shunt wiring of the gate portion is only required to be one gate portion and can be manufactured.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a CCD solid-state image sensor according to the present invention will be described below with reference to FIGS.

FIG. 1 illustrates the present invention in an interline transfer (I
FIG. 3 is a schematic configuration diagram when applied to a T) type CCD solid-state imaging device. In this CCD solid-state imaging device 21, a plurality of light receiving portions 22 are arranged in a matrix, and a vertical transfer portion, that is, a vertical transfer register 23 having a CCD structure is formed on one side of each light receiving portion row. Figure 2 at the end
Further, a horizontal transfer section, that is, a horizontal transfer register 26 having a CCD structure is connected through two gate sections 24 and 25 shown in FIG. 4, and an output section 27 is connected to the final stage of the horizontal transfer register 26.

The vertical transfer register 23 is driven by four-phase vertical transfer clock pulses φV ₁ , φV ₂ , φV ₃ and φV ₄ , and the horizontal transfer register 26 is driven by two-phase horizontal transfer clock pulses φH ₁ and φH ₂ . To be done.
Further, of the two gate units 24 and 25, one gate unit 24 on the vertical transfer register 23 side has a clock pulse of any one phase of the vertical transfer clock pulses φV _{1 to} φV ₄ , the first phase in this example. is driven by the clock pulses .phi.V _1, the other of the gate portion 25 of the horizontal transfer register 26 side, the vertical transfer clock pulses φV ₁ ~φV ₄ is driven by an independent clock pulse FaiHV.

FIG. 2 is an enlarged plan view of a main part from the vertical transfer register 23 to the horizontal transfer register 26. The vertical transfer register 23 includes four transfer electrodes, that is, a first transfer electrode 31, a second transfer electrode 32, and a third transfer electrode on a transfer region 28 formed of a semiconductor region via an insulating film 29 (see FIG. 4). 33 and the fourth transfer electrode 34 are sequentially and repeatedly formed. The second and fourth transfer electrodes 32 and 34 are formed of the first-layer polycrystalline silicon, and the first and third transfer electrodes 31 and 33 are formed of the second-layer polycrystalline silicon.
The transfer electrodes 31 to 34 are formed in a horizontal strip shape so as to be common to the vertical transfer registers 23 except for the light receiving section 22. The fourth transfer electrode 34 is formed at the final stage of the vertical transfer register 23.

The first gate portion 24 extends in the horizontal direction on the transfer region 28 via the gate insulating film 29 so as to communicate with each vertical transfer register 23.
The second gate portion 25 is formed by forming a strip-shaped second gate electrode 36 extending in the horizontal direction on the transfer region 28 via the gate insulating film 29 in the same manner. The first gate electrode 35 is formed of the second-layer polycrystalline silicon, and the second gate electrode 36 is formed of the first-layer polycrystalline silicon.

In the horizontal transfer register 26, two transfer electrodes 41 and 42 are sequentially and repeatedly formed through an insulating film 29, one transfer electrode 41 is formed of a second layer of polycrystalline silicon, and the other transfer electrode 42. Are formed of a third layer of polycrystalline silicon.

On each vertical transfer register 23, a buffer layer 43 [431, which is a third layer of polycrystalline silicon, is provided.
Shunt wiring 44 [441, 442, 443, 444] made of, for example, Al through 432, 433, 434].
Are formed, and the shunt wirings 44 are connected to the corresponding transfer electrodes 31 to 34 through the buffer layer 43. That is, the first every third shunt wiring 441 is connected to the first transfer electrode 31, and the second every third shunt wiring 44.
2 is connected to the second transfer electrode 32, and every third third shunt wiring 443 is connected to the third transfer electrode 33.
Every other three shunt wirings 444 are connected to the fourth transfer electrode 34. Then, the first every third shunt wiring 4
The buffer layer 43 connected to the first gate electrode 35.
It is extended and connected with.

Then, the first every third shunt wiring 4
41 vertical transfer clock pulse φV ₁Is applied, the second
Connect the vertical transfer clock pattern to the shunt wiring 442 every other
Ruth φV_TwoIs applied and the third every third shunt wiring
Vertical transfer clock pulse φV to 443_ThreeIs applied, the
Vertical transfer clock to every third shunt wiring 444
Pulse φV_FourIs applied. By this, the first transfer power
Clock pulse φV is applied to the pole 31 and the first gate electrode 35.₁But
The second transfer electrode 32, the third transfer electrode 33, and the
Clock pulse φV to each of the four transfer electrodes 34_Two, ΦV_ThreeOver
And φV_FourWill be applied.

On the other hand, a buffer layer 46 made of a third layer of polycrystalline silicon is formed so as to extend over the second gate electrode 36 and the first gate electrode 35, and the second gate electrode 3 is further formed.
A shunt wiring 446 made of, for example, Al is formed along the horizontal direction with a width extending over 6 and the first gate electrode 35, and the shunt wiring 446 and the second gate electrode 36 are connected via the buffer layer 46. An independent clock pulse φV is applied to the second gate electrode 36 through the shunt wiring 446.
H is applied.

In FIG. 2, 48 is a shunt wiring 4.
4 [441, 442, 443, 444 and 446] and the buffer layers 43 and 46, and 49 is a contact portion between the buffer layers 43 and 46 and the corresponding transfer electrodes 31 to 34 and the gate electrodes 35 and 36. is there.

Here, the gate electrode 3 of the first gate portion 24
The area of 5 is set to be larger than the areas of the transfer electrodes 31 to 34 of the vertical transfer register 23 and the gate electrode 36 of the second gate portion 25 as shown in FIG. This first gate portion 24
Below, a charge amount equivalent to the charge amount below the first and second transfer electrodes 31 and 32 is accumulated.

The clock pulse supplied to the first gate section 24 is
The clock pulse at the final stage of the vertical transfer register 23
It depends on the phase in which it is. In the example above, the final
Stage is the fourth phase clock pulse φV_FourIf it ends with
Therefore, the first phase clock pulse φV is applied to the first gate unit 24.₁To
Is being applied. In addition, the last stage is the first phase clock pulse
φV₁If it ends with,
Phase clock pulse φV _TwoAnd the final stage is the second phase clock
C pulse φV_TwoIf it ends with, the first gate unit 2
4th phase clock pulse φV_ThreeAnd the final stage is the third
Phase clock pulse φV_ThreeIf it ends with, the first game
The fourth phase clock pulse φV _FourTo give
To

FIG. 3 is a vertical transfer clock pulses φV ₁ ~φV ₄ of the present embodiment shows the timing of the independent clock pulse FaiVH, 4 transfers the signal charges e from the vertical transfer register 23 to the horizontal transfer register 4 At each time point T ₀ ~
The potential at T ₈ is shown.

In the CCD solid-state image pickup device 21 described above, the signal charge of the light receiving portion 22 is read out to the vertical transfer register 23 through the read gate portion during the vertical blanking period, and is read out within the horizontal blanking period, as described above. Then, the signal charge of one horizontal line is transferred from the vertical transfer register 23 to the horizontal transfer register 26, transferred in the horizontal transfer register 4 in one horizontal scanning period, converted into a charge-voltage by the output unit 27, and output.

In the CCD solid-state image pickup device 21, the vertical transfer register 23 and the horizontal transfer register 2 are particularly used.
By providing the first gate portion 24 and the second gate portion 25 to which the vertical transfer clock pulse φV ₁ and the independent clock pulse φVH are respectively applied between the six, the signal charge e from the vertical transfer register 23 to the horizontal transfer register 26 is provided. The transfer can be completed in a short time from time T ₀ to time T ₃ .

That is, as shown in FIG. 4, at time T ₀ , the first
The signal charge e accumulated under the gate portion 24 should be transferred to the horizontal transfer register 26 through the time points T _{1 to} T ₃ within the horizontal blanking period by the clock pulses φV ₁ and φVH shown at the timing of FIG. become. That is, the vertical-horizontal transfer of the signal charge e is completed at time T ₃ . Then, at time T ₈ , the next signal charge e is accumulated under the first gate portion 24.

The time of this vertical-horizontal transfer is the same as that of the example of FIG. 10 described above, and compared with the case of the conventional CCD solid-state image pickup device 1 of the interline transfer system shown in FIGS. The time can be greatly reduced. Moreover,
Compared with the conventional example shown in FIGS. 8 to 10, one independent clock pulse can be reduced, and the number of required terminals can be reduced, which facilitates the creation of the timing generator. At the same time, the number of device terminals can be reduced.

Further, since the independent clock pulse φVH is applied to only one gate portion (only the second gate portion 25), the shunt wiring 446 including the buffer layer 46 to the gate portion 25 has a margin. It can be formed, and the problem of the shunt wiring described above can be solved.

By making the area of the gate electrode 35 of the first gate portion 24 larger than that of each of the other transfer electrodes 31 to 34, the signal charge e can be accumulated in the first gate portion 24 during the horizontal scanning period. Good charge transfer is possible.

Further, the CCD solid-state image pickup device 21 is
It can be manufactured by the same process as conventional ones without requiring complicated processing.

Since the CCD solid-state image pickup device 21 of the interline transfer system of this example can shorten the vertical-horizontal transfer time, CCD solid-state image pickup for HDTV having a plurality of, for example, two horizontal transfer registers. It is suitable if applied to an element.

In the above example, an interline transfer type CCD
Although it is applied to the solid-state image pickup device, it is also applicable to other CCD solid-state image pickup devices of the frame interline transfer system.

[0045]

According to the solid-state image sensor of the present invention, two gate sections are arranged between the vertical transfer section and the horizontal transfer section, and one gate section on the vertical transfer section side drives the vertical transfer section. Since the vertical transfer clock pulse of that phase is applied and the independent clock pulse is applied to the other gate section on the horizontal transfer section side, the time required for vertical-horizontal transfer of signal charges can be shortened. You can

Further, as compared with the conventional example of FIG. 8, one independent clock pulse can be reduced, the timing generator can be made easier, and the configuration can be simplified. At the same time, the number of terminals of the image sensor can be reduced.

By making the gate electrode area of one gate portion on the vertical transfer portion side larger than the area of each transfer electrode of the vertical transfer portion, signal charges can be stored under one gate portion during the horizontal scanning period. , Good charge transfer.

The shunt wiring can be easily formed on the gate portion, and in particular, it can be applied to an interline transfer type CCD solid-state image pickup device.

Further, it is suitable for application to, for example, a CCD solid-state image pickup device for a high-definition television having a plurality of horizontal transfer sections.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an example of a solid-state image sensor according to the present invention.

FIG. 2 is an enlarged plan view of a main part of the solid-state image sensor according to the present invention.

FIG. 3 is a timing chart of drive pulses according to the present invention.

FIG. 4 is a potential diagram during vertical-horizontal transfer according to the present invention.

FIG. 5 is a schematic configuration diagram showing an example of a conventional solid-state imaging device.

FIG. 6 is a timing chart of the drive pulse of FIG.

FIG. 7 is a potential diagram at the time of vertical-horizontal transfer in FIG.

FIG. 8 is a schematic configuration diagram showing another example of a conventional solid-state imaging device.

9 is a timing chart of the drive pulse in FIG.

10 is a potential diagram at the time of vertical-horizontal transfer in FIG.

[Explanation of symbols]

 21 CCD solid-state image sensor 22 Light receiving part 23 Vertical transfer register 24, 25 Gate part 26 Horizontal transfer register 27 Output part 31-34, 41, 42 Transfer electrode 35, 36 Gate electrode 43 Buffer layer 44 [441-444] Shunt wiring

Claims (5)

[Claims] 1. Two gate units are provided between a vertical transfer unit and a horizontal transfer unit, and one of the gate units on the vertical transfer unit side drives one of the vertical transfer clock pulses for driving the vertical transfer unit. The solid-state imaging device is driven by a clock pulse of the phase, and the other gate section on the side of the horizontal transfer section is driven by a clock pulse independent of the vertical transfer clock pulse. 2. The solid-state imaging device according to claim 1, wherein an electrode area of the one gate portion on the vertical transfer portion side is larger than an area of each transfer electrode of the vertical transfer portion. 3. The solid-state image pickup device according to claim 1, wherein shunt wirings are formed on the vertical transfer portion and the gate portion, respectively. 4. The solid-state image pickup device according to claim 2, having a CCD solid-state image pickup device structure of an interline transfer system. 5. A shunt wiring is formed on each of the vertical transfer unit and the gate unit, transfer electrodes are formed of an electrode material having a three-layer structure, and transfer electrodes of the horizontal transfer unit are second and third layers. The solid-state imaging device according to claim 4, wherein the solid-state imaging device is formed of an eye electrode material, and the buffer layer below the shunt wiring is formed of a third layer electrode material.