JPH04343074A - Power analyzer apparatus - Google Patents

Abstract

PURPOSE:To enable measurement of a harmonic power by computing a power of each degree from a complex current and a complex voltage of the degree obtained by the fast Fourier transform of digital data for each one cycle of a voltage signal to be measured. CONSTITUTION:A plurality of voltage/current signals to be measured which are inputted are subjected to A/D conversion on the basis of a measured frequency of a frequency measuring element 35, under the control of a CPU 38, and stored in memories 25 to 30. In order to calculate harmonics of the second to 49th orders correctly, on the occasion, one cycle of a measuring signal is divided in 512 and data at each point are taken in without fail. The analog signal of one selected signal to be measured is inputted to a PLL element 34 and synchronized with a digital signal of a prescribed frequency corresponding to the selected signal. Based on complex currents and complex voltages from the 0th to 49th orders obtained by taking the current/voltage data in a digital signal processor(DSP) 40 from the memories 25 and 26, for instance, and by subjecting them to fast Fourier transform, the power of each order is calculated in this way.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power analyzer device, and more particularly, to a power analyzer device capable of measuring harmonic power of each order.

0002

[Background Art] In recent years, as semiconductor power conversion devices (for example, inverter devices) have been used in many devices, more measurement data can be processed easily and quickly, and the power used to measure the power system. A meter has been proposed. An example of such a power meter is one having the configuration shown in FIG. 7, for example.

In the figure, a voltage/current input analog circuit 1 includes signals to be measured (voltages to be measured (V1, V2, V3), currents (A1, A2, A3)) for 3 channels (channels).
Input, detect the measured voltage and current of those 3 channels,
Then, the voltage and current are subjected to analog calculation to calculate the power, and analog signals of the voltage, current and power are output.

The analog signal from the voltage/current analog circuit 1 is switched by the multiplexer 2, and the switched analog signal is converted into digital data by the A/D converter 3 and written to the RAM/ROM (memory) 4. According to the written program, the CPU 5 will carry out the process of importing the data.

The memory 4 is connected to the bus line 6 of the CPU 5.
, an I/O port 7, a display section 8, a keyboard 9, etc., are connected to the CPU 5. The CPU 5 switches the multiplexer 2 via the I/O port 7, writes the digital data to the memory 4, and executes the process based on the digital data. calculates power, apparent power, reactive power, power factor, etc., displays and processes these calculation results, and multiplies the measured value by a time coefficient based on the imported data and the calculated data, and integrates it to obtain the integrated amount. Calculate and display the integrated amount.

[0006] The display section 8 displays the voltage, current, power, apparent power, reactive power, power factor, etc. of the signal to be measured according to display processing by the CPU 5.

[0007] In the wattmeter configured as described above, since the voltage/current input analog circuit 1 adopts the AC zero flux method operation principle and also uses PT and clamp CT, it can operate at a wide frequency range from 10 Hz to 20 kHz. It maintains good characteristics over a wide range, making it possible to accurately measure voltage, current, power, etc.

[0008]

[Problems to be Solved by the Invention] By the way, when driving a motor with a pulsed voltage waveform in the semiconductor power device described above, such as an inverter device, the current includes harmonic components. is causing noise and disturbance. Equipment failures caused by harmonics are seen as a problem, and especially in the case of home appliances, noise and disturbances caused by harmonic components become a problem. It is now necessary to measure wave components.

However, in the above-mentioned wattmeter, the voltage and
Although it is possible to measure current and power, it has not been possible to directly measure their harmonic components.

Therefore, when measuring the power system of a semiconductor power device, it is only necessary to prepare two measuring devices: a wattmeter and an expensive harmonic analyzer (for example, an FFT analyzer) that measures its harmonic components. Moreover, the operation of the FFT analyzer is complicated and the measurement of harmonic components is troublesome, so there is a demand for an apparatus that can measure not only power but also harmonic components.

[0011]

[Means for Solving the Problems] The present invention has been made in view of the above-mentioned conventional circumstances, and its structural features include converting the voltage to be measured and the current to be measured into digital data using sampling signals of a predetermined frequency. at least two A/D converters each obtaining one cycle of digital data;
A conversion synchronization control section including a PLL circuit that synchronizes each sampling signal of the A/D conversion section, and a conversion synchronization control section that performs fast Fourier transform on each digital data converted by the A/D conversion section to generate a complex current and a complex voltage of a predetermined order. and a power calculation section that calculates the power of each order from the complex current and complex voltage of each order.

0012

[Operation] According to the above structure, the active power and the reactive power of the power can be obtained for each harmonic order with the frequency as the axis.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the overall configuration of a power analyzer device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3.

The power analyzer device according to this embodiment has three channels (voltages to be measured V1 to V3 and currents to be measured A1 to A3) input units 10 to 12 and a predetermined cutoff frequency that allows the fundamental wave and harmonics contained in the analog signals of the signals under test to pass through these input units 10 to 12 to be varied, and to prevent aliasing distortion. filter sections 13 to 18, A/D conversion sections 19 to 24 that digitally convert analog signals passed through these filter sections 13 to 18 using sampling signals of predetermined frequencies, and these A/D conversion sections 19 to 18.
A memory 25 that stores the digital data converted in step 24.
30, a first switching section 31 that selects one of the analog signals passed through the input units 10 to 12, and a waveform shaping of the analog signal switched by the first switching section 31 to form a rectangular shape. a filter waveform shaping section 32 that converts the signal into a wave signal;
A signal for variably controlling the cutoff frequency of the filter sections 13 to 18, a sampling signal of a predetermined frequency of the A/D conversion sections 19 to 24, and a write signal of the memories 25 to 30 are output, and the sampling signal is input to the signal under test. For example, the frequency is set to 5 times the frequency of the input signal under test.
The storage control unit 33 which multiplies the frequency by 12 times and the rectangular wave signal from the filter waveform shaping unit 32 are used as sources, and the rectangular wave signal and the sampling frequency of the A/D converters 19 to 24 are multiplied by an integer (for example, 512). Detects the phase difference with the signal set to 1, varies the voltage of the internal VCO according to this phase difference, outputs a signal with a predetermined frequency to the storage control unit 33, and performs sampling in the A/D conversion units 19 to 24. Synchronize the signal with the analog signal switched by the switching unit 31,
and PLL (Phase Locked Loop) for stabilizing the frequency of the sampling signal.
34.

This power analyzer device also includes a frequency measurement section 35 that measures the frequency of the input signal under test using the rectangular wave signal obtained by the filter waveform shaping section 32, and an oscillation section that outputs a fixed predetermined frequency signal. 36, and a second switch which switches the frequency signal from the oscillation section 36 and the frequency signal from the PLL section 34 and outputs it to the storage control section 33.
A switching section 37 is provided.

Therefore, by switching the second switching section 37, two types of A/D conversion sampling mode, that is, storage mode, PLL synchronization method and fixed synchronization method are possible.

Furthermore, in this power analyzer device, based on the digital data taken into the memories 25 to 30, the fundamental wave and harmonics of a predetermined order contained in the input signal under test are subjected to FFT (fast Fourier transform). ) to obtain the power for each order.

Therefore, as shown in FIG. 2, this power analyzer device is equipped with a CPU 38 as a central processing unit that controls the entire device, and the memories 25 to 30 and a storage control unit are connected to the bus line 39 of the CPU 38. 3
3. PLL section 34, frequency measurement section 35 and oscillation section 36
In addition, the digital data written in the memory units 25 to 30 is subjected to fast Fourier transform (FFT) to extract the fundamental wave and harmonics of a predetermined order (for example, up to the 49th order) contained in the input signal under test. A digital signal processor (DPS) 40 that performs high-speed calculations, and an E that stores control programs for the device and its calculation programs.
A PROM section 41 and a RAM section (SRAM, DRAM) 4 that stores data (numeric data) such as the results of these calculations.
2, a direct memory access (DMA) controller section 43 that controls writing and reading of this RAM section 42, and a VRAM (video RAM) section 44 that can write and read numerical data and waveform data based on the above calculation results. , a parallel interface 47 for connecting a CRT controller section 45 that writes, reads, and controls the display of data in this VRAM section 44, a printer section 46 that prints out numerical values and waveforms, and data such as those numerical values and waveforms. a floppy disk controller (FDC) 49 that controls a floppy disk drive section 48 that stores data on a floppy disk, etc., and a GP-IB that outputs data such as numerical values and waveforms to the outside and inputs data from other devices. Interface 5
0 and an asynchronous communications interface 51 are connected.

Furthermore, this power analyzer device includes a display section (for example, a liquid crystal display device) that displays the numerical values or waveforms processed by the CRT controller section 45.
52 and an operation panel 53 having measurement operation switches for the device, and signals corresponding to the operations are input to the CPU 38 via the bus line 39.

FIG. 3 schematically shows the circuit configuration of the digital signal processor 40. That is,
The processor 40 includes two FFT calculation circuits 401a and 4
01b, and a power calculation unit 402 that calculates the power of each order from the complex signals obtained from the FFT calculation circuits 401a and 401b.

Note that in this example, the power calculation section 4
Integration circuits 403a and 403b are connected in parallel to each output line of 02.

In this case, as illustrated in FIG.
Power calculation circuits 4021 to 40249 for the 49th order are provided. Although power calculation circuits are assigned to each order here for convenience of explanation, in reality, the number can be reduced by processing complex data of each order in a time-sharing manner.

Each of the power calculation circuits 4021 to 40249 has the same configuration, and FIG. 5 shows the internal circuit of the power calculation circuit 4021. That is, the same power calculation circuit 4021
is a multiplication circuit 402 that multiplies complex current and complex voltage.
b, but a conjugation circuit 402a is interposed on the input side of one of them. In this example, it is placed on the complex current side. Further, on the output side of the multiplication circuit 402b, a real part extraction circuit 402c and an imaginary part extraction circuit 40 are provided.
2d are connected in parallel.

Next, the operation of this power analyzer device will be explained. In this embodiment, the three-channel input units 10 to 13 each have two input sections 10a and 10.
b, 11a, 11b, 12a, 12b, and by applying the voltage and current of the signal to be measured to the same input part,
Single-phase to three-phase power measurement is possible.

When a plurality of signals to be measured are input to each of the input units 10 to 13 and, for example, a power measurement operation of an inverter device is performed, the CPU 38 performs the control necessary for the power measurement, and performs, for example, frequency measurement. Sampling of A/D conversion based on the measurement frequency of section 35, memory 2
5 writing etc. are controlled.

That is, the storage control unit 33
The sampling signals of the D converters 19 to 24 are output, and the write signals of the memories 25 to 30 are output, while the input signals under measurement are level-converted to levels that can be input to the A/D converters 19 to 24, respectively. .

As a result, the analog signals passed through the filters 13-18 are converted into digital data by the A/D converters 19-24, and stored in the memories 25-30. At this time, since the A/D converters 19 to 24 operate simultaneously, the respective digitally converted digital data are stored in the memories 25 to 30 at the same time.

Furthermore, when the storage mode is not the fixed synchronization method but the PLL synchronization method, the second switching unit 3
7 is switched to the PLL section 34 side, the signal 1 selected by the first switching section 31 among the input signals under measurement
Analog signals of the two input signals to be measured (voltages to be measured V1 to V3 or currents to be measured A1 to A3) are used as sources of the PLL section 34.

That is, this analog signal is waveform-shaped into a rectangular wave signal by the filter waveform shaping section 32, and this rectangular wave signal is input to the PLL section 34, so that the PLL
In the section 34, the sampling signals of the predetermined frequencies of the A/D converters 19 to 24 and the selected signal under test are synchronized. In this case, synchronization is applied for at least several cycles of the selected signal under test, and each zero-crossing point of the input signal under test is used as the starting point of A/D conversion, and one cycle of the input signal under test is accurately captured. Can be done.

Here, in order to accurately calculate the 2nd to 49th harmonics among the harmonics contained in the signal under test by FFT calculation, in this embodiment, one cycle of the input signal under test is used. is divided into 512 parts to obtain data for each point. In this case, by the above PLL synchronization method,
Since that one cycle can be accurately captured, 512
It is possible to reliably import point digital data.

In this way, each memory 25 to 30 has 5
Twelve points of digital data are written, and harmonic analysis by FFT is performed based on this data.

That is, a memory corresponding to each channel,
For example, current data a(t) and voltage data v(t) from the memories 25 and 26 are transferred to the digital signal processor 40.
The data is taken in by FFT calculation circuits 401a and 401b and subjected to fast Fourier transform.

As a result, the FFT calculation circuit 401a outputs a complex current An (n=0, . . . , 4) from the 0th order to the 49th order.
9), the FFT calculation circuit 401b outputs the 0th to 49th order complex voltages Vn (n=0,...,49), and the complex current An and the complex voltage Vn are sent to the power calculation unit 402. is input.

In the power calculating section 402, as shown in FIG. 4, power calculation is performed for each order. Here, the complex current An is expressed as (Ar+jAi), and the complex voltage Vn is expressed as (Vr+jVi). As shown in FIG. 5, in this example, after the complex current An is conjugated in the conjugation circuit 402a and becomes (Ar-jAi),
A multiplication circuit 402b performs multiplication by a complex voltage Vn (Vr+jVi).

As a result, a real part of (VrAr+ViAi) and an imaginary part of (ViAr-VrAi) are obtained, and the real part extraction circuit 402c extracts the effective power Wn of that order.
is output, and the reactive power varn of the same order is output from the imaginary part extraction circuit 402d.

In this way, the power calculation unit 402 calculates the active power Wn and reactive power varn of each order (n is both 0
,...,49) are output, and each integration circuit 403
The integrated values ΣWn and Σvarn are obtained from a and 403b.

In FIG. 6, the voltage and current components of the fundamental wave and harmonics from the 2nd to the 49th order contained in the input measured signal (V1, A1) of channel 1 are displayed on the display section 52. The active power Wn and reactive power varn of each order are also displayed on the display unit 52 in the same way.

Note that in FIG. 6, "1" in the "k" column displays the voltage and current of the fundamental wave (primary) due to the input signal under test of channel 1, and "2" to "49" indicate its voltage and current. The voltage and current of the 2nd to 49th harmonics included in the signal under measurement are displayed. Further, for example, when the first switching section 31 is switched to the input section 10a side, the screen of the display section 52 displays "PLL" ( V1)” is displayed (indicated by arrow A in the figure).

Here, the signal under test (voltage under test (V
1) If the distortion in (1)) is too large or its level is too low, a normal rectangular wave signal cannot be obtained when the filter waveform shaping section 32 shapes the analog signal of the input signal under test of channel 1. A situation arises. In such a case, the switching section 31 is
, and select another line to be measured.

[0040]

As explained above, according to the present invention, each A/D converter is synchronously controlled to obtain one cycle of digital data, and the same data is subjected to FFT operation.
By obtaining the active power and reactive power of each order from its complex voltage and complex current, this power analyzer is particularly suitable for measuring harmonics, such as measuring the power system of semiconductor power equipment. Equipment is provided.

[Brief explanation of the drawing]

FIG. 1 is a schematic partial block diagram of a power analyzer device according to an embodiment of the present invention.

FIG. 2 is a schematic partial block diagram of a power analyzer device according to an embodiment of the present invention.

FIG. 3 is a schematic block diagram of the digital signal processor shown in FIG. 2;

FIG. 4 is a schematic block diagram of the power calculation unit shown in FIG. 3.

FIG. 5 is a schematic block diagram of the power calculation circuit shown in FIG. 4.

FIG. 6 is a display screen diagram showing measurement data on the display section of this power analyzer device.

FIG. 7 is a schematic block diagram of a conventional power meter.

[Explanation of symbols]

10-12 Input units 19-24 A/D conversion sections 25-30 Memory 31 Switching section 32 Filter waveform shaping section 33 Storage control section 34 PLL section 35 Frequency measurement section 38 CPU 40 Digital signal processor 401 FF
T calculation circuit 402 Power calculation section 403 Integration circuit

Claims (1)

[Claims] Claims: 1. At least two A converters for converting a voltage to be measured and a current to be measured into digital data using a sampling signal of a predetermined frequency and obtaining digital data for one cycle each.
A/D conversion section, a conversion synchronization control section including a PLL circuit that synchronizes each sampling signal of the A/D conversion section, and the above A/D conversion section.
F to obtain complex current and complex voltage of a predetermined order by performing fast Fourier transform on each digital data converted by the /D conversion section.
A power analyzer device comprising: an FT calculation unit; and a power calculation unit that calculates the power of each order from a complex current and a complex voltage of each order.