JP3142339B2 - Power analyzer phase angle correction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention not only measures power using a plurality of input signals under measurement but also analyzes fundamental and harmonic components contained in the signals under measurement.
The present invention relates to a power analyzer capable of measuring and displaying its fundamental wave and harmonics, and more specifically, to a PLL (Ph).
each Lookup Loop)
The present invention relates to a phase angle correction method for a power analyzer that synchronizes a sampling signal of a / D converter to accurately capture digital data of one cycle (period) of each input signal under measurement.

[0002]

2. Description of the Related Art For example, in order to monitor a power system of a semiconductor power conversion device (eg, an inverter device), it is necessary to analyze not only the voltage, current, and power but also a frequency spectrum including harmonics. As a wattmeter used for this purpose, there is, for example, one having a configuration shown in FIG.

In FIG. 1, a voltage / current input analog circuit 1 has input terminals for, for example, 3 channels (channels), and a signal to be measured (voltages to be measured (V1, V
2, V3) and the currents (A1, A2, A3)), these signals are subjected to predetermined arithmetic processing to output analog signals of voltage, current and power.

The analog signal is sequentially supplied to the A / D converter 3 by switching of the multiplexer 2,
After being converted into digital data, it is written into a RAM / ROM (memory) 4.

A CPU (Central Processing Unit) 5 controls writing and reading to and from the memory 4 via a bus line 6. In addition, an I / O port is connected to the bus line 6 of the CPU 5. 7, a display unit 8, a keyboard 9, and the like are connected, and the CPU 5 switches the multiplexer 2 through the I / O port 7 as appropriate.

The CPU 5 calculates power, apparent power, reactive power, power factor, and the like based on the digital data written in the memory 4, displays the results of the calculations, displays the acquired data and the calculated data. , The measured value is multiplied by a time coefficient, added and integrated, the integrated amount is also calculated, and the integrated amount is displayed.

The display unit 8 displays the measurement result of the signal under measurement, the voltage, the current, the power, the apparent power, the reactive power, the power factor, and the like in accordance with the display processing of the CPU 5.

In this conventional example, since the voltage / current input analog circuit 1 employs the operation principle by the AC zero flux method and employs the PT and the clamp CT, a wide frequency range of 10 Hz to 20 kHz is adopted. To ensure good characteristics, accurate voltage, current,
Measurement of electric power etc. is possible.

[0009]

When a motor is driven with a pulse-like voltage waveform as in a semiconductor power device, for example, an inverter device, the current contains a harmonic component, and the harmonic component is It causes noise and vibration.

[0010] Such a failure of equipment due to harmonics is regarded as a problem, and in particular, in the case of home electric appliances and the like, noise and vibration due to the harmonic components become a problem. It is necessary to measure the harmonic components.

However, in the conventional wattmeter, the voltage,
Although current and power can be measured, their harmonic components cannot be directly measured.

Therefore, when measuring the power system of a semiconductor power device, it is necessary to prepare two measuring devices: a power meter and an expensive harmonic analyzer (for example, an FFT analyzer) for measuring its harmonic components. In addition, the operation of the FFT analyzer is complicated and the measurement of harmonic components is troublesome. Therefore, there is a demand for an apparatus that can measure not only power but also harmonic components.

In a harmonic analyzer such as the FFT analyzer, an analog signal of an input signal to be measured is A / D converted, and when the converted digital data is taken in, a synchronization of the A / D conversion sampling signal is performed. Although the PLL synchronization method is adopted as the matching, when there are a plurality of input channels, the PLL synchronization source signal is fixed to the input measurement signal of a specific channel (for example, 1ch).

Also, when correcting the phase angle, PL
As in the case of L-synchronization, phase angle correction is always performed with reference to the fundamental wave of the specific channel.

As described above, whether the PLL is synchronized or the phase angle is corrected, the fact that the reference channel is fixed means that the software configuration is simple. Although it can be evaluated in that the phase relationship with the harmonics is easy to understand, there is another problem as follows.

That is, if the waveform of the signal under measurement of the reference channel is distorted or its level is low, data cannot be reliably taken in, and the measurement accuracy deteriorates. Also, the reference for phase angle correction becomes unstable.

To prevent this, another channel may be used as the reference channel, but the connection must be reconnected each time, which is not a practical solution.

[0018]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional circumstances, and has a structural feature that converts input measured signals of at least a plurality of channels into analog signals of levels that can be input. A plurality of input processing units, a plurality of A / D conversion units for converting their analog signals into digital data by sampling signals of a predetermined frequency, and at least one cycle of digital data converted by the A / D conversion units And a storage controller for outputting a sampling signal to the A / D converter and a data write timing signal to the storage, and outputting the sampling signal in synchronization with the input signal under measurement. A switching unit for selecting one of the input signals under measurement output from the plurality of input processing units; A waveform shaping unit for shaping the input signal under measurement selected by the switching unit into a rectangular wave signal; and using the rectangular wave signal as a source, the rectangular wave signal and the sampling frequency of the A / D converter are divided by an integer. A phase difference from the signal set to 1 is detected, the frequency of the control signal output to the storage control unit is varied according to the difference, and the sampling signal of the A / D conversion unit is selected by the switching unit. A PLL section for synchronizing with one of the input signals under test, and determining whether or not the input signal under test selected as the source of the PLL section is optimal; Source automatic switching control means for switching to an input processing unit to which the most suitable input signal under measurement is input from among the input signal under measurement of the channel; and voltage, current, and power based on data stored in the storage unit. A signal processing unit for calculating the respective harmonic components of the input signal under test and performing an FFT operation on the harmonic signal of the input signal under test. The purpose of the present invention is to correct a phase angle with reference to a fundamental wave of a measurement signal.

[0019]

The signal to be measured as the optimum input signal as a reference for PLL synchronization and phase angle correction is determined by its frequency stability and input level.

That is, when, for example, the level of the input signal under measurement selected as the source of the PLL section becomes low,
The switching unit is automatically switched, and an optimum input signal under measurement is input from the input signal under measurement of each channel.
It is selected as the source of the L section.

In this way, the optimum input signal under measurement as the source of the PLL unit, that is, the input signal under measurement having a good S / N ratio is automatically selected by the switching unit. The sampling synchronization of each A / D conversion can be adjusted to the optimum input signal under measurement without performing the above operation.

The phase angle is corrected based on the optimum fundamental wave of the input signal under test.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As exemplified in FIG. 1, this power analyzer converts a plurality of input signals under test (voltages and currents under test) to predetermined levels required for subsequent signal processing. Input units 10 to 12 for measuring voltages (V1 to V3) and currents (A1 to A3)
A variable cut-off frequency anti-aliasing filter section 13 to 18 for passing a fundamental wave and a harmonic of a predetermined order contained in the analog signal under measurement supplied through these input units 10 to 12; A / D converters 19 to 24 for converting analog signals passed through these filter units 13 to 18 into digital data with sampling signals of a predetermined frequency, respectively, and store the digital data converted by these A / D converters 19 to 24. Memories (storage units) 25 to 30, a first switching unit (for example, an analog switch or a relay) 31 for automatically switching an analog signal to be measured via the input units 10 to 12, and a first switching unit Filter shaping of the analog signal under measurement switched by the section 31 into a rectangular wave signal And outputs a signal for variably controlling the cutoff frequency of the filter units 13 to 18, a sampling signal of the A / D conversion units 19 to 24, and a write signal of the memories 25 to 30, and inputs at least the sampling signal. A storage control unit 33 for outputting in synchronization with a signal under measurement;
2, a phase difference between the rectangular wave signal and the sampling signals of the A / D converters 19 to 24 is detected, and a voltage control oscillator (VCO) (not shown) is used in accordance with the phase difference. The voltage is varied and a signal of a predetermined frequency is output to the storage control unit 33, and the A / D conversion unit 1
The sampling frequency of 9 to 24 is set to an integer (for example, 51
2) A PLL (Phase Locked Loop) unit 34 for synchronizing the reduced signal with the input signal under measurement and stabilizing the frequency of the sampling signal.
And

The power analyzer also includes a frequency measuring section 35 for measuring the frequency of the input signal under measurement using the rectangular wave signal obtained by the filter waveform shaping section 32, and an oscillating section 36 for outputting a fixed predetermined frequency signal. And the oscillation section 36
And a second switching section 37 for switching between the frequency signal from the PLL section 34 and the frequency signal from the PLL section 34 and outputting the frequency signal to the storage control section 33.

That is, by switching of the second switching unit 37, the sampling mode of A / D conversion, that is, the storage mode, can be selected from two types of a PLL synchronous system and a fixed synchronous system.

Further, the power analyzer not only calculates the voltage, current, power, etc. of the input signal under measurement based on the digital data fetched into the memories 25 to 30, but also calculates the voltage, current, power, etc. of the input signal under measurement. The fundamental wave and a harmonic of a predetermined order are calculated by FFT (Fast Fourier Transform) calculation.

For this reason, as shown in FIG. 2, this power analyzer has a CPU 3 serving as a central processing unit for controlling the whole according to a panel operation of the apparatus.
8 is provided.

A bus line 39 of the CPU 38 includes the memories 25 to 30, the storage control unit 33, and the PLL
In addition to the unit 34, the frequency measuring unit 35, and the oscillating unit 36, the voltage, current, power, and the like of the effective value level are calculated at high speed based on the digital data written in the memory units 25 to 30. A DSP (digital signal processor) 40 for calculating a fundamental wave and a harmonic of a predetermined order (for example, up to the 49th order) included in the input signal under measurement, a control program of the device, and a calculation program thereof are stored. EPROM unit 4
1, a RAM (SRAM, DRAM) 42 for storing data such as calculation results, a DMA (Direct Memory Access) controller 43 for controlling writing and reading of the RAM 42, and numerical data based on the calculation results. And a VRAM (video ram) unit 44 capable of writing and reading waveform data,
A CRT controller unit 45 for writing, reading and displaying data in the M unit 44; a parallel interface adapter 47 for connecting a printer unit 46 for printing out numerical values and waveforms thereof; FDC for controlling the floppy disk drive unit 48 for storing the data of the floppy disk in a floppy or the like
(Floppy disk controller) 49 and a GP-IB interface 5 for outputting data such as numerical values and waveforms to the outside and inputting data from other devices.
0 and the asynchronous communications interface 51 are connected.

The power analyzer further includes a display unit (for example, a liquid crystal display) 52 for displaying a numerical value or a waveform processed by the CRT controller unit 45.
And a panel (not shown) provided with operation switches and the like of the apparatus. A signal corresponding to the operation of the panel is transmitted to the CPU 3 via an interface and a bus line 39.
8 is input.

Next, the operation of the power analyzer will be described with reference to the flowchart of FIG. 3 and the screen display state diagram of FIG. When a plurality of signals to be measured are respectively input to the input units 10 to 12 and a power measurement operation is performed, the CPU 38 controls necessary for the power measurement, and the first switching unit 31 controls the panel operation. (The automatic mode operation), and the PLL section 34 is switched.
, One input signal under measurement is selected from the channels (step ST1).

Subsequently, A / D conversion sampling and memory write control are performed based on the measured frequency of the frequency measuring unit 35. That is, the storage control unit 33 outputs the sampling signals of the A / D conversion units 19 to 24, and outputs the write control signals of the memories 25 to 30.

As a result, the analog signals passed through the filters 13 to 18 are converted into digital data by the A / D converters 19 to 24 and stored in the memories 25 to 30 (step ST2).

At this time, the storage mode is not the fixed synchronous system, and the second switching unit 37 is switched to the PLL unit 34 side to adopt the PLL synchronous system. 24 operate at the same time, and digital data converted into digital data are stored in the memories 25 to 30 at the same time.

That is, of the input signals to be measured, one signal to be measured (the voltage to be measured (V1, V2, V3) or the current (A1, A2,
A3)) is used as the source of the PLL unit 34, the measured signal is shaped into a rectangular wave signal by the filter waveform shaping unit 32, and the rectangular wave signal is input to the PLL unit 34. Synchronizes the sampling signal of the predetermined frequency of the A / D converters 19 to 24 with the selected signal under measurement.

In this case, the synchronization is performed at least for several cycles of the selected signal under test, and the zero cross point of the input signal under test is used as the start point of A / D conversion, and one cycle of each input signal under test is defined as one cycle. Can be captured accurately.

In this embodiment, in order to accurately calculate the 2nd to 49th harmonics among the harmonics contained in the signal under measurement by the FFT operation, one of the input signals under measurement is calculated. The cycle is divided into 512, and the
I try to get point data.

Subsequently, based on the data stored in each of the memories 25 to 30, that is, the taken-in 512-point digital data, the voltage and current (effective value (level)) are set for each signal to be measured of each channel. ), Power (active power, apparent power, reactive power) and power factor are calculated, and a fundamental wave and a predetermined order (fundamental wave and current) included in the signal under measurement (voltage under measurement and current) of each channel by FFT operation are calculated. (For example, up to the 49th order) is calculated in real time (step ST3).

Thereafter, the fundamental wave of the signal under test currently selected as the source of the PLL section 34 is set to 0 °, and the phase angle of the signal under test of each channel is corrected (step ST4). Note that the phase angle correction formula is based on the same method as that of the related art, and a description thereof will be omitted.

As shown in FIG. 4, the display unit 52 displays the fundamental wave of the signal under measurement and the calculated values of the second to 49th harmonics in real time (step ST5). ).

In FIG. 4, the calculated value (voltage, current) of the fundamental wave (primary) based on the input signal under measurement of channel 1 is displayed at "1" in the "k" column, and "2" to "49". "
Are the 2nd to 49th included in the signal under measurement.
The calculated value of the next harmonic is displayed. It should be noted that, for convenience of explanation, FIG.
Although the display examples of the fundamental wave and the second to 49th harmonics included in 1) are shown, the display screen can be switched for each channel by, for example, panel operation. Needless to say.

Further, for example, the first switching unit 31
In the case of switching to the 0a side, "PLL (V1)" indicating the input section of the signal under measurement, which is the source of the PLL section 34, is displayed on the screen of the display section 52 (arrow A in the figure). Shown).

Here, the measured signal (measured voltage (V
If the input level of 1)) is too low, a normal rectangular wave signal cannot be obtained when the filter waveform shaping section 32 shapes the waveform of the analog signal of the input signal under measurement of the channel 1. Is out of the normal range, that is, a synchronization shift occurs, and one cycle of the input signal under measurement is
There is a possibility that the image is not divided into two.

If the apparatus has been switched to the auto mode in which the source of the PLL is automatically selected, the process proceeds from step ST6 to step ST7, where the measured signal selected by the first switching section 31 is selected. Voltage (V1) is PLL
It is determined whether or not the level is the optimum level as the source of the unit 34 (step ST7).

In making this determination, for example, P
The output frequency of the LL unit 34 is measured, and the level of the input analog signal of the filter waveform shaping unit 32 at the preceding stage of the PLL unit 34 is set to a predetermined reference value based on whether or not the measurement result is stable. Is provided to the CPU 38 via the I / O port and the bus line 39, and the level of the analog signal is monitored. That is, the input signal under measurement as the source of the PLL unit 34 is monitored. It may be determined whether or not is optimal.

For example, when the level of the selected input signal under measurement is not constant, its S / N ratio is poor, so that it is determined that the input signal under measurement is not optimal as the source of the PLL section 34, and In step ST8, it is determined whether there is an optimum input signal under measurement as the source of the PLL unit 34.

That is, the first switching section 31 is sequentially switched, and the CPU 38 selects an input signal under measurement whose frequency or voltage (current) level is stable. When all the input signals under measurement of each channel are below the appropriate level, the first switching unit 31 is left as it is, that is, without switching the input signal under measurement as a source of the PLL unit 34, for a certain period of time. The waiting process is executed (step ST9), and after a predetermined time, the above-mentioned step ST9 is performed.
Steps 2 to ST8 are repeated again.

In step ST8, the PLL unit 3
If it is determined that there is an input signal to be measured at the optimum level as the source of No. 4, the process proceeds to step ST10, where a switching signal for driving the first switching unit 31 is output via the bus line 39, and the first switching unit is output. 31 is switched to the input signal under measurement having the optimum level.

As a result, the source display "PLL (V1)" shown by the arrow A in FIG. 4 is replaced by the switched input section of the input signal under measurement (step ST11), and thereafter, the process returns to step ST2, and returns to step ST2. The operation is repeated.

That is, 512 new digital data are taken in for the input measured signal of each channel, and based on the data, the voltage, current (including the effective value (level)), The power (active power, apparent power, reactive power) and power factor are calculated, and the fundamental wave and the predetermined order (for example, the 49th order) included in the signal under measurement (voltage under measurement, current) of each channel by the FFT operation are calculated. ) Are calculated in real time.

The fundamental wave of the signal to be measured newly selected as the source of the PLL unit 34 is set to 0 °, and the phase angle of the signal to be measured of each channel is corrected, and the result is displayed on the display unit 52. Is displayed. In this case, P
As the optimal source of LL, for example, the voltage V of the second channel
Assuming that 2 is selected, in the display example of FIG.
PLL (V2) is displayed as the source.

During this repetitive operation, when it is determined that the selected input signal under measurement is not optimal as the source of the PLL section 34, for example, the LED element emits light,
Alternatively, a buzzer may be sounded to notify the operator of the apparatus.

As described above, the voltage,
In calculating the current, power, and the fundamental and harmonics of the input signal under measurement,
Since the input signal under test at the optimum level is automatically selected as the source of the PLL section 34, the sampling synchronization of the A / D conversion can be surely synchronized, and one cycle of each input signal under test is determined by a predetermined period. Number (eg 5
12), the digital data can be reliably taken in at the predetermined number of points.

When correcting the phase angle, PL
By using the fundamental wave of the input signal under measurement at the optimum level as the source of the L section 34, highly reliable phase angle correction can be performed.

When the manual mode is selected instead of the auto mode by the panel operation, the first switching section 31 is manually switched so that a desired input signal to be measured is supplied to the source of the PLL section 34. It can be. In this sense, the phase relationship between the channels can be observed by changing the reference of the phase angle correction without changing the connection of each channel.

[0055]

As described above, according to the present invention, the phase angle is corrected with reference to the fundamental wave of the input signal to be measured which is always selected as the source of the A / D converter. Highly reliable measurement data can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic partial block diagram of a power analyzer showing one embodiment of the present invention.

FIG. 2 is a schematic partial block diagram of a power analyzer showing one embodiment of the present invention.

FIG. 3 is a flowchart for explaining the operation of the power analyzer shown in FIGS. 1 and 2;

FIG. 4 is a schematic display screen view of the power analyzer shown in FIGS. 1 and 2;

FIG. 5 is a schematic block diagram of a conventional power meter.

[Explanation of symbols]

 10 to 12 input unit 19 to 24 A / D conversion unit 25 to 30 memory (storage unit) 31 first switching unit 32 filter shaping unit 33 storage control unit 34 PLL unit 35 frequency measurement unit 38 CPU (central processing control means) 40 DSP (Digital Signal Processor) 45 CRT Controller (Display Control Means) 52 Display Unit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-55-15067 (JP, A) JP-A-2-140479 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 21/00-22/04 G01R 11/00-11/66 G01R 23/165 G01R 23/167 H03L 7/06-7/22

Claims (1)

(57) [Claims] 1. A plurality of input processing units for converting at least a plurality of channels of input signals to be measured into analog signals having inputtable levels, and a plurality of input processors for converting those analog signals into digital data by sampling signals of a predetermined frequency. An A / D conversion unit, a storage unit for storing at least one cycle of digital data converted by the A / D conversion unit, a sampling signal for the A / D conversion unit, and a data write timing for the storage unit A storage control unit that outputs a signal and outputs the sampling signal in synchronization with the input measured signal, and a switch that selects one of the input measured signals output from the plurality of input processing units A waveform shaping section for shaping the input signal under test selected by the switching section into a rectangular wave signal; Wave signal as a source, 1 the sampling frequency of the square wave signal and the A / D converter of the integer fraction
Detect the phase difference with the signal and the frequency of the control signal output to the storage control unit according to the difference,
A PLL section for synchronizing the sampling signal of the A / D conversion section with one of the input measured signals selected by the switching section and an input measured signal selected as a source of the PLL section are optimal. Source automatic switching control means for switching the switching unit to an input processing unit to which an optimum input signal under measurement among the input signals under measurement of the plurality of channels is input when it is not optimal, A signal processing unit that calculates a voltage, a current, and a power based on data stored in the storage unit, and performs an FFT calculation on a harmonic component of the input signal under measurement. The above-mentioned PLL by automatic switching control means
A phase angle correction method for a power analyzer, wherein the phase angle is corrected based on a fundamental wave of an input signal under measurement selected as a source of the section.