JPH04342166A - Semiconductor device - Google Patents

Abstract

PURPOSE:To cut photoengraving process by flattening a surface of each element by cutting out a difference of height between a lowest element and other elements based on the lowest element of a plurality of elements. CONSTITUTION:A step is provided in advance by a height which is higher than a peripheral circuit part to a memory cell part of a substrate 1 and a memory cell is formed thereon including a capacitor whose size is larger than the peripheral circuit part. That is, A/l is formed all over the substrate 1 by sputtering method, etc., the peripheral circuit part and the memory cell part are patterned at once by one operation of photoengraving and each of first layers of Al wirings 23, 25 are formed. Thereafter, a layer insulating film 26 is formed and second layers of Al wirings 27, 28 of the peripheral circuit part and the memory cell part are formed simultaneously by a second photoengraving in the same way as the first layers of Al wiring layers 23, 25. Thereby, a photoengraving process can be cut.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention relates to semiconductor devices, especially DR
The present invention relates to reducing the level difference between an element part having a layered structure element such as a stacked capacitor such as an AM, and an element part of a semiconductor device having a planar element such as a simple transistor.

0002

[Prior Art] FIGS. 10 to 18 show a conventional semiconductor device (D
FIG. 2 is a manufacturing process diagram mainly showing a part of a memory cell section and a peripheral circuit section of a RAM. First, as shown in FIG. 10, approximately 30%
An oxide film 2 with a thickness of 0 angstroms is formed, and CV
A nitride film having a thickness of approximately 500 angstroms is formed using the D method or the like, and this is patterned using photolithography to remove the nitride film in the region that will become the P-channel transistor section.
Next, phosphorus ions were implanted at 100 keV and about 5×10 12 /cm 2 , and oxidation and driving were performed at 1130° C. for about 3 hours to form an N well 3 and an oxide film 4 of about 5000 angstroms. 80keV, 3×1012/cm as ion implantation resistant mask
A certain amount of boron is implanted into the memory cell portion and the N-channel transistor.

Next, a P-well 5 is formed by driving at 1100° C. for about 3 hours, the oxide films 2 and 4 on the surface of the substrate are etched away, and an oxide film of about 300 angstroms is formed by thermal oxidation or CVD. Furthermore, CV
After forming a nitride film of approximately 500 angstroms by the D method, patterning is performed by photolithography, and only the nitride film is etched away to form a nitride film pattern. c.
A device isolation oxide film 6 of about 5000 angstroms is formed by thermal oxidation using the nitride film pattern as an oxidation-resistant mask, and the nitride film used as a mask and the oxide film below it are etched by about 300 angstroms. (Figure 11).

Next, an oxide film 7 of approximately 170 angstroms is formed on the entire surface by thermal oxidation, a polysilicon 8 for a gate electrode is formed, patterning is performed by photolithography, the polysilicon 8 is etched, and then P is formed using a resist or the like.
Covering the channel transistor part, 1×1012/cm
A certain amount of phosphorus is ion-implanted to form an N- layer 9,
An oxide film 10 with a thickness of approximately 5000 angstroms is formed using a CVD method, etc., the P-channel transistor side is covered with a resist, etc., and anisotropic etching is performed, and arsenic of approximately 1×1015/cm 2 is ion-implanted using an ion implantation method to form a memory cell area and N. An N+ layer 11 is formed in the channel transistor section, the N channel transistor section and the memory cell section are covered with a resist, etc., boron ions are implanted at a density of about 1 x 1015/cm, a P+ layer 12 is formed, and a polyamide layer is formed on top of the N+ layer 11. Silicon 13 is formed and patterned (FIG. 12).

[0005] Thereafter, polysilicon 14 is further formed on the entire surface and patterned, and then an oxide film 15 is formed thereon by CVD or the like and patterned into a predetermined shape (FIG. 13).

Thereafter, a polysilicon pattern 16 that will become one electrode of the capacitor is formed in the memory cell portion, and
A polysilicon pattern 18 that will become the other electrode of the capacitor is formed through an oxide film 17 of about 0 angstroms, and an interlayer oxide film 19 is formed thereon by CVD or the like. A contact hole is formed in the portion (FIG. 14).

Further, each contact hole in the peripheral circuit section is filled with tungsten 20, while polysilicon 21 for wiring is formed in the memory cell section, and an interlayer oxide film 22 is formed on the entire surface.
After forming the contact hole, a contact hole is again formed in the interlayer oxide film 22 above the tungsten 20 in the peripheral circuit section, and the tungsten 20 is buried therein (FIG. 15).

Next, Al is formed on the entire surface of the substrate by sputtering or the like, and one part of the peripheral circuit is formed using a resist 24 by photolithography.
A layer of Al wiring 23 is formed (FIG. 16). Furthermore, the first layer of Al wiring 25 in the memory cell portion is photoengraved.
(Figure 17).

Thereafter, after removing the resist 24, an interlayer oxide film 26 is formed, and as with the first layer Al wirings 23 and 25, the second layer is photolithographically processed twice for the peripheral circuit area and the memory cell area. Al wirings 27 and 28 are formed (FIG. 18).

Next, the operation will be explained. In the memory cell section, the gate electrode 8 serves as a transfer gate,
The polysilicon pattern 16, oxide film 17, and polysilicon pattern 18 constitute a capacitor, and a high potential (usually 5 V) is applied to the transfer gate (gate electrode) 8. The transistor is turned on and the potential of the capacitor is read from the bit line (poly wiring 21).

[0011]

[Problem to be Solved by the Invention] The conventional semiconductor device is constructed as described above, and has a structure in which the capacitor of the memory cell is stacked on the transistor.
During the Al wiring process, the difference in level between the memory cell part and the peripheral circuit part (see Figure 18) is about 1 μm, which causes a focus shift during exposure, so the memory cell part and peripheral circuit part are photographed separately during wiring. Wiring must be done by plate making, and since there are two Al wiring layers in the example described above, there was a problem in that the photolithography process had to be performed four times.

The present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that can reduce the photolithography process.

[0013]

[Means for Solving the Problems] A semiconductor device according to the present invention includes a substrate region where a certain element is formed among a plurality of elements formed on the same substrate and having different heights. The element is formed by cutting out the difference between the height of the element and the height of the lowest element, with the element having the lowest height as a reference.

[0014]

[Operation] In this invention, the element with the lowest height is formed on the surface of the substrate, and the area of the substrate where other elements are formed is cut by the difference in height with respect to the element with the lowest height. I cut it out and installed other elements, so
The surface between each element becomes flat.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 9 are cross-sectional views showing a part of a memory cell section and a peripheral circuit section of a semiconductor device according to an embodiment of the present invention according to its manufacturing flow. In the figures, the same reference numerals as in FIGS. 10 to 18 indicate the same or corresponding parts. First, an oxide film of about 500 angstroms is formed on a P-type silicon substrate 1 by thermal oxidation or CVD method, and then CVD
A nitride film of approximately 1,000 angstroms is formed by a method such as a method, and the nitride film is patterned by photolithography to use the nitride film as an oxidation-resistant mask. After forming a thermal oxide film 29 of approximately 2 μm, the nitride film mask is removed by etching ( Figure 1).

Next, the thermal oxide film 29 is removed by etching to form a step d in the region of the substrate 1 that will become the memory cell portion, and an oxide film 2 of about 300 angstroms is formed by thermal oxidation or CVD, and on top of that a step d is formed. A nitride film with a thickness of approximately 500 angstroms was formed by CVD, etc., patterned by photolithography, and only the nitride film in the P-channel transistor area was etched away.
After ion-implanting approximately 5,000 angstroms of phosphorus, oxidation and driving were performed at 1,130°C for approximately 3 hours to form an N-well 3 of the P-channel transistor portion and an oxide film 4 of approximately 5,000 angstroms, and the oxide film 4 was made resistant to ion implantation. 8 as a mask
Boron of about 0 keV, 3 x 1012/cm2 is implanted into the memory cell part and the N-channel transistor part (Fig. 2
).

Next, driving was performed at 1100° C. for about 3 hours to form the P well 5 of the N channel transistor section.
The above oxide films 2 and 4 are removed by etching, and thermal oxidation or carbon
An oxide film of about 300 angstroms is formed by the VD method, and a nitride film of about 500 angstroms is formed on it by the CVD method, etc., and this is patterned and etched by photolithography to form a channel cut for element isolation. Boron was implanted at a rate of about 3 x 1013/cm2, and the nitride film pattern was used as an oxidation-resistant mask to thermally oxidize the
An oxide film 6 of 0 angstroms thick is formed, the nitride film used as a mask and the oxide film of about 300 angstroms are etched, and an oxide film 7 of about 170 angstroms is formed on the entire surface by thermal oxidation. Silicon is formed, and only the memory cell portion is patterned by photolithography using a resist 24 to form a gate polysilicon pattern 8 (FIG. 3). Furthermore, the peripheral circuit area is patterned using a resist 24 by photolithography, and the gate polysilicon pattern 3 of the peripheral circuit area is patterned.
0 (Figure 4).

Next, the P-channel transistor portion is covered with a resist or the like, phosphorus ions are implanted at a density of 1×10 12 /cm 2 to form an N − layer 9, and an oxide film 10 with a thickness of approximately 5000 angstroms is formed by CVD or the like. , cover the P-channel transistor side with a resist or the like, perform anisotropic etching, perform ion implantation of arsenic of about 1×1015/cm2 to form the N+ layer 11, and then cover the N-channel transistor part and the memory cell part. Covering with resist or the like, boron ions are implanted at a density of about 1×10 15 /cm to form a P+ layer 12, and polysilicon 13 is formed thereon and patterned (FIG. 5).

Thereafter, polysilicon 14 is further formed and patterned, and an oxide film 15 is formed thereon by CVD or the like and patterned (FIG. 6). after that,
A polysilicon pattern 16 that will become one electrode of the capacitor is formed in the memory cell portion, and a polysilicon pattern 18 that will become the other electrode of the capacitor is further formed with an oxide film 17 of about 100 angstroms interposed therebetween.
An interlayer oxide film 19 is formed by a VD method or the like, and contact holes are formed in predetermined portions of each element part by photolithography (FIG. 7).

Furthermore, while tungsten 20 is buried in the contact hole in the peripheral circuit section, polysilicon 21 for wiring is formed in the memory cell section, and after forming an interlayer oxide film 22 on the entire surface, the tungsten 20 above the tungsten 20 in the peripheral circuit section is formed. A contact hole is again formed in the interlayer oxide film 22, and tungsten 20 is filled in it (FIG. 8).

Next, Al is formed on the entire surface of the substrate by sputtering or the like, and the peripheral circuit part and the memory cell part are patterned at the same time by one photolithography process.
After forming 3 and 25, an interlayer oxide film 26 is formed, and the second layer of Al wiring 27 and 28 in the peripheral circuit area and memory cell area is formed by a second photolithography process, similar to the first Al wiring layer. formed at the same time (Fig. 9).

As described above, according to this embodiment, a step d is provided in advance in the memory cell portion of the substrate 1 by an amount higher than the height of the peripheral circuit portion, and a capacitor that is bulkier than the peripheral circuit portion is placed on top of the step d. Since we formed a memory cell containing
The upper surface between both elements becomes flat, and the first and second Al wiring layers can be formed in two photolithography processes in the wiring process after forming the element.

Since the operation is the same as that of the conventional example, a description thereof will be omitted here. In the above embodiment, a DRAM is used as an example of a semiconductor device, and the application is applied to a case where there is a step difference between a memory cell section and a peripheral circuit section.
A similar effect can be achieved if the semiconductor device has a part in which elements are formed three-dimensionally and a part in which elements are formed two-dimensionally (planarly), such as a semiconductor device such as a semiconductor device.

[0024]

[Effects of the Invention] As described above, according to the semiconductor device of the present invention, the element with the lowest height is formed on the surface of the substrate,
Since the substrate area where other elements are formed is cut out by the difference in height from the above-mentioned lowest element as a reference, and each other element is provided, the surface between each element is flat. This has the effect that the post-process wiring photolithography can be performed simultaneously for each element, simplifying the manufacturing process, and making it possible to reduce the size of the device.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a semiconductor device according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a semiconductor device according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a semiconductor device according to an embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing flow around a memory cell section and a peripheral circuit section of a conventional semiconductor device.

FIG. 11 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a conventional semiconductor device.

FIG. 12 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a conventional semiconductor device.

FIG. 13 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a conventional semiconductor device.

FIG. 14 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a conventional semiconductor device.

FIG. 15 is a cross-sectional view showing a manufacturing flow around a memory cell section and a peripheral circuit section of a conventional semiconductor device.

FIG. 16 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a conventional semiconductor device.

FIG. 17 is a cross-sectional view showing a manufacturing flow around a memory cell section and a peripheral circuit section of a conventional semiconductor device.

FIG. 18 is a cross-sectional view showing a manufacturing flow around a memory cell portion and a peripheral circuit portion of a conventional semiconductor device.

[Explanation of symbols]

1 P-type silicon substrate 2 Oxide film 3 N-well 4 Thermal oxide film 5 P-well 6 Element isolation oxide film 7 Gate oxide film 8 Gate polysilicon 9 N- Diffusion layer 10 Oxide film 11 N+ Diffusion layer 12 P+ Diffusion layer 13 Polysilicon 14 Polysilicon 15 Oxide film 16 Polysilicon 17 Oxide film 18 Polysilicon 19 Interlayer oxide film 20 Tungsten 21 Polysilicon 22 Interlayer oxide film 23 Al wiring (first layer, peripheral circuit part) 24 Resist 25 Al wiring (first layer, Memory cell part) 26 Interlayer oxide film 27 Al wiring (second layer, peripheral circuit part) 28 Al
Wiring (2nd layer, memory cell part) 29 Oxide film

Claims (1)

[Claims] 1. In a semiconductor device having a plurality of elements on the same substrate, each element having a different height from the substrate surface, a substrate region where a certain element of the plurality of elements is formed is defined by a region of the substrate where a certain element of the plurality of elements is formed. 1. A semiconductor device, characterized in that an element is formed by cutting out a difference between the height of the element and the height of the lowest element, with the element having the lowest height as a reference.