JPH04340881A - Digital video signal recording/reproducing device - Google Patents

Abstract

PURPOSE:To improve the picture quality of the reproduced picture of the digital VTR at the time of reproducing at a high speed. CONSTITUTION:The recording data is rearranged by a framming circuit 6 so that the picture of an area A1 at the center part of 1-frame picture may be recorded at the respective starting end of tracks V1, V2, V3,.... At the time of recording and normally reproducing, the recording/reproducing is performed by a rotary head H1. At the time of reproducing at a high speed, 4 rotary heads are used and the switching synthetic circuit outputs the reproduced signal of the area A1 around the starting end of the track of the reproduced signal of each head selectively. The four reproduced signals from each head are rearranged in a buffer memory and the divided display of them is performed on the 1-frame screen.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal recording/reproducing apparatus for recording/reproducing digital video signals on a magnetic tape using a rotary head.

0002

2. Description of the Related Art In a digital VTR for recording/reproducing digital video signals, as shown in FIG. A rotary head was scanning the magnetic tape as indicated by T0 across a plurality of tracks V1, V2, . . . , V8 formed on the magnetic tape. The example in FIG. 7 is an example of a playback operation in which the tape speed is eight times the normal speed. In the case of a digital VTR, since the amount of recorded/playback data is large, a multi-track configuration is sometimes adopted, but for the sake of simplicity in FIG. 7, each track records one frame of video data. It is assumed that

As mentioned above, eight tracks V1 to V8
The reproduced signal reproduced from each of the frames spans eight frame periods. By assembling these eight frames of data using digital image memory,
A reproduced image of one frame was formed. This high-speed playback method is basically the same as that used in analog VTRs.

0004

During high-speed playback, data contained in each of a plurality of frame periods related to the ratio of tape speeds during normal playback and high-speed playback is used to form one frame of screen. However, as this ratio increases, the data making up one frame of screen becomes less correlated, and the quality of the reproduced image during high-speed reproduction deteriorates. This tendency is particularly strong when there is movement; for example, in scenes such as panning, the content is almost invisible.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital video signal recording/reproducing apparatus that can improve the quality of reproduced images during high-speed reproduction.

[0006]

[Means for Solving the Problems] The present invention records a signal corresponding to a specific area on a screen in a digital video signal to be recorded so as to correspond to a predetermined position on a recording track of a recording medium, and Compared to normal playback, where the tape speed is the same as that during recording,
A digital video signal recording/recording system characterized in that during high-speed playback when the tape speed is higher, signals corresponding to specific areas are sequentially obtained by switching a plurality of playback heads H1 to H4 at predetermined intervals. It is a playback device.

[0007]

[Operation] Since signals of a specific schematic diagram recorded at a predetermined position on a recording track are obtained by a plurality of reproducing heads H1 to H4, a reproduced image can be composed of highly correlated signals.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the recording system of this embodiment. An analog video signal to be recorded is supplied to an input terminal indicated by 1. This video signal is converted into a digital signal by an A/D converter 2. A digital video signal in which one sample is digitized into 8 bits is supplied to a blocking circuit 3. A blocking circuit 3 converts the data arrangement of the video data from the order of scanning lines to the order of blocks. One frame or one field of screen is subdivided into a large number of blocks, for example (4×4=16 pixels) blocks. The output signal of the blocking circuit 3 is supplied to a block encoding circuit 4 and a buffering circuit 5.

The block encoding circuit 4 is, for example, a dynamic range-adaptive encoding proposed by the applicant of the present application. In other words, the applicant of the present application is
A high-efficiency encoding device that obtains a dynamic range defined by the maximum and minimum values of a plurality of pixels included in a two-dimensional block and performs encoding adapted to this dynamic range, as described in Publication No. 144989. is proposed. Furthermore, as described in Japanese Patent Laid-Open No. 62-92620, a high-efficiency encoding device that performs encoding adapted to the dynamic range of a three-dimensional block formed from pixels in areas included in multiple frames is also provided. is suggesting. Furthermore, as described in Japanese Patent Application Laid-Open No. 128621/1982, we proposed a variable length encoding method in which the number of bits is changed according to the dynamic range so that the maximum distortion caused when quantization is constant. are doing. These encodings can be used as block encodings.

[0010] The previously proposed encoding method adapted to the dynamic range (referred to as ADRC) calculates the dynamic range DR (the difference between the maximum value MAX and the minimum value MIN) for each block, and The lowest level (minimum value) within that block is removed from . The pixel data after the minimum value has been removed is converted to a representative level. This quantization divides the detected dynamic range DR into four level ranges corresponding to bits smaller than the original quantization bit number, for example 2 bits, and detects the level range to which each pixel data in the block belongs. , is a process of generating a code signal indicating this level range. When performing 2-bit quantization, the dynamic range DR of the block is divided into four level ranges, and the pixel data included in each of the minimum level range to the maximum level range is (00
) are encoded in order as (01), (10), and (11). Therefore, the 8-bit data of each pixel is compressed to 2 bits and transmitted. On the receiving side, the received code signal is restored to a representative level. This representative level is the center level of each of the four level ranges that serve as quantization standards.

AD adapted to the above dynamic range
RC encoding is suitable for application to digital VTRs because it can significantly compress the amount of data to be transmitted. especially,
Variable length ADRC can increase the compression ratio. However, with variable length ADRC, the amount of data to be transmitted varies depending on the image content, so when using a fixed rate transmission line such as a digital VTR that records a predetermined amount of data as one track, buffering processing is required. Needed. Buffering circuit 5 is provided for this purpose. As the buffering circuit 5, the
As described in the specification of No. 257586, a cumulative dynamic range frequency distribution is formed, and a threshold value for determining the number of allocated bits prepared in advance is applied to this frequency distribution, It is possible to use one that determines the amount of information generated during a predetermined period, for example, one frame period, and controls the amount of generated information so that it does not exceed a target value.

[0012] Here, the present invention is not limited only to ADRC, but also to DCT (Discrete Co
Block encoding such as sine Transform) can be used.

Data necessary for buffering, such as the encoded output of the block encoding circuit 4 and the threshold data from the buffering circuit 5, is supplied to the framing circuit 6. The framing circuit 6 has a dynamic range DR,
The minimum value MIN and the code signal DT are arranged byte serially to form recording data to which a synchronization signal is added. Further, the framing circuit 6 changes the order of recording data of one frame so that the image at the center of the screen of one frame is recorded on the head entry side of the magnetic tape (that is, near the beginning of the track). Further, in the framing circuit 6, error correction codes are encoded for each of the additional codes (DR, MIN) and the code signal DT.

The recording data from the framing circuit 6 is supplied to the recording circuit 7, and processing such as channel encoding and recording amplification is performed by the recording circuit 7. Although the recording signal from the recording circuit 7 is not shown, it is transmitted to the rotary head H via a rotary transformer.
1. In this embodiment, one frame of recording data is recorded as one track. Further, as shown in FIG. 3, four heads H1, H2, H3, and H4 are attached at 90° intervals to a drum 8 that rotates at a frame frequency. Although not shown, a magnetic tape is wound around the circumferential surface of the drum 8 at a wrapping angle larger than about 300 degrees. During recording, one rotary head H1 of the four rotary heads is used.

In the framing circuit 6, as shown in FIG. 4, the screen 9 of one frame is divided into four areas A1 of equal area.
, A2, A3, and A4, the order of the recorded data is rearranged so that the central area A1 is recorded on the track first. That is, FIG. 5 shows a track pattern on a magnetic tape, and as the rotary head H1 scans the magnetic tape from the bottom to the top, diagonal tracks V1, V2, . . . are sequentially formed. Ru. Record data for one frame is recorded on each of tracks V1 to V8. Near the start of each track,
The recording data regarding area A1 is recorded, and then the recording data regarding area A2 is recorded.
The recording data of area A3 is recorded next, and the recording data of area A4 is recorded near the end.

During normal reproduction of the magnetic tape recorded as described above, the magnetic tape is fed at the same speed as during recording, and each track is scanned by the rotary head H1. Furthermore, during high-speed reproduction, four rotary heads H1 to H4 are used. FIG. 2 shows the configuration of the reproducing system, with the rotating head H
Reproduction signals 1 to H4 are supplied to reproduction circuits 11a to 11d through rotary transformers (not shown), respectively. The reproduction circuits 11a to 11d perform reproduction amplification, recovery of reproduction clocks, channel decoding, and the like.

The output signals of the reproducing circuits 11a to 11d are supplied to a switching and combining circuit 12. This switching synthesis circuit 12 is controlled by a switching signal from a switching signal generating circuit 13. The switching signal generating circuit 13 is supplied with a mode control signal from an input terminal 14 . The mode control signal is generated by the system controller and indicates the value of n for n times speed playback, where (n=1) means normal playback mode. This mode control signal is also supplied to a control signal generation circuit 15 that generates a control signal for a buffer memory 18, which will be described later.

In the normal playback mode, the switching synthesis circuit 12 is picked up by the rotary head H1, and the playback circuit 1
Only the reproduced signal output from 1a is selectively output,
In high-speed playback mode (i.e., n>1), the playback signals of the four rotary heads H1 to H4 are output in order.
Controlled by a switching signal. In this embodiment, (n=4 m, m: 1, 2, 3, . . . ) is possible as the double speed ratio n.

The output signal from switching synthesis circuit 12 is provided to block decoding circuit 16. Block decoding circuit 1
6 is for decoding the encoding by the block encoding circuit 4 provided in the recording system, and is, for example, an ADRC decoder. The output signal of the block decoding circuit 16 is fed to a block decomposition circuit 17, which restores the block order data to the raster scan order of the television. The output signal of this block decomposition circuit 17 is transmitted to the buffer memory 18.
supplied to The buffer memory 18 has a capacity that can store, for example, one frame of image data.

A control signal from the control signal generation circuit 15 is supplied to the buffer memory 18 . As described above, in each track, the recording data of each area is recorded in the order of areas A1, A2, A3, and A4. Rotating head H1
In the normal playback mode in which only 1 frame is used, the playback data in this recording order and in the raster scanning order is written to the buffer memory 18, and the data in the normal raster scanning order starting from the upper left of the screen of one frame is read out. . This rearrangement can be performed by controlling the addresses of the buffer memory 18.

In the high-speed playback mode, four rotating heads H
All reproduced signals from 1 to H4 are used. For example, in the 8x playback mode, each head scans the magnetic tape with a time delay of 1/4 frame period, that is, with a shift of 2 tracks. Among the scanning trajectories for one frame of the rotary heads H1 to H4, scanning corresponding to a 1/4 frame period from the start of scanning (T1, T2 in FIG. 6,
The reproduction signal obtained at T3, T4) is switched to the synthesis circuit 1.
2 is selected, and one frame of playback data is formed. As can be seen from FIG. 6, the reproduced data obtained by each partial scan is data in the central portion composed of data for two frame periods.

In the above-mentioned 8x playback mode, in one frame period, area A1 corresponds to scans T1 to T4, respectively.
Reproduction data of 4 times is obtained. Not limited to 8x speed playback, but 4
In 4m double speed playback using rotating heads H1 to H,
Reproduction data of area A1 is obtained four times in one frame period. Here, the reproduced data in area A1 is not composed of data of the same frame, but is composed of data of m frames. In the case of 8x speed playback, the area A1 included in two frames is combined. Also, area A1
is 1/4 of the area of one frame, so 4
A screen with the size of one frame can be constructed by the reproduced data of the areas A1.

In this embodiment, the reproduced data of four areas A1 are displayed in each of the four areas obtained by dividing the screen of one frame into four equal parts. In the example of the 8x playback mode, an image based on the playback data obtained in scan T1 is displayed in the upper left of the screen, and
The image based on the reproduced data obtained in scan T3 is displayed in the upper right corner of the screen, the image based on the reproduced data obtained in scan T3 is displayed in the lower left corner of the screen, and the image based on the reproduced data obtained in scan T4 is displayed in the lower right corner of the screen. to be displayed. The data is rearranged for such divided display in the buffer memory 18. The different sorting processes between the normal playback mode and the high-speed playback mode are controlled by a control signal from the control signal generation circuit 15.

As described above, in the high-speed playback mode, the image at the center of the screen is displayed in four parts, each of which is composed of the signals of each area A1 of two frame periods. Since it is composed of signals of two frame periods, the correlation is strong and the image quality is good even when there is movement. Although only the central part of the screen is reproduced, the purpose of high-speed reproduction, which is to understand the recorded contents, can be achieved. Furthermore, since four consecutive divided images are displayed, it is easier to understand the contents. Note that the present invention is capable of cutting out an image at any arbitrary position, not only at the center of the screen.

The present invention is particularly effective when applied to variable length encoding. That is, in the case of variable-length coding, for example variable-length ADRC, fixed-length data such as the dynamic range and minimum value MIN of a block are arranged regularly, and the encoded data of variable-length pixels are sequentially moved forward. It forms packed recorded data. In this method, the latter half of one track of recorded data is more susceptible to error propagation. However, as described above, since the image data in the center is recorded near the start end of the track, there is an advantage that the image in the center is less prone to errors in the normal playback mode.

The present invention can also be applied to a digital VTR that records/reproduces block-encoded high-resolution video signals such as high-definition signals. A high-definition signal has about five times as much information as a standard-definition signal, and has a different aspect ratio, so down-conversion is required when viewing images played back from a high-definition VTR on a standard monitor. . However, even if down-conversion is performed, there are problems in that areas with no images are created above and below, and images on the left and right are deleted. When this invention is applied, the central part of the screen of a high-definition signal (4
:3) and recorded at a predetermined position on a track on the tape, and in standard mode, only 1/5 of the amount of data is output. As a result, high-definition VT
It becomes possible to view the reproduced image of R on a standard monitor.

[0027]

According to the present invention, since a reproduced image is formed using image data having a strong correlation during high-speed reproduction, the image quality of the reproduced image can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a recording system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a reproduction system according to an embodiment of the present invention.

FIG. 3 is a schematic diagram showing the head arrangement of an embodiment of the present invention.

FIG. 4 is a schematic diagram showing the division of one frame of screen in an embodiment of the present invention.

FIG. 5 is a schematic diagram showing a tape pattern in an embodiment of the present invention.

FIG. 6 is a schematic diagram used to explain high-speed reproduction operation in an embodiment of the present invention.

FIG. 7 is a schematic diagram of a tape pattern used to explain a conventional high-speed reproduction operation.

[Explanation of symbols]

4 Block encoding circuit 6 Framing circuit H1~H4 Rotating head

Claims (1)

[Claims] Claim 1: A signal corresponding to a specific area on the screen in a digital video signal to be recorded is recorded so as to correspond to a predetermined position on a recording track of a recording medium, and a plurality of playback heads are provided, and when recording During high-speed playback where the tape speed is higher than during normal playback where the tape speed is the same, the plurality of playback heads are switched at a predetermined cycle to sequentially obtain signals corresponding to the specific area. A digital video signal recording/reproducing device characterized by: