JPH04339262A - Device for detecting key-striking speed - Google Patents

Abstract

PURPOSE:To enable a detection sensitivity of a key-striking speed to be switched arbitrarily and set by performing an exponential operation after actuation of a first switching means, outputting this exponential operation value as a keystriking speed information indicating the key-striking speed at actuation of a second switching means, switching and giving a change-rate information which determines a ratio of the change in exponential operation value for allowing operation details of exponential operation to be switched. CONSTITUTION:When a switch S1 is closed by striking a key, a numeric value N is read into a memory circuit (a) 7 through a data selection circuit 6, this numeric value N is multiplied by a constant M (0<M<1) by a multiplier 8 at each clock signal phi0 for performing exponential operation. When this constant M is switched and set, contents of the exponential operation change and a detection sensitivity of key-striking speed is switched. Then, when the switch S2 is closed, this exponential operation value is read into a memory circuit (b) 9 and then is outputted. This kind of processing is executed for a plurality of keys by time-sharing.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is a keyboard instrument equipped with a touch response device that detects the speed of keystrokes and controls the volume and timbre of the music generated based on that speed to more faithfully express the player's intentions. The present invention relates to a keystroke speed detection device.

0002

2. Description of the Related Art Conventionally, a well-known typical method for detecting the keying speed is a method of extracting the keying speed using a time constant circuit consisting of a resistive element and a capacitive element. In principle, switches SW1 and SW are closed so that SW1 is closed first when a key is pressed, and then SW2 is closed after a time delay.
W2 is provided under each key. Then, in response to the closing signal of the switch SW1, the capacitive element, which has been charged to a predetermined potential in advance, is discharged via the resistor. That is, the voltage between the terminals of the capacitive element decays exponentially over time. By detecting the potential of the capacitive element based on the closing signal of the switch SW2, which is subsequently closed, the time difference between the closing of the two switches SW1 and SW2 due to key depression can be extracted as a voltage value.

0003

[Problems to be Solved by the Invention] However, such conventional systems have the following drawbacks, and it has been difficult to obtain sufficiently satisfactory performance. In other words, the capacitive element used in the time constant circuit needs to have a relatively large capacity, and the L
It is difficult to downsize such as by making it into an SI. Also, when using multiple time constant circuits for electronic musical instruments with multiple keys,
Since the resistance values and capacitances of the capacitive elements are not uniform, it is necessary to make adjustments to make the time constants uniform.

[0004] Also, the difference in closing time of two switches is expressed as
A method of obtaining the keystroke speed by counting clock pulses with a counter has also been disclosed, but unlike the method using a time constant circuit, the value obtained as the keystroke speed cannot be obtained as an exponential calculation value, and the time constant When replacing it with an electronic musical instrument or the like having a touch response device using a circuit, some kind of conversion device is required.

The object of the present invention is to be able to detect the keying speed with high accuracy and stability using a digital calculation circuit equivalent to a time constant circuit of resistors and capacitors, and to make it possible to miniaturize the device such as an LSI. An object of the present invention is to provide a keystroke speed detection device that can arbitrarily switch and set detection sensitivity.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the present invention performs an exponent calculation after the first switching means is activated, and uses this exponent calculation value at the keystroke speed when the second switching means is activated. The content of the exponent operation can be changed by outputting keying speed information indicating the exponent operation and changing rate information for determining the rate of change of the exponent operation value.

[0007]

[Operation] As a result, keystroke information corresponding to the time difference between the activation points of the two switching means can be outputted through digital processing, and therefore the keystroke speed can be detected with high precision and stability.
Furthermore, it is ideal for downsizing devices such as LSIs, and the detection sensitivity of the keystroke speed can be arbitrarily switched and set by switching the calculation contents of the exponent calculation.

[0008]

Embodiment FIG. 1 is a circuit diagram of an embodiment of the present invention. In the figure, a switch S1 placed under the keyboard of a keyboard instrument, etc.
, S2 are provided so that when the key is pressed, switch S1 is first closed, and then, after a time delay, switch S2 is closed. Also, one terminal of each switch S1, S2 is grounded, and the other terminal is connected to a resistor r1,
It is connected to the power supply Vcc via r2.

Therefore, when the switches S1 and S2 are opened (OFF)
), the potentials at both terminals of the switches S1 and S2 increase to voltage Vcc, and when closed (ON), the potentials at both terminals decrease to 0V. That is, digitally, from the switches S1 and S2, a low level signal "0" is output when closed,
When opened, a high level signal "1" is output. Although a mechanical switch is shown in the figure, any switch that can substantially display two states, open and closed, may be used, such as a switch that uses magnetism or light.

[0010] Flip-flop 1, flip-flop 2
is the closing (ON) of each of switch S1 and switch S2
This signal is provided to synchronize the timing clock signal φ0 from the clock generator 11 with a signal indicating open (OFF). Therefore, switch S
1. When switch S2 is turned ON/OFF, the ON/OFF signals of switch S1 and switch S2 output from flip-flop 1 and flip-flop 2 are output at the timing of the next timing clock signal φ0.

The ON/OFF signal of the switch S1 from the flip-flop 1 is input to the flip-flop 3, and this signal is output after being delayed by one period of the timing clock signal φ0. Therefore, when the AND gate 5 takes the logical product of the output signal of the flip-flop 1 inverted by the NOT circuit 4 and the output signal of the flip-flop 3, the AND gate 5 outputs a single signal at the moment the switch S1 is closed. A pulse is output.

This single pulse has a pulse width of one cycle of the timing clock signal φ0, and is used to control the data selection circuit 6. The data selection circuit 6 is supplied with the numerical value N and the output of the multiplier 8, and the numerical value N is selectively output while a single pulse is being generated, and the output of the multiplier 8 is selectively output at other times. Ru.

The storage circuit (a) 7 is given the timing clock signal φ0 as a storage command signal, and receives the selection output from the data selection circuit 6.
It is output with a delay of one period of the timing clock signal φ0. Then, the output of this memory circuit (a) 7 is a constant M (0<M<1) set in advance in the multiplier 8.
The resultant signal is multiplied by , and then supplied to the data selection circuit 6 again.

Therefore, at the moment when the switch S1 is closed, the numerical value N is stored in the storage circuit (a) 7 via the data selection circuit 6, and thereafter the numerical value N is stored in the storage circuit (a) 7, the multiplier 8,
A cyclic arithmetic circuit formed by the data selection circuit 6 sequentially performs exponent operations at intervals of a constant period of the timing clock signal φ0. Then, the memory circuit (a) 7 outputs an exponentially decreasing calculated value shown in FIG. 2 every cycle of the timing clock signal φ0.

In FIG. 2, the case where M=0.98 and
The calculation contents of two index calculations with M=0.94 are shown, and the state after each switch S1 is closed and the numerical value N is stored in the storage circuit (a) 7 is shown. This constant M determines the rate of change of the above exponent calculation value, and can be arbitrarily switched and set to adjust the value corresponding to the keying speed.

Such sequential timing clock signal φ
By extracting a calculated value that decreases exponentially in synchronization with 0 with the closing signal of switch S2, which closes with a time delay following the closing of switch S1, value can be obtained. That is, when the switch S2 is closed, its closing signal is synchronized with the timing clock signal φ0 by the flip-flop 2 and is given to the storage circuit (b) 9 as a storage command signal. Then, the exponent calculation value from the memory circuit (a) 7 at that time is taken into the memory circuit (b) 9 and output. As a result, key-pressing speed information of the two switches S1 and S2, which close with a time difference as the key is pressed, is detected and output according to the time difference.

FIG. 3 is a circuit diagram of another embodiment of the present invention, in which values corresponding to the keying speeds of a plurality of keys are obtained independently and time-divisionally for each key. In the same figure, a first switch that closes when a key is pressed and a second switch that closes after a time delay from the first switch are arranged separately in correspondence to multiple keys. A set is provided. and means for detecting the closed and opened states of each of the first switches in a time-sharing manner;
Means for obtaining each predetermined value N by detecting the closing points of a plurality of first switches obtained in a time-division manner, and a value that decreases exponentially from the obtained predetermined value N every predetermined unit time. A digital calculation circuit is provided to perform multiple calculations for each key, and by extracting the output of the calculation circuit based on the second switch closing signal obtained in a time-sharing manner, a value corresponding to the keystroke speed is obtained. It is something. FIG. 3 shows an example of eight keys as the plurality of keys.

A timing clock signal nφ0 is generated from the clock generator 11 and applied to the counter 12. The counter 12 is an octal counter and counts continuously in synchronization with the timing clock signal nφ0. The count value of the counter 12 is given to the decoder 13, and the decoder 13
8 time-division time slot signals Q1, Q2, Q
3, . . . , Q8 are decoded and output.

These time division time slot signals Q1, Q2
, Q3, ..., Q8 are low level signals "0", and S1-1 and S2-1, S1-2 and S2 provided for each key.
-2, S1-3 and S2-3, ..., S1-8 and S2-8
is applied to each of the eight sets of switches. These eight sets of switches include a first switch S1 that closes when a key is pressed;
-1, S1-2, . . . and second switches S2-1, S2-2, . . . which close later than the first switches.

Therefore, on the line L1, there are ON/OF signals indicating the closing and opening of the eight first switches corresponding to the eight keys.
The F signal is obtained in a time-division manner, and on line L2 there are ON/OFF signals indicating the closing and opening of eight second switches corresponding to the eight keys.
OFF signals are obtained in a time-division manner. A timing clock signal nφ0 is applied to the flip-flops 14 and 15 to which the signals of lines L1 and L2 are input, and the ON/OFF signals of the first switch and the second switch are synchronized with the timing clock signal nφ0. flip flop 1
4 and 15 in a time-division manner.

The output of this flip-flop 14 is input to a shift register 16, and this shift register 16 has 8
This is a serial input and serial output shift register of the stage, and sequentially shifts in response to the timing clock signal nφ0. The shift register 16 serially stores ON/OFF signals of the eight first switches for one time division frame, and the stored contents are delayed by eight timing clock signals.

Therefore, the output of the flip-flop 14 is N
The signal inverted by the OT circuit 17 and the output of the shift register 16 are given to the AND gate 18 to perform a logical product.
Signals indicating the instants at which the first switches are closed are sequentially obtained in a time-division manner. The circuit of FIG. 3 is constructed so that a high level signal "1" is generated in the time slot corresponding to the closed key.

On the other hand, from the flip-flop 15,
ON/OFF signals of the eight second switches are output in a time-division manner and input to the shift register 19 and NOT circuit 20. The output of this NOT circuit 20 and the shift register 1
The output of 9 is given to AND gate 21, and this AND
As in the case of the first switch described above, from the gate 21, signals indicating the moments when eight second switches provided for each key are closed are sequentially obtained in a time-sharing manner.

The data selection circuit (A) 22 is supplied with the numerical value N and the output of the multiplier 24, and the AND gate 18
Depending on the signal obtained, one of the two inputs is selected and output. When a certain key is pressed and the first switch corresponding to that key is closed, in the time slot corresponding to that key, the output of the AND gate 18 is set only at the moment when the first switch is closed. A high level signal "1" is generated at the period of the timing clock signal nφ0, and as a result, the data selection circuit (A) 22 selects the numerical value N. Further, when the output of the AND gate 18 is a low level signal "0", the output of the multiplier 24 is selected.

The output of the data selection circuit (A) 22 is given to a storage circuit (A) 23, and a timing clock signal n
The data is sequentially captured and stored at the timing of φ0. As the memory circuit (A) 23, an 8-stage serial input/serial output multi-bit shift register corresponding to the number of keys is used, and shifts are performed sequentially in response to a timing clock signal nφ0.

Therefore, the output from the data selection circuit 22 is delayed from the output from the storage circuit (A) 23 by eight timing clock signals nφ0. In this way, the memory circuit (A) 23 performs a shift operation in synchronization with the shift register 16. The output of this memory circuit (A) 23 is sent to a multiplier 24 using a preset constant M (0<M
<1) and provided to the data selection circuit 22.

When a certain key is pressed, the first
When the switch is closed, the numerical value N is stored in the memory circuit (A) 23 in the time slot corresponding to the key, and then the numerical value N is stored in the memory circuit (A) 23, the multiplier 24, and the data selection circuit. (A) A cyclic arithmetic circuit of 22 sequentially performs exponential operations in time slots of a constant period corresponding to every eight timing clock signals nφ0. That is, the exponentially decreasing values shown in FIG. 2 can be obtained independently for each key in a time-sharing manner.

On the other hand, following the closing of the first switch provided for each key, a signal indicating the closing of the second switch, which is closed with a time delay, is sent by the AND gate 21 in a time-division manner. The signal is outputted and given to the data selection circuit (B) 25 as a storage command signal. Then, the memory circuit at that time (A
) 23 is taken into the storage circuit (B) 26 and output. The memory circuit (B) 26 is similar to the memory circuit (A) 23, and is sequentially shifted by the timing clock signal nφ0. Therefore, the keying speed information for each key is output from the memory circuit (B) 26 in a time-division manner.

In this embodiment, the memory circuit (A) 23
Although a shift register is used for the storage circuit (B) 26, it may be replaced with a random access memory or the like. In addition, the output of the memory circuit (B) 26 is a digital
An analog converter may also be provided to obtain the key pressing speed as an analog value. Note that by arbitrarily switching and setting the constant M given to the multiplier 24, the sensitivity of the value corresponding to the keying speed can be adjusted.

[0030]

As explained above, the present invention performs exponent calculation after the first switching means is activated, and converts this exponent calculation value into keystroke speed information indicating the keystroke speed at the time of activation of the second switching means. The content of the exponent calculation is switched by outputting the information as follows, and changing rate information for determining the rate of change of the exponent calculation value is switched and given. Therefore, it is possible to output keystroke information according to the time difference between the activation points of the two switching means through digital processing, and therefore the keystroke speed can be detected with high precision and stability.
In addition to being ideal for downsizing devices such as computer systems, it is also possible to arbitrarily switch and set the detection sensitivity of keystroke speed by switching the contents of the exponent calculation.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing the contents of exponent calculation according to the present invention.

FIG. 3 is a circuit diagram of another embodiment of the present invention.

[Explanation of symbols]

1, 2, 3, 14, 15...Flip-flop, 4, 17
, 20...NOT circuit, 5, 18, 21...AND gate,
6, 22, 25...data selection circuit, 7, 9, 23, 26
...Memory circuit, 8, 24... Multiplier, 11... Clock generator, 12... Counter, 13... Decoder, S1, S2, S1
-1 to S1-8, S2-1 to S2-8...switches.

Claims (1)

[Claims] 1. A first switching means that operates in response to a keystroke; and a first switching device that operates in response to a keystroke;
a second switching means that operates with a time delay from the switching means; an exponent calculation means that performs an exponent calculation after the activation of the first switching means; and an exponent calculation value calculated by the exponent calculation means, At the time of activation of the second switching means, the output means outputs the keying speed information indicating the keying speed and the change rate information that determines the rate of change of the exponent calculation value calculated by the exponent calculation means. 1. A keying speed detecting device comprising: switching means for switching and applying information to a calculating means to switch the content of the exponent calculation of the exponent calculating means.