JPH0554069B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention detects the speed of keystrokes and controls the volume and timbre of the musical tones generated based on the speed to more faithfully express the performer's intention. The present invention relates to a method for detecting keystroke speed in a keyboard instrument or the like having a response device.

(2) Prior Art and Problems Conventionally, a well-known typical method for detecting the keying speed is a method of extracting the keying speed using a time constant circuit consisting of a resistive element and a capacitive element. In principle, two switches SW1 and SW2 are provided under the keyboard so that when a key is pressed, SW1 is first closed, followed by SW2. First, in response to the closing signal of SW1, the capacitive element, which has been charged to a predetermined potential in advance, is discharged via the resistor. That is, the voltage between the terminals of the capacitive element decays exponentially over time. Therefore, by detecting the potential of the capacitive element based on the closing signal of SW2, which is subsequently closed, it is possible to extract the time difference between the closing of the two switches SW1 and SW2 due to key depression as a voltage value. can.

However, such conventional methods have the following drawbacks, and it has been difficult to obtain sufficiently satisfactory performance. That is, the capacitive element used in the time constant circuit needs to have a relatively large capacity, and it is difficult to miniaturize it by making it into an LSI. In addition, when multiple time constant circuits are used for an electronic musical instrument with multiple keys, each resistance value and capacitance of the capacitive element are uneven, so adjustment is required to make the time constants uniform. There were some inconveniences.

Also, a method is disclosed in which the keying speed is obtained by counting the clock pulses with a counter to determine the time difference between the closing times of two switches, but as with the method using a time constant circuit, the keying speed and the obtained value are exponential Therefore, when replacing it with an electronic musical instrument or the like having a touch response device using a time constant circuit, some kind of conversion device is required.

(3) Purpose of the Invention The purpose of the present invention is to provide a keying speed detection device that can detect the keying speed with high accuracy and stability using a digital calculation circuit equivalent to a time constant circuit of resistors and capacitors, and that can be miniaturized by using an LSI. It is to provide.

(4) Structure of the Invention In order to achieve the above-mentioned object, the keystroke speed detection device of the present invention provides a keyboard instrument that has a keyboard consisting of a plurality of keys and generates a musical tone by striking the keys. a first switch that closes when a key is pressed; a second switch that closes with a time delay from the first switch; and the first switch and second switch of the plurality of keys. detection means for scanning and detecting the state of each switch; means for setting a predetermined value N based on a signal indicating the closing time of the first switch from the detection means; digital calculation means for time-divisionally calculating a value that decreases over time, and a digital calculation means that calculates a value that decreases in time based on a signal from the detection means indicating the point in time when the second switch is closed; It is characterized by obtaining a value.

(5) Embodiment of the invention FIG. 1 is an explanatory diagram of the configuration of an embodiment of the invention.
In the figure, switches S1 and S2 placed under the keyboard of a keyboard instrument or the like are provided so that when a key is pressed, switch S1 is first closed, followed by switch S2. In addition, each switch is connected to the power supply voltage Vcc through resistors r ₁ and r ₂ as shown in the figure, and when it is open (OFF), it is connected to the voltage Vcc, and when it is closed (ON), it is connected to the power supply voltage Vcc.
Time is grounded. In other words, digitally ON
The respective switches S1 and S2 output "0" when the switch is turned off, and "1" when the switch is OFF. Although a mechanical switch is shown in the figure, any switch that uses magnetism or light that can essentially display two states, open and closed, can be easily applied. Flip-flop 1 and flip-flop 2 are provided to synchronize signals indicating the closing (ON) and opening (OFF) of switches S1 and S2 with timing clock φ ₀ . Therefore, switch S1, switch S
2 turns ON/OFF, the switch S output from flip-flop 1 and flip-flop 2
1. The signal indicating ON/OFF of switch S2 is a signal synchronized with timing clock _φ0 . Flip-flop 3 receives the output of flip-flop 1 as an input, and receives a signal indicating the closing or opening of switch S1, which is synchronized with timing clock φ ₀ by flip-flop 1, from timing clock φ ₀ .
The signal is output with a delay of one period. Therefore, when the output signal of flip-flop 1 is inverted by NOT circuit 4 and the output of flip-flop 3 is ANDed by AND gate 5, the output of AND gate 5 has a timing signal at the moment switch S1 is closed. A single pulse having a pulse width of one cycle of the clock φ ₀ is generated, and this single pulse is used to control the data selection circuit 6. The data selection circuit 6 receives the numerical value N and the output of the multiplier 8, and selectively outputs the numerical value N while a single pulse is being generated.
During other times, the output of the multiplier 8 is selected and output. The memory circuit 7 is supplied with a timing clock φ ₀ and outputs the output from the data selection circuit ₆ with a delay of one cycle of φ ₀ at the rate of the timing clock φ 0 . Then, the output of the storage circuit 7 is multiplied by a preset constant M (0<M<1) in a multiplier 8 and provided to the data selection circuit 6. That is, at the moment the switch S1 is closed, the numerical value N is stored in the memory circuit 7 via the data selection circuit 6, and then the numerical value N is stored in the cyclic arithmetic circuit consisting of the memory circuit 7, the multiplier 8, and the data selection circuit 6. The calculations are performed sequentially at the cycle of the timing clock _φ0 . From the output of the memory circuit 7, a value that decreases exponentially in accordance with the period of the timing clock φ ₀ as shown in FIG. 2 can be obtained.

In Figure 2, the case of M=0.980 and the case of M=
Two cases of 0.94 are shown, and in each case the value N is stored at the moment when the switch S1 is closed.

In this way, the timing clock φ ₀
By extracting the value that decays exponentially in synchronization with the key pressing speed and the closing signal of switch S2, which closes with a time delay following the closing of switch S1, value can be obtained.
That is, when the switch S2 is closed, the closing signal is synchronized with the timing clock φ ₀ by the flip-flop 2, and is attenuated in synchronization with the output of the memory circuit 7, that is, the timing clock φ ₀ . It is configured to be given as a timing signal for writing a value into the memory circuit 9, and the value corresponding to the time difference between two switches that close with a time difference as a key is pressed is detected.

FIG. 3 is a configuration explanatory diagram of another embodiment of the present invention, and is an example of a circuit for obtaining values corresponding to the keying speeds of a plurality of keys independently for each key.

In the same figure, the first
A plurality of sets of a switch and a second switch that closes later than the first switch are separately provided in correspondence with a plurality of keys. and a means for time-divisionally detecting the closed and open states of each of the first switches, and a means for detecting the closing time points of the plurality of first switches obtained in a time-divisionally manner to obtain a predetermined value N.
and a digital arithmetic circuit for each key to calculate a plurality of values that exponentially decrease from the obtained predetermined value N every predetermined unit time, and a second switch obtained in a time-division manner. By extracting the output of the arithmetic circuit based on the closing signal of , a value corresponding to the keying speed is obtained.

In the figure, eight keys are illustrated as the plurality of keys.

The clock generator 11 is a timing clock nφ ₀
is generated and given to the counter 12. counter 1
2 is an octal counter and a timing clock.
Continuously count in synchronization with nφ ₀ . counter 12
The count value of is given to the decoder 13, and the decoder 1
3 outputs eight time division time slots as its output, and the outputs ₁ , ₂ , Q ₃ ,..., ₈ are the first switch that closes when the key is pressed, and the time slots from the first switch. It consists of a second switch that closes after a certain delay, and S1-1 and S1 are provided for each key.
-2, S1-2 and S2-2, S1-3 and S2-
3,..., given to 8 sets of S1-8 and S2-8. Therefore, on line L1, signals indicating the closing and opening of eight first switches corresponding to eight keys are obtained in a time-division manner, and on line L2, signals indicating the closing and opening of eight first switches corresponding to eight keys are obtained in a time-division manner. A signal indicating whether the second switch is closed or opened is obtained in a time-division manner. A timing clock nφ ₀ is provided to the flip-flops 14 and 15 that input the signals on the lines L1 and L2, and a time division signal indicating the closing and opening of the first switch and the second switch is sent to the timing clock nφ ₀ . Used for synchronized formatting. The output of the flip-flop 14 is given as an input to an 8-stage serial input/serial output shift register 16 which is shifted by the timing clock _nφ0 , and time-division signals indicating the closing and opening of the eight first switches are generated. An output delayed by one time division frame, here eight timing blocks, is obtained. Therefore, by providing the AND gate 18 with a signal obtained by inverting the output of the flip-flop 14 by the NOT circuit 17 and the output of the shift register 16, and performing a logical product, the output of the AND gate 18 is used to calculate the 8 signals provided for each key. A signal indicating the moment when the first switch is closed is obtained as a time-shared signal. In the circuit of FIG. 3, a "1" is shown to occur in the time slot corresponding to the closed key.

On the other hand, the output of the flip-flop 15, which indicates time-division signals indicating the closing and opening of the eight second switches, is applied to a shift register 19 and a NOT circuit 20. Output of NOT circuit 20, shift register 1
The output of 9 is given to the AND gate 21, and as in the case of the first switch described above, the signals indicating the moments when the eight second switches provided for each key are closed are ANDed as time-division signals. It is obtained from the output of gate 21.

The data selection circuit A22 receives the numerical value N and the output of the multiplier 24 as input, and one of the two inputs is selected and output according to the signal obtained from the AND gate 18. That is, when a certain key is pressed and the first switch corresponding to that key is closed, the output of the AND gate 18 is changed only at the moment when the first switch is closed in the time slot corresponding to that key. , "1" occurs at the cycle of timing clock nφ ₀ , and N is output to data selection circuit A22.
is selected. When the output of the AND gate 18 is "0", the output of the multiplier 24 is always selected.

The output of the data selection circuit A22 is the memory circuit A23.
The memory circuit 23 sequentially writes the output of the data selection circuit A22 at the timing of the timing clock _nφ0 .

The memory circuit A23 uses an 8-stage serial input/serial output shifter register corresponding to the number of keys of a plurality of bits, and sequentially performs a shifting operation using a timing clock _nφ0 . Therefore, the output of the data selection circuit 22 to be written sequentially is ₈ of the timing clock nφ0.
It is obtained from the output of the storage circuit A23 after being delayed by one time. In this way, the memory circuit A23 performs a shift operation in synchronization with the shift register 16. That is, the output of the storage circuit A23 is multiplied by a preset constant M (0<M<1) in a multiplier 24, and then provided to the data selection circuit 22.

That is, when a certain key is pressed and the first switch corresponding to that key is closed, the numerical value N is stored in the memory circuit A23 in the time slot corresponding to that key, and then the numerical value N is stored in the memory circuit A23. Circuit A2
3. A cyclic arithmetic circuit consisting of a multiplier 24 and a data selection circuit A22 generates a timing clock.
It is calculated in the time slot corresponding to every 8 nφ ₀ and outputted from the storage circuit A23. That is, the second
The exponentially decreasing values shown in the figure can be obtained for each key independently in a time-division manner.

On the other hand, following the closing of the first switch provided for each key, a signal indicating the moment of closing of the second switch, which closes with a time delay, is output in a time-sharing manner.
The output of the AND gate 21 is the data selection circuit B2
5 as a control signal, and when the second switch is closed, the exponentially decaying value output from the memory circuit A23 is selected and given to the memory circuit B26, and in other cases has memory circuit B
26 outputs are selected. The memory circuit B26 is similar to the memory circuit A23, and is sequentially shifted using a timing clock _nφ0 . Therefore, from the output of the memory circuit B26, a value corresponding to the key pressing speed can be obtained for each key separately in a time-division manner.

In this embodiment, shift registers were used for the memory circuit A23 and the memory circuit B26, but
It may be configured by replacing it with a random access memory or the like. It is also possible to provide a digital-to-analog converter at the output of the memory circuit B26 to obtain a value corresponding to the key pressing speed as an analog value. Note that by arbitrarily setting the constant M given to the multiplier 24, the value corresponding to the keying speed can be adjusted.

(6) Effects of the Invention As explained above, according to the present invention, a circuit equivalent to a conventional time constant circuit consisting of a resistor and a capacitor is constructed with a digital arithmetic circuit, and a highly accurate and stable keying speed can be achieved. The value corresponding to can be extracted. The keystroke information obtained in this manner can be effectively used to control the tone, volume, and other effects of electronic musical instruments. Furthermore, it is possible to downsize it by making it into an LSI, etc., and it is also easy to perform time division multiplexing, and it is possible to extract values corresponding to the keying speed of multiple keys for each key with a small number of parts.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram of characteristics of essential parts of the present invention, and FIG. 3 is an explanatory diagram of the configuration of another embodiment of the present invention. 2,
3, 14, 15 are flip-flops, 4, 17,
20 is a NOT circuit, 5, 18, 21 are AND gates, 6, 22, 25 are data selection circuits, 7, 9,
23, 26 are storage circuits, 8, 24 are multipliers, 11
is a clock generator, 12 is a counter, 13 is a decoder, S1, S2, S1-1 to S1-8, S2-
1 to S2-8 indicate switches.

Claims (1)

[Scope of Claims] 1. A keyboard instrument that has a keyboard consisting of a plurality of keys and generates musical tones when the keys are struck, which is provided for each of the plurality of keys and closes when the keys are struck. a second switch that is provided for each of the plurality of keys and that closes with a time delay from the first switch when the key is pressed; a detection means for scanning the second switch and detecting the state of each switch; a setting means for setting a predetermined value N in response to the closing of the first switch detected by the detection means; A digital cyclic calculation means that calculates a value that decreases exponentially every predetermined unit time from a predetermined value N set by a setting means in a time-sharing manner for each key. , storage means for storing a plurality of values that decrease exponentially from the predetermined value N set by the setting means for each key;
1) a calculation means that repeatedly performs the multiplication operation every predetermined unit time, thereby calculating a value that decreases exponentially from the predetermined value N in a time-sharing manner for each key; a memory selection means for storing the predetermined value N in the storage means, and storing the predetermined value N in the storage means when the predetermined value N is set by the setting means; A keystroke speed detection device characterized in that a value corresponding to a keystroke speed is obtained from the digital cyclic calculation means in response to the detected closing of the second switch.