JPH04335728A - Interface circuit - Google Patents

Abstract

PURPOSE:To prevent a data read error by devising it so that a timing to read a data at high speed transmission is kept within a prescribed range. CONSTITUTION:The interface circuit reading a data synchronously with a rising or falling of a timing signal is provided with a detection means (equivalent to a disable area detection circuit 3 and a disable area generating circuit 6) detecting it that the rising or the falling of the timing signal comes around the rising or the falling of the relevant data and a phase control means (equivalent to an inverting circuit 4, a selection circuit 5 and a selection control circuit 7) controlling the phase shift of the timing signal when the detection means detects it that the rising or the falling of the timing signal comes around the rising or the falling of the data. The data is read by using the timing signal whose phase is controlled by the phase control means. The data read error is prevented in this case.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit between a terminal equipment (hereinafter abbreviated as DTE) and a line termination equipment (hereinafter abbreviated as DCE).

0002

[Prior Art] Conventionally, CC is used as this type of interface.
ITTV28, V. 35 or X. 21, but the one that transmits data at high speed is CCITTV. 35 or X. 21 are used. These interface standards specify the phase relationship between the data signal and the timing signal, and the falling edge of the timing signal is the nominal center of the data signal, and the data signal is read into the DCE at the falling edge of the timing signal. It is now possible to

[0003] Therefore, when the above-mentioned interface is used for high-speed communication with a data rate of 1.5 Mbps, and the length of one data is 666 nS, the data is It will be loaded. However, when the timing signal is supplied from the DCE to the DTE when reading data as described above, the following delay occurs. (1)D
When the timing signal is output from the CE, the timing signal is CCITTV. 35 or X. 21 interface conversion, this conversion causes a delay. (2) When the DTE inputs the timing signal, the timing signal is input to CCITTV. 35 or X. 2
1 interface conversion, this conversion causes a delay. (3) A delay occurs when data is output from the DTE. (4) A delay occurs when data is input to the DCE. (5) Delays occur due to cables connecting DTE and DCE. If you add up the delays caused by the reasons shown in (1) to (5), the total delay may be 333 nS in some cases, and in such cases, DCE
When the data signal from the DTE is read at the falling edge of the timing signal, the edge portion of the data signal is read, which has the drawback of causing reading errors due to jitter and the like.

0004

[Problem to be solved by the invention] As mentioned above, DTE and D
When the interface circuit between CEs is used for high-speed transmission,
This has the drawback of causing data reading errors because the data reading position shifts due to signal interface conversion and signal delays caused by cables.

SUMMARY OF THE INVENTION Therefore, the present invention aims to eliminate the above-mentioned drawbacks, and aims to provide an interface circuit that can prevent data reading errors by ensuring that the timing of reading data during high-speed transmission falls within a predetermined range. It is said that [Structure of the invention]

[0006]

[Means for Solving the Problems] The present invention provides an interface circuit that reads data in synchronization with the rising or falling edge of a timing signal, when the rising edge or falling edge of the timing signal comes near the rising edge or falling edge of the data. a detection means for detecting this, and a phase control for controlling the phase of the timing signal when the detection means detects that the rising edge or falling edge of the timing signal is near the rising edge or falling edge of the data; The data is read using a timing signal whose phase is controlled by the phase control means.

[0007]

In the interface circuit of the present invention, the detection means detects that the rising or falling edge of the timing signal comes near the rising edge or falling edge of the data. The phase control means performs control to shift the phase of the timing signal when the detection means detects that the rise or fall of the timing signal is near the rise or fall of the data. The data is read using a timing signal whose phase is controlled by the phase control means.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an interface circuit according to the present invention. 1 is an interface conversion circuit that converts the level of the data signal; 2 is a latch circuit that latches the data signal whose level has been converted by the interface conversion circuit 1 in synchronization with the timing signal 100 or 101; and 3 is the output from the impossible area creation circuit 6. an unusable area detection circuit that reads the unusable area signal at the rising or falling edge of the data signal output from the interface conversion circuit 1, and outputs an unusable area detection signal of "1" to the selection control circuit 7 when the unusable area is read; 4 is an inverting circuit that inverts the polarity of the timing signal output from the frequency dividing circuit 8 by 180 degrees, 5 is a selection circuit that selects and outputs either the timing signal 100 or the inverted timing signal 101, and 6 is a frequency dividing circuit Timing signal 100 or 1 outputted from selection circuit 5 by clock 50 outputted from 8
7 is a selection control circuit that inverts the output control signal 70 when the detection signal output from the impossibility area detection circuit 3 is input; A frequency dividing circuit divides the frequency of the generated reference signal to create a timing signal 100 and a clock 50, 9 is an oscillator that generates the reference signal, and 10 is an interface conversion circuit that converts the level of the timing signal 100. It is assumed that the illustrated interface circuit is built into the DCE.

Next, the operation of this embodiment will be explained. The reference signal generated by the oscillator 9 is frequency-divided by the frequency divider circuit 8 into a timing signal 100 and a clock 50,
The timing signal 100 is sent to the interface conversion circuit 10,
The clock 50 is input to the inversion circuit 4 and the selection circuit 5, and the clock 50 is input to the impossible area creation circuit 6. The interface conversion circuit 10 converts the level etc. of the input timing signal 100 and outputs it to a DTE (not shown). As a result, the DTE performs data synchronization with the timing signal.
This data signal is input to the interface conversion circuit 1. The interface conversion circuit 1 converts the level of the input data signal and outputs it to the latch circuit 2 and the invalid area detection circuit 3. On the other hand, the timing signal 100 input to the inverting circuit 4 has a polarity of 1.
The signal is converted by 80 degrees and becomes a timing signal 101, which is output to the selection circuit 5. The selection circuit 5 is the selection control circuit 7
Timing signal 1 is controlled by control signal 70 output from
Select either 00 or 101 and latch circuit 2
Output to. Latch circuit 2 is interface conversion circuit 1
The data signal input from the timing signal is latched at the falling edge of the timing signal.

FIGS. 2A and 2B show the normal relationship between the timing signal and data signal input to the latch circuit 2, and the falling edge of the timing signal 100 or 101 corresponds to the data signal. The data signal is located almost at the center of the timing signal, and the data signal is latched into the latch circuit 2 at the falling edge of this timing signal.

By the way, the clock 50 created by the frequency dividing circuit 8 is as shown in FIG. The specified timing signal is read. Here, assuming that the clock 50 is four times faster than the timing signal 100, the impossible area creation circuit 6 shifts the timing signal input by the shift register into three stages. 3(B) shows a timing signal shifted by one stage, FIG. 3(C) shows a timing signal shifted by two stages, and FIG. 3(D) shows a waveform of a timing signal shifted by three stages. As described above, after shifting the timing signal to three stages, the AND condition of the two-stage shift signal shown in FIG. 3(C) and the inverted signal of the three-stage shift signal shown in FIG. 3(D) is taken. The signal shown in FIG. Here, the impossible area signal 60 indicates the area before and after the fall of the timing signal output from the selection circuit 5.

The impossible area detection circuit 3 takes in the impossible area signal 60 as shown in FIG. 4(C) at the falling or rising edge of the data signal shown in FIG. 4(B). Figure 4(B)
, (C), the impossible area detection circuit 3 sets its output to "1" and outputs it to the selection control circuit 7. When the selection control circuit 7 receives a signal of "1" from the impossible area detection circuit 3, it inverts the polarity of the control signal 70 at point A in FIG. 4(D). When the polarity of the control signal 70 output from the selection control circuit 7 is reversed, the selection circuit 5 changes the selected timing signal 100 (or 101) to the timing signal 1.
01 (or 100) as shown in FIG. 4(E), and outputs the changed timing signal to the latch circuit 2. Therefore, in the latch circuit 2, the falling edge of the timing signal deviates from the center of the data signal due to circuit delays, etc.
When the timing signal comes near the rising edge or falling edge of the data signal, the polarity of the timing signal is reversed by 180 degrees so that the falling edge of the timing signal comes near the center of the data signal.

According to this embodiment, the prohibited area creating circuit 6 creates the prohibited area signal 60 indicating a predetermined range before and after the fall of the timing signal for data reading, and the prohibited area signal 60 indicates the range indicated by the prohibited area signal 60. When there is a rising or falling edge of the data signal to be read, control is performed to shift the phase of the timing signal so that the falling edge of the timing signal is always near the center of the data signal. Therefore, errors when reading the data signal can be eliminated. Incidentally, in the above embodiment, when the falling edge of the timing signal deviates from around the rising edge or falling edge of the data to be read, the phase of the timing signal is shifted by 180 degrees; however, the phase of the timing signal is not limited to this. The phase may be shifted so that the falling edge (or rising edge) is near the center of the data signal. Furthermore, in the above embodiment, the clock 50 is set to four times the speed of the timing signal 100;
The clock may be faster.

[0014]

As described above, according to the interface circuit of the present invention, data reading errors can be prevented by ensuring that the data reading timing falls within a predetermined range during high-speed transmission.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an interface circuit of the present invention.

FIG. 2 is a waveform diagram showing a normal relationship between a timing signal and a data signal in the circuit of FIG. 1;

FIG. 3 is a waveform diagram showing the process of creating an impossible area signal used in the circuit of FIG. 1;

FIG. 4 is a waveform diagram illustrating a phase changing operation of a timing signal in the circuit shown in FIG. 1;

[Explanation of symbols]

1, 10...Interface conversion circuit 2...Latch circuit 3...Unusable area detection circuit
4... Inversion circuit 5... Selection circuit
6...Unusable area creation circuit 7...Selection control circuit
8... Frequency divider circuit 9... Oscillator

Claims (1)

[Claims] 1. An interface circuit that reads data in synchronization with a rising edge or falling edge of a timing signal, comprising: a detection means for detecting that the rising edge or falling edge of the timing signal comes near the rising edge or falling edge of the data; , comprising phase control means that controls to shift the phase of the timing signal when the detection means detects that the rise or fall of the timing signal is near the rise or fall of the data; An interface circuit characterized in that the data is read using a timing signal whose phase is controlled by the phase control means.