JPH04334119A - Level conversion integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a level conversion circuit due to the influence of so-called power supply noise caused by the conversion circuit and its succeeding output buffer circuit sharing a same power supply with respect to the level conversion integrated circuit converting a TTL level input into a CMOS level output. CONSTITUTION:A variable conductance circuit 2 is inserted between the output node NO of a pre-stage inverter 1 of CMOS configuration connected to the input terminal T1 of a TTL input D1 and the succeeding-stage inverter 3 of CMOS configuration receiving its output signal at its input node N1 and responding to the signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion integrated circuit, and more particularly to a semiconductor level conversion integrated circuit for converting a TTL level input to a CMOS level.

0002

2. Description of the Related Art Today, logic integrated circuits, especially memory circuits, are becoming larger in scale and faster in speed. However, as shown in FIG. For example, the power supply level VD and the ground level VG are fluctuated to generate so-called power supply noise vn, which causes various malfunctions. That is, the output buffer circuit 5, which outputs the data DO to the outside asynchronously, is generally the circuit through which the largest current flows in the integrated circuit 20a, and near the transient time tb when the output voltage DO changes, the output buffer circuit 5 outputs the data DO to the outside as shown in FIG. 4(c). It is well known that power supply noise vn is generated on ground voltage VG by parasitic inductance within the integrated circuit.

This ground noise is transmitted as power supply noise vn to each internal circuit connected to the power supply terminal TD and the ground terminal TG via the DC power supply wiring, but normally the CM
There is almost no direct influence on the internal circuit 4 to which the OS level signal is input. However, this has a direct adverse effect on the level conversion circuit 10a, which consists of the front-stage inverter 1 which inputs the TTL level logic input data DI to the input terminal TI, and the rear-stage inverter 3 via the intermediate node X.

More specifically, as shown in FIG. 3, the conventional level conversion circuit 10a is a p-type circuit in which a TTL level input voltage DI is input to the gate, the source is connected to the power supply terminal TD, and the drain is connected to the node NO. A front-stage inverter 1 having a CMOS configuration consisting of an enhancement MOS transistor pEO and an n-type enhancement MOS transistor nEO whose gate receives logic data DI, whose source is connected to a ground terminal TG, and whose drain is connected to a node NO;
A downstream inverter 3 having a similar CMOS configuration is provided via an intermediate node X.

Next, the basic operation will be explained using FIG. 4. As shown in Figure (a), this external address input data DI is normally at TTL level, and at "H" level it is 2.
It is around 2V, and around 0.8V at "L" level. Therefore, the CMOS transistor pEO,n of the front-stage inverter 1 is adjusted so that the threshold voltage corresponds to such a TTL level.
The gate size of EO is designed. Here time ta
1, the external address ADD of input data DI is “L” 0.
The output data DO of the integrated circuit 20a changes from 8V to "H" 2.2V, and the output data DO of the integrated circuit 20a corresponding to this changes at time t after delay time Td.
d, and its output data DO changes from “H” to “L”.
”.In this level conversion circuit, the output data DO
Near the steep time tb, power supply noise vn is superimposed on the ground voltage VG as shown in FIG. 4(c). At that time, the transistor nEO has a gate input of 2.2
The positive pulse part n of this noise VG was receiving V.
The threshold voltage VT of transistor nEO momentarily at p
N, it becomes “L” as if it were a gate input.
As shown in FIGS. 4(d) and 4(e), near the time tb when the noise pulse np is generated, the "H" level pulse HP is applied to the node NO, and the "L" level is applied to the node N2. The level pulse LP is output, resulting in an adverse effect that an unexpected address is generated.

[0006]

[Problem to be Solved by the Invention] This conventional level conversion integrated circuit has a problem in that incorrect addresses occur due to power supply noise accompanying the change of output data from the "H" level to the "L" level. Ta.

[0007]

[Means for Solving the Problems] The level converting integrated circuit of the present invention inputs TTL level input data from an external input terminal to a preceding stage logic circuit and an intermediate node to a subsequent stage logic circuit and converting it into a CMOS level internal circuit. It has a level conversion circuit that outputs data, and an internal circuit that inputs the internal data and outputs output data from an external output terminal via an output buffer circuit, and the circuits are connected to the same power supply terminal and ground terminal, respectively. A level conversion integrated circuit receiving a direct current voltage, the intermediate node having a variable conductance element whose drain and source are connected and whose gate is controlled by an off control pulse with a predetermined delay time corresponding to the input data. It is constructed by inserting a variable conductance circuit.

[0008]

[Example] Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention, in which a p-type enhancement MOS transistor pEO is connected to the gate with input data DI, the source is connected to the power supply terminal TD, and the drain is connected to the node NO, and the input data DI is input to the gate and the source is connected. a front-stage inverter 1 having a CMOS configuration including an n-type enhancement MOS transistor nEO whose drain is connected to a ground power supply terminal TG and a node N1; pE1 whose gate input is the node V1, whose source is connected to the power supply VD and whose drain is connected to the node V2; A delay pulse generation circuit 2a that inputs input data DI and generates a predetermined delay pulse φ, and an n-type depletion circuit M that inputs the delay pulse φ to the gate, connects the source to the node NO, and the drain to the node N1.
A variable conductance circuit 2 having an OS variable conductance transistor nDO, and a p-type enhancement MOS transistor pE1 having a gate connected to a node N1, a source connected to a power supply terminal TD, and a drain connected to a node N2.
and a rear-stage inverter 2 having a CMOS configuration including an n-type enhancement MOS transistor nE1 whose gate receives input data DI, whose source is connected to the ground power supply terminal TG, and whose drain is connected to the node N2.

Here, it is assumed that a TTL level is applied as the input data DI, that 5V is normally applied to the power supply voltage VD, and 0V is applied to the ground voltage VG. The delayed pulse generation circuit 2a receives input data AD as shown in FIG. 2(d).
A gate signal φ having a downward convex width TW is generated from a time td after a delay time Td from a rising time ta1 of D.

Next, regarding the basic operation of the circuit shown in FIG.
) to (g). For example, at time ta1, the address data ADD of the input data DI changes from "L" level of 0.8V to "H" level of 2.2V, and at time td after a delay time Td from time ta1, the external output terminal TD is output. Output data DO changes from "H" level to "L" level. Then, near time tb when power supply noise vn is generated in the ground power supply VG caused by the output data DO, the input data DI is "
Even though 2.2V at the H level is applied, the noise pulse np of the power supply noise vn makes the transistor nEO feel a relatively low level at the gate for a moment, and the node NO becomes high. However, near time tb, the gate of the variable conductance transistor nDO outputs a voltage VO of "L" level (
Since the gate pulse φP of 0V) is applied, the conductance of the transistor nDO is lower than the normal conductance at times ta1 and tb1. As a result, the sudden noise pulse np generated at the node NO shown in FIG. 4(d) is sufficiently attenuated and the node voltage V1 shown in FIG. 2(f) is transmitted to the node N1. tb, the voltage V2 at the output node N2 of the level conversion circuit 10 has a normal waveform as shown in FIG. 2(g), and therefore the integrated circuit 20 does not malfunction due to power supply noise.

As another embodiment, the variable conductance transistor nDO shown in FIG. 1 may be a p-type MOS transistor, and a gate voltage having the opposite phase to the gate voltage φ may be input. Also, instead of depression, enhancement M
An OS transistor may also be used. Furthermore, a resistor may be inserted in parallel or in series between the drain and source of the transistor. In addition to this, a similar effect can be obtained in a level conversion circuit configured with a TTL level logic circuit instead of the front-stage and rear-stage inverters.

0012

As explained above, the present invention inserts a variable conductance element between the output node of a front-stage logic circuit connected to an input terminal and the input node of a rear-stage logic circuit that receives and responds to the output signal. During the power supply noise period that occurs when output data is output from an integrated circuit, the output signal of the pulse generation circuit corresponding to the noise is gated to lower the conductance of the variable conductance element than usual, thereby preventing errors in the preceding stage logic circuit due to ground power supply noise. To prevent malfunction of a level conversion circuit by making it difficult to transmit an output to a subsequent logic circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram of each voltage for explaining the operation of the circuit in FIG. 1;

FIG. 3 is a circuit diagram of an example of a conventional level conversion integrated circuit.

FIG. 4 is a waveform diagram of each voltage for explaining the operation of the circuit in FIG. 3;

[Explanation of symbols]

1 Pre-stage inverter 2 Variable conductance circuit 2a Delay pulse generation circuit 3 Post-stage inverter 4 Internal circuit 5 Output buffer circuit 6 Level conversion circuit 7 Integrated circuit DI Input data DO Output data N0 to N3 0th to 3rd nodes nEO, nE1
N-type enhancement MOS transistor pEO, pE1 P-type enhancement MOS transistor nDO N-type depletion MOS transistor TI Input data terminal TO Output data terminal V0 to V2 Voltage of nodes 0 to 2 X Intermediate node φ Gate control voltage

Claims (2)

[Claims] 1. A front stage logic circuit which inputs TTL level input data of an external input terminal, a level conversion circuit which inputs the input data to a rear stage logic circuit via an intermediate node and outputs CMOS level internal data, and converts the internal data into In a level conversion integrated circuit having an internal circuit for inputting data and outputting output data from an external output terminal via an output buffer circuit, and in which the circuit receives DC voltage from the same power supply terminal and ground terminal, respectively. , a level conversion characterized in that a variable conductance circuit having a variable conductance element whose drain and source are connected and whose gate is controlled by an off control pulse with a predetermined delay time corresponding to the input data is inserted at the intermediate node. integrated circuit. 2. The variable conductance element includes an enhancement type FET whose gate receives the off control pulse, and a resistor or diode made of an impurity layer such as an FET resistor, a FET diode, or a diffusion layer, which are connected in parallel. The level conversion integrated circuit according to claim 1, characterized in that: