JPH04333115A - Information processor - Google Patents

Abstract

PURPOSE:To extremely improve the whole processing performance of a system. CONSTITUTION:A control storage 1 stores plural words of microinstructions. Each of these words consists of an arithmetic instruction field 1a which stores the arithmetic instruction information, a control information field 1b which stores the control information, and a clock control field 1c which stores the clock cycle control information. A microinstruction holding register 2 holds the arithmetic instruction information on the microinstruction during execution in an area 2a, the control information in an area 2b, and the clock cycle control information in an area 2c respectively. A clock generating part 3 generates a clock signal in response to the clock cycle control information received from the area 2c of the register 2. An arithmetic circuit 4 performs the addition or the multiplication of the data received from the accumulators 5 and 6 by using the clock signal generated from the part 3. Then the result of addition or multiplication is stored in the accumulator 5 based on the arithmetic instruction information on the microinstruction.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to a clock cycle control method for an information processing apparatus controlled by microinstructions.

0002

[Prior Art] The demand for improved computer performance is increasing year by year, and as a hardware approach to improving performance, technology development such as higher integration, higher speed, and higher density packaging has been developed to speed up the system clock cycle. is in progress. However, with conventional technology, the target system clock cycle must be set late due to severe circuit configuration constraints on delay time, or systems must change the circuit configuration to operate with multiple clock cycles. There were many.

[0003] In such conventional information processing devices, for some circuits whose delay time is severely restricted, the clock cycle of the entire system is slowed down or the circuit configuration is modified to operate with multiple clock cycles. This may lead to a decrease in the performance of the entire system.

For example, when building a circuit that has multiple functions and is switched between function modes in order to reduce the amount of hardware, the circuit delay time is severely restricted only in a certain function mode, and the target There will be cases where it will not fit within the system clock cycle. In addition, in such a case, if the device is configured to operate at multiple clock cycles, control becomes complicated. Furthermore, if the circuit is frequently used and has an impact on performance, a configuration in which it operates with multiple clock cycles has the disadvantage that the performance will be significantly degraded.

[0005]

OBJECTS OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the conventional system, and an object of the present invention is to provide an information processing apparatus that can significantly improve the processing performance of the entire system.

[0006]

SUMMARY OF THE INVENTION An information processing apparatus according to the present invention includes a storage means for storing a plurality of microinstructions, each of which is provided with clock information specifying a cycle of a system clock at the time of instruction execution, and a plurality of microinstructions read from the storage means. The present invention is characterized by comprising a clock generating means for generating a system clock having a cycle according to the clock information when executing a microinstruction.

[0007]

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a control storage device 1 stores a plurality of words of 2-byte microinstructions in which processing contents are programmed in advance. Here, the microinstruction consists of a high-order 4-bit operation instruction field 1a that stores operation instruction information that instructs execution of addition or multiplication, a 10-bit control information field 1b that stores other control information, and a clock period. It consists of a clock control field 1c of lower two bits that stores clock cycle control information for control.

Microinstruction holding register 2 stores microinstructions being executed. That is, the microinstruction holding register 2 holds the microinstruction 101 from the control storage device 1.
calculation instruction information in area 2a, control information in area 2b,
Clock cycle control information is stored in each area 2c.

The clock generator 3 receives the clock control signal 1 sent from the area 2c of the microinstruction holding register 2.
03, that is, generates a clock signal according to the clock period control information stored in the clock control field 1c of the control storage device 1, and uses the clock signal as the system clock 104 to operate the accumulators 5 and 6 and each circuit in the system (not shown). ).

The addition circuit 41 of the arithmetic circuit 4 adds data 107 and 108 from the accumulators 5 and 6 that store values to be added or multiplied, and the addition result 109 is
is output to the selector 43. The multiplication circuit 42 multiplies the data 107 and 108 from the accumulators 5 and 6,
The multiplication result 110 is output to the selector 43. The selector 43 selects the addition result 109 from the adder circuit 41 according to the calculation control signal 102 sent from the area 2a of the microinstruction holding register 2, that is, the calculation instruction information stored in the calculation instruction field 1a of the control storage device 1. One of the multiplication results 110 1 of the multiplication circuit 42 is selected and the selected data 111 2 is output to the accumulator 5.

Accumulator 5 stores data 105 or selection data 111 from selector 43 and outputs data 107 to addition circuit 41 and multiplication circuit 42. Accumulator 6 stores data 106 2 and outputs data 108 2 to addition circuit 41 and multiplication circuit 42 . Here, the accumulators 5 and 6 are the clock generator 3.
It is operated by the system clock 104 from .

FIG. 2 is a block diagram showing the configuration of the clock generator 3 of FIG. 1. In the figure, an oscillator 31 of a clock generator 3 outputs a basic clock 131 faster than the system clock period of the system to a counter 32 and a JK clock.
Output to flip-flop 36. The counter 32 counts the basic clock 131 from the oscillator 31 and outputs the count value 132 to comparators 33 and 34, respectively. Further, the counter 32 receives the selection result 1 from the selector 35.
When 35 becomes "1", the count value is cleared in order to synchronize the clocks.

In this embodiment, when the basic clock 131 from the oscillator 31 is set to 10 nsec per one machine cycle (hereinafter referred to as 1T), the clock generator 3
1T of the system clock period output from 100n
sec and 120nsec, the comparator 33
Then, the count value 132 from the counter 32 is compared with "5", and the comparator 34 compares the count value 132 from the counter 32 with "6". Comparator 3
3 and 34 respectively detect a match, the comparison result 133,
134, "1" is output to the selector 35. That is, the comparator 33 outputs "1" to the selector 35 every 50 nsec, and the comparator 34 outputs "1" every 60 nsec.
is output to the selector 35.

The selector 35 receives the clock control signal 103 sent from the area 2c of the microinstruction holding register 2.
Comparison results 133 from comparators 33 and 34 according to
Select one of 134 and press counter 32 and JK.
Output to flip-flop 36. That is, if the clock control signal 103 from the area 2c of the microinstruction holding register 2 is "01", the selector 35 selects the comparator 3.
The comparison result 133 from 3 is selected and output to the counter 32 and the JK flip-flop 36. Further, if the clock control signal 103 from the area 2c of the microinstruction holding register 2 is "10", the selector 35 selects the comparison result 134 from the comparator 34 and outputs it to the counter 32 and the JK flip-flop 36.

The JK flip-flop 36 is the oscillator 3
The basic clock 131 from 1 is input to the clock input terminal C, and the selection result 135 from the selector 35 is input to the input terminals J and K, respectively. JK flip flop 3
6 does not change the internal value if the selection result 135 from the selector 35 is "0", and inverts the internal value if the selection result 135 from the selector 35 is "1", and outputs the value to the output terminal. It is output from O as a system clock 104 to accumulators 5 and 6 and each circuit in the system.

Therefore, when the clock control signal 103 from the area 2c of the microinstruction holding register 2 is "01", the JK flip-flop 36 outputs "1" from the selector 35 at intervals of 50 nsec to the input terminal J,
Since the system clock 104 is inputted to the output terminal O, the system clock 104 with 1T of 100 nsec is output from the output terminal O. Also, J
K flip-flop 36 is microinstruction holding register 2
The clock control signal 103 from the area 2c is “10”
If so, "1" output from the selector 35 at 60 nsec intervals is input to the input terminals J and K, so that the system clock 104 with 1T of 120 nsec is output from the output terminal O. As a result, if the clock cycle control information stored in the clock control field 1c of the control storage device 1 is "01", the clock generation unit 3 outputs 1T.
outputs a system clock 104 of 100 nsec, and if the clock cycle control information is “10”, 1T is 12
A system clock 104 of 0 nsec is output.

The arithmetic processing operation of one embodiment of the present invention will be explained using FIGS. 1 and 2. In the arithmetic circuit 4, the system clock 104 is output from the clock generator 3.
By receiving , the values of the accumulators 5 and 6 are outputted to the adder circuit 41 and the multiplier circuit 42, respectively, and the adder circuit 41 or the multiplier circuit 42 performs addition or multiplication. After this, the calculation processing time until the calculation result is stored in the accumulator 5 again via the selector 43 is 100 nsec in the case of addition processing and 120 nsec in the case of multiplication processing. Furthermore, if the operation instruction information in the operation instruction field 1a of the microinstruction is information indicating addition, "0" is preset in the clock control field 1c as clock period control information by assembling processing.
Furthermore, if the operation instruction information in the operation instruction field 1a of the microinstruction is information indicating multiplication, "10" is set in advance as clock period control information in the clock control field 1c by assembling processing.
is set.

The control memory 1 has a given address 10
The microinstruction 101 corresponding to 0 is output to the microinstruction holding register 2. Microinstruction holding register 2
holds microinstructions 101 from control store 1. That is, the microinstruction holding register 2 stores microinstruction operation instruction information in area 2a and control information in area 2b.
In addition, clock cycle control information is held in area 2c. The calculation instruction information held in the area 2a is the calculation control signal 10.
The clock cycle control information held in the area 2c is output as a clock control signal 103 to the clock generating section 3.

Here, if the calculation instruction information is information indicating addition, "01" is outputted to the clock generating section 3 as the clock control signal 103. When “01” is input as the clock control signal 103 in the clock generator 3, the system clock 104 with 1T of 100 nsec is generated.
is output to accumulators 5 and 6. At the same time, data 107 and 108 output from accumulators 5 and 6, respectively.
is processed by the calculation circuit 4 based on the calculation control signal 10.
2, the addition result is stored in the accumulator 5.

On the other hand, if the operation instruction information is information indicating multiplication, "10" is outputted to the clock generating section 3 as the clock control signal 103. When “10” is input as the clock control signal 103 in the clock generator 3,
A system clock 104 of 1T of 120 nsec is output to the accumulators 5 and 6. At the same time, data 107 and 108 are output from accumulators 5 and 6, respectively.
is processed by the calculation circuit 4 based on the calculation control signal 10.
2, the multiplication result is stored in the accumulator 5.

That is, clock cycle control information for controlling the system clock cycle is provided as part of each microinstruction, and the cycle of the system clock 104 generated by the clock generator 3 is controlled in accordance with this clock cycle control information. As a result, even when the same arithmetic circuit as described above performs processes with different circuit delay times according to the contents indicated by microinstructions, it is possible to send out a system clock that matches the circuit delay time of those processes. .

FIG. 3 is a time chart showing the operation of one embodiment of the present invention. The figure shows the processing time when 10 additions and 2 multiplications are performed according to an embodiment of the present invention, and the processing time when 10 additions and 2 multiplications are performed according to the conventional technology. There is.

When 10 additions and 2 multiplications are performed according to an embodiment of the present invention, 1T of the system clock 104 is 100 nsec when performing addition, and 1T of system clock 104 is 12 ns when performing multiplication.
Since it is 0nsec, the processing time for addition is 1000n
sec, the processing time for multiplication is 240 ns, and the total processing time is 1240 ns.

On the other hand, according to the prior art, the addition 10
1T of the system clock 104 is 120 when performing addition and multiplication.
nsec, the total processing time for addition and multiplication is 1440 nsec. Therefore, one embodiment of the present invention can perform processing 200 nsec faster than the conventional example. That is, addition processing 1 according to an embodiment of the present invention
The processing can be performed 20 nsec faster than the addition processing according to the conventional technology. Therefore, the processing performance of the entire system can be significantly improved.

As described above, by providing the clock control field 1c storing clock cycle control information for controlling the system clock cycle as a part of each microinstruction, it is possible to solve the problem due to strict circuit configuration constraints on delay time. Fine-grained clock control corresponding to the circuit delay time of the process instructed by the microinstruction can be performed without lowering the system clock throughout the entire process. Therefore, the processing performance of the entire system can be significantly improved.

[0027]

As explained above, according to the present invention, clock information specifying the cycle of the system clock at the time of execution of each instruction is given to each microinstruction in advance, By generating a system clock with a cycle that corresponds to the provided clock information, there is an effect that the processing performance of the entire system can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a clock generation section in FIG. 1;

FIG. 3 is a time chart showing the operation of an embodiment of the present invention.

[Explanation of symbols]

1 Control storage device 3 Clock generation section 4 Arithmetic circuit 5, 6 Accumulator 31 Oscillator 32 Counter 33, 34 Comparator 35, 43 Selector 36 JK flip flop 41 Adder circuit 42 Multiplication circuit

Claims (1)

[Claims] 1. Storage means for storing a plurality of microinstructions, each of which is provided with clock information specifying a cycle of a system clock at the time of instruction execution; 1. An information processing device comprising: clock generation means for generating a system clock having a cycle according to clock information.