JPH04332873A - Digital oscilloscope - Google Patents

Abstract

PURPOSE:To achieve a digital oscilloscope which allows a result of waveform observation to be displayed on a general television etc., video image recording to be made, and a result of waveform observation for a long time to be memorized and observed. CONSTITUTION:A digital oscilloscope is provided with an A/D conversion means 1, a display data memory means 2, a waveform display circuit 3, a built-in display means 4, namely a normal CRT, and a circuit 5 for converting the CRT output to TV output. A result of waveform observation can be displayed on a general television etc.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display on a digital oscilloscope, and more particularly to a digital oscilloscope having a function of converting the display screen into a video signal of standard television signal standard and outputting the same.

0002

2. Description of the Related Art Conventional digital oscilloscopes display waveform observation results on their built-in CRT, and cannot be displayed on an external standard television or the like. For example, suppose you want to observe a waveform over a long period of time using such a digital oscilloscope and then reproduce it later.

0003

[Problems to be Solved by the Invention] In order to realize the above-mentioned long memory, a large capacity memory is required, which is difficult to realize. . The present invention was made in order to solve these problems, and it provides a means for displaying the waveform observation results on a standard television or the like in a digital oscilloscope, etc., and enables video recording, etc., and can be used for long periods of time. The purpose is to realize a digital oscilloscope that can store and observe the results of waveform observation.

0004

[Means for Solving the Problems] The present invention provides an A/D conversion circuit that converts an analog input signal into a digital signal;
display data storage means for storing the digital signal input from the A/D conversion means; a waveform display circuit for converting the digital signal input from the display data storage means into a signal for display; and a display data storage means for storing the digital signal input from the display data storage means; The present invention is characterized in that it is equipped with a built-in display means for displaying the signal input from the waveform display circuit, and a television output conversion circuit that converts the signal input from the waveform display circuit into a video signal of standard television signal standard and outputs it, so that waveform observation can be performed on a general television. It is a digital oscilloscope.

[0005]

[Operation] When outputting data for each screen to be displayed on a CRT with a built-in digital oscilloscope to a TV, etc., by using multiple memories in sequence, the built-in CRT
The display data given at the timing (frame cycle) to be displayed on the RT is output to the TV etc. at the timing (frame cycle for TV) to be displayed on the TV etc.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a basic configuration diagram of the present invention.

Reference numeral 1 denotes an A/D conversion means which inputs an analog input signal and converts it into a digital signal. 2 is a display data storage means that stores a digital signal converted by an A/D conversion circuit. 3 is a waveform display circuit that converts the digital signal output from the display data storage means 2 into a signal that can be displayed in waveform. 4 is a built-in display means that displays the signal input from the waveform display circuit 3. Reference numeral 5 denotes a television output conversion circuit that converts the signal input from the waveform display circuit 3 into a signal that can be output to a general television. In such a configuration, an input signal is converted into a digital signal by the A/D conversion circuit 1. The data of this digital signal is stored in the display data storage means 2,
A CPU, which controls the entire operation of the digital oscilloscope of the present invention, reads out the data, performs arithmetic processing, and then inputs the data to the waveform display circuit 3. The waveform display circuit 3 converts the data into a serial signal or the like that can be displayed on the built-in display means 4. A built-in display means 4, which is built in the digital oscilloscope body, displays display data using signals from the waveform display circuit 3. Furthermore, the television output conversion circuit 5 is responsible for the feature of the present invention and converts the output signal s from the waveform display circuit into a signal that can be output to a general television.

FIG. 2 is a concrete block diagram of one embodiment of the present invention, which explains the television output conversion circuit 5 in FIG. 1 in detail. In the figure, reference numerals 10 and 11 denote data conversion circuits, which convert the video serial data signal s inputted into the built-in display means 4 in FIG. , 24. The 8-bit data read from the conversion memories 17 to 19 is sent to the data conversion circuit 1 via buffers 26, 28, and 30.
1, it is converted into a serial signal and output as a serial television signal from the terminal Vout. 12 and 13 are address counters, and 8 is a display clock from the terminal Coin (a clock indicating the time to display one point on the built-in display means 4).
The address counter 12 counts pulses at the timing of frequency division, and the write address is set in the buffers 21, 23, 2.
5 to the conversion memories 17 to 19. The address counter 13 counts pulses at the timing of frequency division by eight of the television signal display clock from the terminal Cvin, and outputs read addresses to the conversion memories 17 to 19 via buffers 27, 29, and 31. Reference numeral 14 denotes a write signal generation circuit which inputs the frame signal (pulse indicating the time for displaying one screen of the built-in display means 4) of the built-in display means 4 inputted from the terminal Foin, and generates the write signal w1 of the conversion memories 17 to 19. , w2, w3 are output to buffers 20-25 and conversion memories 17-19. 15 is a read signal generation circuit which inputs the signal from the timing adjustment circuit 16;
Read signals r1, r2, r3 from conversion memories 17-19 are output to buffers 26-31 and conversion memories 17-19. The timing adjustment circuit 16 includes the write signal generation circuit 1
4, the TV frame signal (pulse indicating the time for displaying one TV screen) input from the terminal Fvin, and the TV signal display clock from the terminal Cvin are input, and the frame signal of the built-in display means 4 is inputted. A signal for adjusting the deviation between the signal and the television frame signal is output to the read signal generation circuit 15, and a signal used by the read address counter 13 and the data conversion circuit 11 is output.

Display data is sent from the waveform display circuit 3 as a serial signal one screen at a time for each period of the frame signal. Then, display data is output to a general television one screen at a time for each period of the television frame signal. However, since the frame signal and the TV frame signal are not synchronized, the display data is sequentially written into conversion memories 17 to 19 using the frame signal, and the display data is written into conversion memory 1 using the TV frame signal.
If display data is read out sequentially from 7 to 19, writing and reading will be performed simultaneously in the same memory. In order to avoid this, the timing adjustment circuit 16 uses the signal from the write signal generation circuit 14, the TV frame signal (pulse indicating the time to display one TV screen) input from the terminal Fvin, and the signal from the terminal Cvin. inputs the television signal display clock of the built-in display means 4 and outputs a signal for adjusting the deviation between the frame signal of the built-in display means 4 and the television frame signal to the readout signal generation circuit 15, which is used by the readout address counter 13 and the data conversion circuit 11. Output a signal. Based on this signal, read signal generation circuit 15 outputs read signals r1, r2, r3 to buffers 26-31 and conversion memories 17-19 at timings where writing and reading do not overlap. The buffers 20 to 31 receive write signals w1, w2, w3 and read signals r1, r2,
Based on r3, addresses input to the memories 17 to 19 are controlled and data writing/reading is controlled.

The operation of such a configuration will be explained with reference to the time chart shown in FIG. In this embodiment, since the display data is sequentially stored in three memories, the write signals w1, w
2, w3 is the frame signal divided by three. When each signal is at L level, operation is permitted. for example,
When the write signal w1 is in the L level state, the conversion memory 17 enters the write state, and 8-bit display data via the buffer 20 is written to the write address from the address counter 13 input via the buffer 21. Further, the frequency of the television frame signal is divided by three to obtain a readout signal. When the read signal r1 is in the L level state, the conversion memory 17 is in the read state, and the buffer 27 is in the read state.
8-bit display data is read out from the address counter 14 via the buffer 26, converted into a serial signal by the data conversion circuit 11, and outputted as a television signal from the terminal Vout. .

However, if we focus on r1', which is just the frequency of the TV frame signal divided by 3, as shown in FIG. It is understood that the readings will occur simultaneously. At this time (from t1 to t2), the timing adjustment circuit 16
period), all memories are prohibited from being read, and from the rising edge of the next TV frame signal, the conversion memory 17,
A signal is outputted to a read signal generation circuit or the like so that reading is performed in order of 18 and 19. In this way, display data is output to the television using a frame signal (for example, 59.97 Hz) and a television frame signal (for example, 60 Hz in the NTSC system) having different periods.

0012

[Effects of the Invention] According to the present invention, it has become possible to output the contents displayed on a CRT with a built-in digital oscilloscope to a television or the like.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a time chart showing the operation of an embodiment of the present invention.

[Explanation of symbols]

1... A/D conversion means, 2...Display data storage means, 3... Waveform display circuit, 4...Built-in display means, 5...TV output conversion circuit, 10, 11...data conversion circuit, 12, 13...address counter, 14, 15...signal generation circuit, 16...timing adjustment circuit, 17-19...conversion memory, 20-31...buffer.

Claims (1)

[Claims] 1. An A/D conversion circuit for converting an analog input signal into a digital signal; display data storage means for storing the digital signal inputted from the A/D conversion means; and input from the display data storage means. a waveform display circuit for converting the digital signal into a signal for display; a built-in display means for displaying the signal input from the waveform display circuit; and a built-in display means for displaying the signal input from the waveform display circuit; A digital oscilloscope that is equipped with a television output conversion circuit that converts and outputs, and is capable of observing waveforms on a general television.