JPH04329671A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a method for manufacturing a semiconductor device, which can reduce a contact resistance by increasing an electric contact area of a gate electrode with a diffused layer in a static RAM. CONSTITUTION:A conductive film 5 made of metal such as tungsten, titanium, etc., or polycrystalline silicon, a single crystalline silicon, etc., is selectively grown in a buried contact 4 opened at a gate oxide film 3 of a semiconductor substrate 1, a gate electrode 6 is formed on the film 5, an impurity is implanted to the substrate 1 through the electrode 6 and the film 5 to form a diffused layer 8. Thus, the layer 8 is electrically connected to the electrode 6 in the entire area of the contact 4 by the film 5.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a static type memory cell that can be written to and read at any time, and more particularly to a method for manufacturing a buried contact portion connecting a gate electrode and a diffusion layer in this type of semiconductor device.

0002

[Prior Art] Conventional static RAM (Random
MOSF that constitutes Access Memory
FIG. 3 shows the manufacturing process of a buried contact structure that electrically connects the gate electrode of the ET and the diffusion layer. First, Figure 3 (
As shown in a), on one main surface of the P-type semiconductor substrate 1, about 4
An element isolation oxide film 2 with a thickness of 000 Å to 6000 Å is formed, and a gate oxide film 3 with a thickness of about 200 Å is formed in the element region. Next, the photoresist is patterned, and using a technique such as wet etching, the gate oxide film 3 is selectively removed as shown in FIG. 3(b), and a buried contact 4 is opened.

Next, as shown in FIG. 3(c), phosphorus-containing polycrystalline silicon is grown, and the polycrystalline silicon is selectively removed by anisotropic etching using a patterned photoresist as a mask. Electrode 6 is formed. Subsequently, using this gate electrode 6 as a mask, ions of, for example, arsenic are implanted, and heat treatment is applied for activation. Through this heat treatment, the n-type diffusion layer 8 is formed by the ion-implanted arsenic and the phosphorus diffused into the semiconductor substrate 1 from the gate electrode 6, and electrical connection between the gate electrode 6 and the n-type diffusion layer 8 is achieved.

0004

However, in this manufacturing method, after opening the buried contact 4, the polycrystalline silicon is selectively removed to form the gate electrode 6; For accuracy reasons, the area where the gate electrode 6 contacts the diffusion layer 8 is only a part of the entire area of the buried contact 4. Therefore, as semiconductor devices have become highly integrated in recent years, device dimensions have been reduced and buried contacts 4 and gate electrodes 6 have become finer. There is a problem in that the contact area is further reduced and the contact resistance is increased, making it difficult to operate the circuit normally. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that enables reduction in contact resistance by increasing the contact area between a gate electrode and a diffusion layer in a buried contact.

[0005]

[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention is to fill a buried contact opened in a gate oxide film of a semiconductor substrate with metal such as tungsten or titanium, polycrystalline silicon, single crystal silicon, etc. The method includes the steps of selectively growing a conductive film, forming a gate electrode on the conductive film, and introducing impurities into the semiconductor substrate through the gate electrode and the conductive film to form a diffusion layer. Furthermore, after forming the gate electrode in contact with the buried contact, a conductive film may be selectively grown on the surface of the semiconductor substrate within the buried contact and on the surface of the gate electrode, respectively.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIGS. 1(a) to 1(e) are longitudinal cross-sections showing a first embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG. 1(a), an element isolation oxide film 2 is formed on one main surface of a P-type semiconductor substrate 1.
A gate oxide film 3 is formed to a thickness of about 6000 Å and a gate oxide film 3 is formed to a thickness of about 200 Å in the element region. Next, Figure 1
As shown in FIG. 3B, a part of the gate oxide film 3 is etched away using the patterned photoresist as a mask, a buried contact 4 is opened, and the surface of the semiconductor substrate 1 is exposed.

Next, after removing the photoresist, as shown in FIG. 1(c), approximately tungsten 5 is deposited on the surface of the semiconductor substrate 1 of the buried contact 4 by a metal selective growth method.
It is grown to a thickness of about 200 Å. Next, as shown in FIG. 1(d), a phosphorus-containing polycrystalline silicon film with a thickness of approximately 3000
The gate electrode 6 is formed by etching using the patterned photoresist as a mask. Next, using the gate electrode 6 as a mask, for example, phosphorus is accelerated at 1E13 cm-2 with an energy of 30 KeV.
Ions are implanted into the semiconductor substrate 1 at a dose of .

Next, as shown in FIG. 1(e), CVD
A silicon oxide film having a thickness of about 2000 Å is formed by the method, and is etched by anisotropic dry etching to form sidewalls 7 on the sidewalls of the gate electrode 6. Then, using the gate electrode 6 and sidewall 7 as a mask, for example, arsenic is applied at an acceleration energy of 1E16c at 50KeV.
Ions are implanted into the semiconductor substrate 1 at a dose of m-2, and heat treatment is applied to activate the implanted ions. As a result of this heat treatment, source/drain regions of an LDD structure are formed in the element region (not shown), phosphorus is diffused from the gate electrode 6 into the semiconductor substrate 1 via the tungsten 5 in the buried contact 4, and ion-implanted phosphorus is diffused into the semiconductor substrate 1 through the tungsten 5. , an n-type diffusion layer 8 is formed by lateral diffusion of arsenic, and electrical connection between the gate electrode 6 and the n-type diffusion layer 8 at the buried contact 4 is achieved.

Therefore, according to this manufacturing method, the highly conductive tungsten 5 is formed over the entire area of the buried contact 4 by the selective growth method, so that the tungsten 5 is in contact with the diffusion layer 8 over a wide area. In addition, since the gate electrode 6 is electrically connected to the tungsten 5, the contact resistance can be reduced compared to the conventional case. In addition, by the heat treatment for activating the implanted ions, both the gate electrode 6 and the semiconductor substrate 1 in contact with the tungsten 5 are silicided, and the gate electrode 6 and the semiconductor substrate 1 are metallurgically integrated.
This also allows the contact resistance to be further reduced. Note that if the device does not have an LDD structure, the formation of the sidewall 7 and the two ion implantation steps described above are not necessary, and it is sufficient to perform ion implantation once to obtain the required impurity concentration.

FIGS. 2(a) to 2(e) are longitudinal sectional views showing the manufacturing process of a second embodiment of the present invention. First, Figure 2(a)
As shown in the first embodiment, an element isolation oxide film 2, a gate oxide film 3,
Embedded contacts 4 are sequentially formed. Next, as shown in FIG. 2(b), here, a phosphorus-containing polycrystalline silicon film is first formed and selectively etched to form a gate electrode 6. Using this gate electrode 6 as a mask, for example, Phosphorus is implanted at an acceleration energy of 30 KeV and a dose of 1E13 cm-2.

Next, as shown in FIG. 2(c), about 200
A silicon oxide film with a thickness of 0 Å is formed by the CVD method, and sidewalls 7 are formed on the side walls of the gate electrode 6 by anisotropic etching. Then, for example, arsenic is etched with an acceleration energy of 50 KeV and a dose of 1E16 cm-2. Implant ions. Thereafter, as shown in FIG. 2(d), a silicon oxide film 9 of about 200 Å is grown by the CVD method, a photoresist 10 is formed on it in the same pattern as the buried contact 4, and etching is performed using this as a mask. As a result, the silicon oxide film 9 in the buried contact portion is removed.

Thereafter, after removing the photoresist 10, as shown in FIG. 2(e), tungsten 5 is grown on the surface of the gate electrode 6 exposed to the buried contact 4 and the surface of the semiconductor substrate 1 by a metal selective growth method. It is selectively grown to a thickness of about 200 Å, and then heat treated to activate the ion-implanted impurities. Through this heat treatment, phosphorus is diffused from the gate electrode 6 to the semiconductor substrate 1 to form an n-type diffusion layer 8.
Electrical connection using the buried contact 4 is completed. In this embodiment as well, since electrical connection is also made by the selectively grown tungsten 5 in the buried contact 4, the substantial contact area between the diffusion layer 8 and the gate electrode 6 is increased.
Contact resistance can be reduced compared to conventional methods. Incidentally, in the present invention, instead of tungsten in each of the above embodiments, other conductive materials,
It is also possible to use metals such as titanium or polycrystalline silicon.

[0013]

[Effects of the Invention] As explained above, the present invention includes a step of selectively forming a conductive film within a buried contact, or a step of selectively forming a conductive film on each of a gate electrode and a buried contact. Therefore, the diffusion layer and the gate electrode are electrically connected by the conductive film over the entire area of the buried contact, which has the effect of increasing the substantial contact area between the two and reducing the contact resistance.

[Brief explanation of drawings]

FIGS. 1A to 1E are cross-sectional views showing a first embodiment of the present invention in the order of manufacturing steps.

FIGS. 2(a) to 2(e) are cross-sectional views showing a second embodiment of the present invention in the order of manufacturing steps.

FIGS. 3A to 3C are cross-sectional views showing a conventional manufacturing method in the order of steps.

[Explanation of symbols]

1 Semiconductor substrate 2 Element isolation oxide film 3 Gate oxide film 4 Embedded contact 5 Tungsten 6 Gate electrode

Claims (2)

[Claims] 1. A step of forming a gate oxide film on one main surface of a semiconductor substrate in which an element isolation region is formed, and a step of selectively removing the gate oxide film to open a buried contact. A process of selectively growing a conductive film made of a metal such as tungsten or titanium, polycrystalline silicon, single crystal silicon, etc. on the surface of the semiconductor substrate exposed in the buried contact, and growing silicon and patterning it to form a gate electrode, at least a portion of which is located over the buried contact; and introducing impurities into the semiconductor substrate through the gate electrode and the conductive film. A method for manufacturing a semiconductor device, comprising the step of applying heat treatment to form a diffusion layer in a region including a buried contact. 2. Forming a gate oxide film on one main surface of the semiconductor substrate on which the element isolation region is formed; selectively removing the gate oxide film to open a buried contact; a step of growing polycrystalline silicon and patterning it to form a gate electrode, at least a portion of which is in contact with the buried contact; and forming an oxide film over the entire surface and then forming an area corresponding to the buried contact. a conductive film made of metal such as tungsten, titanium, polycrystalline silicon, single crystal silicon, etc. on the surface of the semiconductor substrate exposed in the buried contact and the surface of the gate electrode, respectively. and a step of introducing an impurity into the semiconductor substrate through the gate electrode and the conductive film and applying heat treatment to form a diffusion layer in a region including the buried contact. A method for manufacturing a semiconductor device.