JPH04328962A - Picture quality improving device - Google Patents

Abstract

PURPOSE:To implement edge emphasis in a natural form without giving a sense of disorder to a viewer and to facilitate the digital circuit processing by adding properly a waveform step to a midpoint of a slope of an input signal with respect to the picture quality improving device proper to a video equipment and various picture processing units. CONSTITUTION:A sampling frequency of an input signal S1 is shifted to a higher frequency by an interpolation processing by an interpolation circuit 1 to form a signal S2. The signal S2, an output signal S3 of a delay circuit 2 and an output signal S4 of the delay circuit 3 are fed to a signal selection circuit 8. A control signal Sc is obtained from the signals S2, S3, S4 at subtractors 4-6 and a control signal generating circuit 7. The signal selection circuit 8 selectively outputs one of the supplied three signals S2, S3, S4 in response to the control signal Sc and obtains an output signal S0 subject to edge emphasis.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention is applicable to television (TV).
) The present invention relates to an image quality improvement device suitable for various video devices such as television receivers, video tape recorders (VTRs), and printers, and various image processing devices that handle image data. and,
The purpose of this invention is to provide an image quality improvement device that can perform edge enhancement in a natural manner without causing any discomfort to viewers, improve the sharpness and resolution of reproduced images, and is suitable for digital circuits. There is.

0002

[Prior Art] Conventionally, in contour correction used to improve image quality, contour correction components are obtained by quadratic differential processing.
An appropriate amount of this correction component was added to the original signal. In this method, the second-order differential waveform, which is the contour correction component, has a peak far outside the midpoint of the waveform changing part (edge part) of the original signal. Therefore, if this second-order differential waveform is added to the original signal, preshoot or overshoot may occur, resulting in unnatural contour correction such as white and black borders on the edges of the reproduced image. was there.

0003

[Problems to be Solved by the Invention] The problem to be solved by the present invention is to prevent preshoot and overflow by adding a waveform step to the midpoint position of the waveform change part (edge part) of the original signal. In order to create an image quality improvement device that can prevent unnatural contour correction caused by shots, improve sharpness and resolution in a natural manner without giving viewers a sense of discomfort, and is suitable for digital circuitization. The point is what measures should be taken. Furthermore, the problem to be solved by the present invention is to determine what means can be used to add sufficient out-of-band frequency components to the input signal to obtain a large edge enhancement effect. It's all about whether it's good or not.

0004

[Means for Solving the Problems] Therefore, in order to solve the above problems, the present invention provides the following features for a sampled input signal:
an interpolation circuit that generates an interpolation signal with a cycle shorter than the sampling cycle of the input signal by interpolation processing; and a second signal that is the first signal that is the interpolation signal delayed by a predetermined time. a delay circuit that outputs a third signal obtained by delaying the second signal by the predetermined time; a control circuit that generates a control signal based on the first signal; A third signal and the control signal are supplied to the first and second signals in accordance with the control signal so as to obtain an output signal with a waveform step added to the midpoint position of the waveform changing part of the input signal. , and a signal selection circuit that selects and outputs one of the third signals.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment of an image quality improving apparatus according to the present invention. 2 is a diagram showing a specific configuration example of the interpolation circuit shown in FIG. 1, FIG. 3 is a diagram for explaining each circuit in the interpolation circuit, and FIG. 4 is a diagram showing the control signal shown in FIG. 1. 5 is a diagram illustrating an example of the use of the present invention, and FIGS. 6, 7, 9, and 10 are diagrams showing specific configuration examples of the formation circuit and signal selection circuit. FIG. 8 is an explanatory diagram of the operation of the example shown in FIG. 5, and FIGS. 11 to 14 are diagrams showing main parts of the second to fifth embodiments, respectively. In addition, in FIGS. 6 to 8 and FIG. 10, the steps in the waveform slope portion are exaggerated to make the explanation easier to understand, and also to make it easier to understand the relative level changes and position changes. Therefore, the waveform is expressed as an impulse-like sample value. Further, even when a digital circuit is cited as a specific example of a circuit, the signal waveform may be shown as an analog value in order to make the explanation of its operation easier to understand. In FIG. 1, 1 is an interpolation circuit, 2 and 3 are delay circuits having the same delay time, 4 to 6 are subtracters, 7 is a control signal forming circuit, and 8 is a signal selection circuit. A circuit consisting of the delay circuit 2 to signal selection circuit 8 is referred to as a first edge emphasis processing circuit. For convenience of explanation, signal delays due to the processing time of each circuit itself, and delay circuits and the like that are normally used simply to correct the delays will be omitted. The input signals handled by this image quality improvement device include various video signals, brightness signals, RGB
Signals etc. can be considered. First, a case will be described in which the input signal S1 coming from the line L1 is a signal with a bar pulse waveform as shown in FIG. 7(a). This signal is an example of the waveform of a luminance signal of a TV video signal, and is a signal whose frequency components are band-limited to an upper limit frequency of 4 MHz, sampled (sampling period T), and discretized. The sampling period T is given by the following formula,

[0006]

[Math 1]

[0007] The value of this sampling period T is a value set based on the sampling frequency fs (fs = 4fsc) that is normally used when quantizing a TV video signal and processing the signal in a digital system. Input signal S1 is input to interpolation circuit 1
supplied to A specific example of the configuration of the interpolation circuit 1 is shown in FIG.
) and (b). First, the interpolation circuit 1 shown in FIG.
I will explain about it. The delay time of the delay circuits 2-1 and 2-2 is the same as the sampling period T. Delay circuit 2-1
, 2-2 act as a latch circuit for one clock. The input signal S1 coming from the line L1 is transmitted to the delay circuit 2-1.
The signal is delayed by the time T, and the signal is further delayed by the time T by the delay circuit 2-2. Next mixer 2-
3 mixes the input signal S1 and each output signal of the delay circuits 2-1 and 2-2 at a predetermined ratio. If the sample values of the input signal S1 and the output signals of the delay circuits 2-1 and 2-2 at any time are respectively x1, x2, and x3, the output sample value y of the mixer 2-3 is as follows. The formula becomes

[0008]

[Math 2]

[0009]

[Math 3]

A specific example of the configuration of the mixer 2-3 is shown in FIG.
). Blocks 3-1 to 3-3 are amplifiers (data converters) that provide mixing ratios k1, k2, and k3, respectively, and can be realized by a table lookup method using a ROM or the like. Sample values x1, x2, supplied to each input terminal
After x3 is multiplied by k1, k2, and k3, respectively, it is added to the combiner of block 3-4, and the resultant summation is performed to obtain the output sample value y. FIG. 6(a) shows sample values x1, x2, x
3 on the real time axis, and is drawn based on the position of sample value x2. The mixer 2-3 is shown in FIG.
As shown in b), the function is to obtain a value y1 at an intermediate position between sample values x1 and x2 using sample values x1, x2, and x3. A value y at an arbitrary position between sample values x1 and x2 is obtained as shown in the following equation by quadratic curve approximation based on the values of sample values x1, x2, x3 and the relative positional relationship.

[0011]

[Math 4]

When formula (4) is summarized as in formula (2) for sample values x1, x2, x3, each mixing ratio k1,
k2 and k3 are as shown in the following equation.

[0013]

[Math 5]

The value y1 at the intermediate position between the sample values x1 and x2 shown in FIG. 6(b) is obtained using the above equation (5) with p=1/2.

[0015]

[Math 6]

This value y1 is used as an interpolation value. Figure 2 (
Returning to a), the switching circuit 2-4 is supplied with the sample value x2 from the delay circuit 2-1 and is supplied with the interpolated value y1 from the mixer 2-3. Then, as shown in FIG. 6(b), the switching circuit 2-4 creates a new sample value sequence in which the interpolated value y1 is interpolated after a time T/2 from the sample value x2. A specific example of the configuration of this switching circuit 2-4 is shown in FIG. 3(e). The switching circuit 2-4 includes two switch circuits 3-20,
3-21, and a latch circuit 3-22. The switch circuits 3-20 and 3-21 are comprised of buffer circuits with control terminals as shown in FIG. 3(c). The example shown in FIG. 3(c) is an example corresponding to 8-bit data. When the control signal φn supplied to the common control terminal is 0 (Lo
w), the input data is output as is, and when the control signal φn is 1 (High), the output is in a tristate or high impedance state. The latch circuit 3-22 is 8-bit compatible as shown in FIG. 3(d), and the clock ψm applied to the ck terminal
Input data is taken in and taken out to the output side. The input side of the switch circuit 3-21 is supplied with the sample value x2, and the control terminal is supplied with a control signal φ2 having a period T for passing the sample value. The interpolated value y1 is supplied to the input side of the switch circuit 3-20, and a control signal with a period T having a phase difference of T/2 from the control signal φ2 is supplied to the control terminal for passing the interpolated value. φ1 is supplied. The input side of the latch circuit 3-22 receives the sample value x2 from the switch circuit 3-21 and the interpolated value y from the switch circuit 3-20.
1 is supplied at a period of T/2. The latch circuit 3-22 alternately latches the two signals using the clock ψ1 to obtain the output signal S2.

As described above, in the interpolation circuit 1 shown in FIG. 2(a), for the sampled values for each period T shown in FIG. 6(d), two consecutive sampled values are used. An interpolated value is obtained by approximating the following curve, and an interpolated signal S2 for every period T/2 shown in FIG. 6(e) is obtained. FIG. 9(a) is a diagram showing the relationship between the original signal (upper limit frequency fu=4 MHz) and the sampling frequency fs. FIG. 9(b) shows that the sampling frequency is equivalently shifted to the position f=2fs by the processing in the interpolation circuit 1 shown in FIG. 2(a), and the frequency difference between the sampling frequency and the original signal is It is a figure showing that it has spread twice.

FIG. 7(b) shows the output signal S2 of the interpolation circuit 1.
The waveform of is shown. The white circles are sample values that are output as is from the input signal S1, and the black circles are interpolated values. Note that due to the delay T caused by the delay circuit 2-1 in the interpolation circuit 1 and the delay T/2 caused by the latch circuit 3-22, the output signal (interpolated signal) S2 is 1. The signal is delayed by 5T. Now, returning to FIG. 1, the signal S2 is supplied to the delay circuit 2 via the line L2. The delay time Tp of the delay circuit 2 is

[0019]

[Math 7]

[0020] The value of this delay time Tp is shown in FIG.
As can be seen from b), the new sampling frequency fp after interpolation,

[0021]

[Math. 8]

This corresponds to one period of [0022]. In delay circuit 2, time T
The output signal S3 delayed by p is shown in FIG. 7(c). The next stage delay circuit 3 is a circuit with the same function as the delay circuit 2,
A signal S4 (see FIG. 7(d)) which is obtained by further delaying the supplied signal S3 by a time Tp is output. Figure 6 shows three signals S2, S3, and S4 separated by time Tp on the same signal waveform with signal S3 as the time reference (t=0).
(g). The subtracter 4 receives the output signal S2 of the interpolation circuit 1.
The output signal S3 of the delay circuit 2 is subtracted from the signal S3, and a signal S5 expressed by the following equation is output. Waveform of signal S5 (see Figure 7(e))
is a difference waveform, that is, a differential waveform.

[0023]

[Math. 9]

The subtracter 5 has the same function as the subtracter 4, and subtracts the output signal S4 of the delay circuit 3 from the output signal S3 of the delay circuit 2, and produces a signal S6 (FIG. 7(f)) shown in the following equation. reference)
Output.

[0025]

[Math. 10]

The subtracter 6 also has the same function as the subtracter 4, and outputs the output signal S6 of the subtracter 5 from the output signal S5 of the subtracter 4.
is subtracted, and a signal S7 shown in the following equation is output. The waveform of the signal S7 (see FIG. 7(g)) is a second-order difference waveform, that is, a second-order differential waveform.

[0027]

[Math. 11]

The next stage control signal forming circuit 7 includes a subtracter 4
, 5, and 6, respectively, are supplied with output signals S5, S6, and S7. The control signal forming circuit 7 then generates signals S5, S6, S7.
The control signal Sc is formed according to the combination of values. The control signal Sc is a low active (negative logic) logic signal consisting of three signals Sc2, Sc3, and Sc4. Table 1 below shows the logic of each control signal and the conditions for its establishment. Further, waveform diagrams of the signals Sc2, Sc3, and Sc4 are shown in FIGS. 7(i), (j), and (h), respectively.

[0029]

[Table 1]

As described above, (a) the values of the signals S5 and S6 are both greater than the first positive constant α, and at the same time the values of the signals S7 and S6 are greater than the first positive constant α;
is greater than the second positive constant β, or the values of the signals S5 and S6 are both smaller than the first negative constant −α, and at the same time the value of the signal S7 is the second negative constant β. When it is smaller than the constant -β, the control signal Sc4 becomes 0 (Low), (b) the values of the signals S5 and S6 are both larger than the first positive constant α, and at the same time the value of the signal S7 becomes the second positive constant α. is smaller than the negative constant −β, or the values of the signals S5 and S6 are both the first
is smaller than a negative constant −α and at the same time the value of the signal S7 is larger than a second positive constant β, then the control signal Sc
2 becomes 0 (Low), and (c) signals S5, S6, S7
When the combination of the values of the three signals is a combination other than the above (i.e., the signals Sc2 and Sc4 are 1 (High) at the same time)
), the control signal Sc3 becomes 0 (Low). The above constants α and β are small values compared to the values of the signals S5, S6, and S7, and are set to remove noise components. As a result, the noise equivalent components whose amplitude values are less than α in the signals S5 and S6 are removed, and the noise equivalent components whose amplitude values are less than β from the signal S7 are removed. Therefore, a more accurate control signal Sc that is not affected by noise components can be obtained. Note that there is no problem as long as the signal component lost along with the noise component by this noise removal processing is kept within a few percent of the original signal. An example of a circuit realizing the control signal forming circuit 7 is shown in FIG. 4(a).
Shown below. In FIG. 4(a), signals S5 to S7 are treated as 8-bit digital signals in two's complement representation. Signals S5-S7 are supplied to converters 4-1-4-3, respectively. Converters 4-1 to 4-3 convert signals S5 to S7 into
When the absolute value of the signals S5 to S7 is larger than the positive constants α and β, it is converted to 1, and when it is smaller, it is converted to 0, and it is output as a 2-bit signal in two's complement representation. Table 2 shows the conversion table for each converter.
The IT signals are shown in the following equation (12).

[0031]

[Table 2]

[0032]

[Math. 12]

The converters 4-1 to 4-3 can be realized by a table lookup method using TTL-IC or ROM, and can also be realized by PLA (Programmable L
It can also be realized using Logic Array). The three converter outputs are AND circuits 4-4 to 4-8 and OR circuit 4-9.
, 4-10, NAND circuit 4-11, 4-12, 4-1
3, control signals Sc2, Sc3, Sc4 shown in the following equations
becomes.

[0034]

[Math. 13]

Note that in FIG. 4(a), each signal name Sc2
, Sc3, and Sc4 are listed as mere names, but in the above equation (13), in order to clarify the purpose and operation of the signals, they are expressed as low active (negative logic) logical expressions (i.e., the bar is Sc2, Sc3, and Sc4 are shown. When there is no need for noise removal in the control signal forming circuit 7, positive constants α, β and negative constants − as shown in Tables 1 and 2 are used.
Instead of sorting the signals S5 to S7 by α and -β, the signals S5 to S7 may be sorted by positive, negative, and zero. The conversion table for the converters 4-1 to 4-3 in this case is shown in Table 3 below, and the logic of each control signal and the conditions for its establishment are shown in Table 4 below.

[0036]

[Table 3]

[Table 4]

Returning to FIG. 1, the next stage signal selection circuit 8 receives control signals Sc (signals Sc2, Sc3, Sc4).
), and signals S2, S3, and S4 are supplied. The signal selection circuit 8 selects signals S2, S3, and S according to the control signal Sc.
One of the four signals is selected and output. The output So of the signal selection circuit 8 is expressed by the following equation (14).

[0038]

[Math. 14]

That is, the signal selection circuit 8 selects the control signal Sc2.
When is 0 (Low), the signal S2 is selectively output, when the control signal Sc3 is 0 (Low), the signal S3 is selectively output, and when the control signal Sc4 is 0 (Low), the signal S4 is selectively output. . An example of a circuit realizing the signal selection circuit 8 is shown in FIG.
Shown in c). Blocks 4-14, 4-15, and 4-16 are switch circuits. Each switch circuit 4-14 to 4-1
6 is supplied with signals S2 to S4, respectively, and when one of the control signals Sc2 to Sc4 is 0 (Low), the switch circuit to which that control signal is supplied is turned on,
One of the signals S2 to S4 is output as a signal S8 from the shared output terminal. This signal S8 is
In the next stage latch circuit 4-17, the clock ψm with period Tp
The data of each bit is latched by and synchronized with the data of each bit, and is output from line L3 as an output signal So (an output signal of this image quality improvement device). The output signal S obtained in this way
o has the waveform shown in FIG. 7(k). Each switch circuit 4
-14 to 4-16 are circuits having the same configuration. Figure 4(b)
), as a specific circuit example of the switch circuits 4-14 to 4-16, the switch circuit 4-14 is shown as a representative. Signals S2 and S8 are assumed to be 8-bit, two's complement representation. Blocks 4-20 to 4-27 are buffer circuits with control terminals, and a control signal Sc2 is supplied to the common control terminals. When this control signal Sc2 is 0 (Low), the input signal S2, that is, S20 (LSB) to S2
7 (MSB) is directly output as output S8 (i.e., S80 (L
SB) to S87 (MSB)). When the control signal Sc2 is 1 (High), the output is in a tristate or high impedance state.

Comparing the output waveform So of this image quality improvement device with the input waveform S1, the output waveform So has a waveform step added at approximately the midpoint of the waveform changing part (edge part) of the input waveform S1, and a waveform step is added to the waveform slope part. It can be seen that the slope is steep and the waveform has properly edge-emphasized edges. By reproducing the output signal So, an image whose horizontal contour has been corrected can be obtained. In addition, as can be seen from the output waveform So shown in FIG. 7(k), the edge enhancement processing of this image quality improvement device is effective against edges that exceed the amplitude of the original signal, such as preshoot and overshoot, as in conventional contour correction. This is not an enhancement process, but an edge enhancement process within the amplitude of the original signal. Therefore,
Even when a device incorporating this image quality improvement device is configured with a digital circuit, the problem of overflow does not occur, and the device can improve image quality satisfactorily. In this way, line L
As a result of edge enhancement, the signal So output from 3 is a signal with a waveform step added at approximately the midpoint of the waveform changing part (edge part), that is, a new sideband component is formed,
A frequency component exceeding the original frequency band of the input signal S1 becomes a newly added signal. The addition of this new frequency component equivalently gives the viewer the impression that the resolution of the original signal has been improved, and serves to improve the sharpness of the image.

[0041] The upper limit of the newly added frequency component is:
As will be described later, a first circuit consisting of a delay circuit 2 to a signal selection circuit 8
This value is half the sampling frequency of the signal supplied to the edge enhancement processing circuit. In this embodiment, the interpolation circuit 1 shifts the sampling frequency of the input signal S1 to twice the original frequency, and supplies the shifted signal to the first edge enhancement processing circuit. Therefore, the upper limit value of the frequency component newly added by the edge enhancement process is also twice the upper limit value obtained from the original input signal, and a large edge enhancement effect can be obtained.

Here, the steepness of the edge portion of the signal So (degree of edge emphasis) is determined by the steepness of the edge portion of the original signal S1 before edge emphasis, regardless of the shift of the sampling frequency in the interpolation circuit. It depends on the frequency characteristics it has. For example, if the rising and falling parts (edge parts) of the original signal S1 have a steeper slope as shown in FIG. A certain degree of edge emphasis is performed. FIG. 5(m) is a signal S2 obtained by interpolating the signal S1 shown in FIG. 1(l). in this way,
The degree of edge enhancement processing depends on the frequency of the input signal,
Since there is a perfect correlation with the input signal, this image quality improvement device can improve sharpness and resolution in a natural manner without giving viewers a sense of discomfort.

Furthermore, the illustrated embodiment does not use an expensive quadrature high-pass filter or an in-phase high-pass filter with a complicated circuit configuration, but uses a subtracter with a simpler circuit configuration and lower cost than those filters. The control signal Sc can be formed, and a signal whose edges are properly emphasized is obtained. Therefore, the cost of the entire device can be reduced.

FIGS. 8(a) to 8(c) show the main waveform diagrams in FIG. 7. 8(a) is a waveform diagram of the same signal S1 as in FIG. 7(a), FIG. 8(b) is a waveform diagram of the signal S2 same as in FIG. 7(b), and FIG. ) is a waveform diagram of the same signal So. The signal So2 shown in FIG. 8(d) is a signal obtained by performing edge enhancement processing on the output signal So again using the same circuit as the first edge enhancement processing circuit consisting of the delay circuit 2 to the signal selection circuit 8. Yes, Figure 8(e)
The signal So3 shown in is a signal obtained by further performing the same edge enhancement processing on the signal So2. This figure 8
FIG. 5 shows an image quality improvement device that performs the three-stage edge enhancement process shown in FIG. The block 5-1 is the same circuit as the interpolation circuit 1, and the block 5-2 is a first edge emphasis processing circuit consisting of the delay circuit 2 to the signal selection circuit 8. The block 5-3 is a second edge enhancement processing circuit having the same configuration as the first edge enhancement processing circuit 5-2, and the block 5-4 is also a second edge enhancement processing circuit having the same configuration as the first edge enhancement processing circuit 5-2.
This is a third edge enhancement processing circuit having the same configuration as the edge enhancement processing circuit 5-2. The second and third edge enhancement processing circuits are
The function and effect are the same as those of the first edge enhancement processing circuit. The first edge enhancement processing circuit 5-2 corresponds to a first image quality improvement circuit, and the second edge enhancement processing circuit 5-3 and the third edge enhancement processing circuit 5-4 correspond to a second image quality improvement circuit. do. The second edge enhancement processing circuit 5-3 and the third edge enhancement processing circuit 5-4 connected in series constitute an image quality improver. The image quality improvement device shown in FIG. 5 has a configuration in which an image quality improver is connected in series to a first image quality improvement circuit.

What can be seen from FIG. 8 is that ■signals So, So
2. So3, each time the edge enhancement process is repeated, the waveform slope becomes steeper. (2) Even if the edge enhancement process is repeated, the edge enhancement process does not exceed the amplitude of the original signal S1, such as preshoot or overshoot, as in conventional contour correction, but is an edge enhancement process within the amplitude of the original signal. ■Even if edge enhancement processing is repeated, there is a limit to which further edge enhancement effects cannot be obtained (in the case of Fig. 8, even if edge enhancement processing is performed again on signal So3,
The waveform slope is no longer steepened), and its limit is determined by the sampling period of the signal S2 entering the edge enhancement processing section. ■Even after repeated edge enhancement processing,
The half width Tw of the pulse of the input signal S1 is maintained. These are points such as. The following facts can be understood from the above facts. Each time the edge enhancement process is repeated, peripheral signals move from left and right toward the midpoint of the waveform slope and concentrate, resulting in a steeper slope near the midpoint of the waveform slope. The frequency component added by steepening the waveform slope is a new frequency component that is not included in the input signal to the edge enhancement processing section. If this input signal is sampled, the upper limit value of the new frequency component to be added is half the sampling frequency of the input signal. Therefore, the upper limit value of the new frequency component added by the edge enhancement process by the image quality improvement device of the present invention is half the sampling frequency of the signal S2.

Here, the effects of the interpolation process will be explained with reference to FIG. Figure (a) shows the relationship between the original signal before sampling of the input signal S1 (i.e., the baseband component of the input signal S1, the shaded area in the figure) and the sampling frequency fs of the input signal S1. There is. It is assumed that the original signal is band-limited at the upper limit frequency fu. When this input signal S1 is directly supplied to the first edge enhancement processing circuit shown in FIG. 1 without going through the interpolation circuit 1, the frequency fs/2
The frequency region with an upper limit of 1 is the region that can be used in edge enhancement processing. FIG. 9(b) shows that the sampling frequency of the input signal S1 is doubled to 2f by the interpolation process by the interpolation circuit 1.
FIG. 2 is a diagram showing the relationship with the original signal when s is used. The upper limit of the area that can be used for edge enhancement processing is a frequency of 2fs/
Figure 9(a) extends to 2=fs and does not perform interpolation processing.
This is twice as much as in the case of . Therefore, when the sampling frequency is increased by interpolation processing, sharper edge emphasis can be achieved. FIG. 9C shows the relationship with the original signal when the interpolation process is further advanced and the sampling frequency of the input signal S1 is quadrupled to 4 fs. The frequency domain that can be used for edge enhancement processing is 2 fs, which is four times that of the case without interpolation processing.
With the image quality improvement device of the present invention, sharper and finer edge enhancement can be achieved.

Next, the sampling frequency of 4 by interpolation processing is
Returning to FIG. 1, the change in edge enhancement effect due to doubling and quadrupling of the sampling frequency will be explained. Figure 10(a
), the input signal S1 has a bar pulse waveform as shown in FIG.
The same signal as a) is supplied to the interpolation circuit 1. FIG. 10 is an operation waveform diagram of each part when the sampling frequency is quadrupled. A specific configuration example of the interpolation circuit 1 is shown in FIG.
). The delay time of the delay circuits 2-10, 2-11, and 2-12 is the same as the sampling period T, as in the case of the doubling interpolation circuit shown in FIG. 2(a). Delay circuit 2
-10 to 2-12 act as latch circuits for one clock. x1 is the sample value of input signal S1 on line L1 at an arbitrary time; x2 is the sample value delayed by time T in delay circuit 2-10; x3 is the sample value further delayed by time T in delay circuit 2-11. . The sample value further delayed by time T in the delay circuit 2-12 is assumed to be x4. A relative arrangement diagram of these four sample values on the real time axis is shown in FIG. 6(c) with the position of sample value x3 as the time reference. 4 sample values x
The function of the interpolation circuit shown in Fig. 2(b) is to place three interpolated values y2, y3, y4 between sample values x2 and x3 using 1, x2, x3, x4. be. Sample value x3
, that is, from t=0 to 3T/4, y2, T/2
Interpolate y3 at , and y4 at T/4, respectively. When the interpolated value between sample values x2 and x3 is y,

00
48]

[Math. 15]

[0049]

[Math. 16]

[0050] Mixer 2 that realizes the above formula (15)
Specific configuration examples of -13 to 2-15 are shown in FIG. 3(b). Blocks 3-5 to 3-8 have mixing ratios k1 and k, respectively.
This is an amplifier (data converter) that provides 2, k3, and k4, and can be realized using a table lookup method using a ROM or the like. Sample values x1, x2, x supplied to each input terminal
3 and x4 are multiplied by k1, k2, k3, and k4, respectively, and then added to the combiner of block 3-9, where they are added and combined to become the output sample value y. The interpolated value (sample value) y at any position between the sample values x2 and x3 is the sample value x1~
It is determined by the following equation using the value of x4 and cubic curve approximation based on the relative positional relationship.

[0051]

[Math. 17]

When formula (17) is summarized as formula (15) for the sample values x1 to x4, each mixture ratio k1, k
2, k3, and k4 are as shown in the following equation.

[0053]

[Math. 18]

Using the above equations (17) and (18), FIG.
The following table shows the values of each mixing ratio that give the interpolated values y2 to y4 in c).

[0055]

[Table 5]

Mixers 2-13 to 2-1 shown in FIG. 2(b)
5 is the interpolated value y according to each mixing ratio shown in Table 5.
I'm looking for 2 to y4. The next stage switching circuit 2-16 is supplied with the sample value x3 from the delay circuit 2-11, and interpolated values y2 to y4 from the mixers 2-13 to 2-15, respectively.
is supplied. Then, the switching circuit 2-16 switches the sample value x
3 and three interpolated values y2, y3, y4 as shown in FIG. 6(c).
Output in the order of the sample value sequence shown in . Switching circuit 2-1
6 is shown in FIG. 3(f). Switching circuit 2-
16 is composed of four switch circuits 3-30 to 3-33 and a latch circuit 3-34. The switch circuits 3-30 to 3-33 each have the configuration shown in FIG. 3(c), and the latch circuit 3-34 has the configuration shown in FIG. 3(d). As for FIGS. 3(c) and 3(d), the description has been made regarding the doubling interpolation circuit, so the description thereof will be omitted here. Returning to FIG. 3(f), the input side of the switch circuit 3-33 is supplied with the sample value x3, and the control terminal is supplied with a control signal φ6 of period T for passing the sample value. . The input side of the switch circuit 3-32 has an interpolated value y4
is supplied, and the control terminal is supplied with a control signal φ5 having a period T having a phase difference of T/4 from the control signal φ6 for passing the interpolated value. An interpolated value y3 is supplied to the input side of the switch circuit 3-31, and a control signal with a period T having a phase difference of T/2 from the control signal φ6 is supplied to the control terminal for passing the interpolated value. φ4 is supplied. The interpolated value y2 is supplied to the input side of the switch circuit 3-30, and a control signal with a period T having a phase difference of 3T/4 from the control signal φ6 is supplied to the control terminal for passing the interpolated value. φ3
is supplied. On the input side of the latch circuit 3-34,
Sample value x3 from switch circuit 3-33, interpolated value y4 from switch circuit 3-32, and switch circuit 3-31
The interpolated value y3 from the switch circuit 3-30 and the interpolated value y2 from the switch circuit 3-30 are supplied at T/4 cycles. Then, the latch circuit 3-34 latches each of the four signals every cycle T/4 using the clock ψ2, and outputs a signal S2.
I am getting .

As described above, in the interpolation circuit 1 shown in FIG. 2(b), for the sample values for each period T shown in FIG. 6(d), 3 consecutive sample values are used. An interpolated value is obtained by approximating the following curve, and an interpolated signal S2 of every period T/4 shown in FIG. 6(f) is obtained. FIG. 10(b) shows the waveform of the output signal S2 of the interpolation circuit 1. The white circle is the input signal S1
is the sample value output as is, and the black circle is the interpolated value. Note that the delay circuits 2-10 and 2-11 in the interpolation circuit 1
and a delay T due to the latch circuit 3-34.
/4, the output signal (interpolated signal) S2 is a signal with a time delay of 2.25T with respect to the input signal S1.

A signal S2 is supplied via line L2,
The basic operation of the first edge enhancement processing circuit that outputs the signal S3 from the line L3 is the same as that described above even if the sampling frequency of the signal S2 is quadrupled, so a description of the operation will be omitted. Here, parameters etc. that have been changed due to the quadrupling of the sampling frequency will be explained. First, the delay time Tp of the delay circuits 2 and 3 shown in FIG. 1 is expressed by the following equation.

[0059]

[Math. 19]

This value corresponds to one period of the new sampling frequency fp obtained by the interpolation process. The new sampling frequency fp is

[0061]

[Math. 20]

[0062] Then, the period of the clock ψm supplied to the latch circuit 4-17 in FIG. 4(c), which is a specific configuration example of the signal selection circuit 8, takes the value shown in the above equation (19). These are the changes. The waveform diagrams of each part of the first edge enhancement processing circuit when the sampling frequency is quadrupled are shown in FIGS. 10(c) to 10(k) in correspondence with FIGS. 7(c) to (k).
Shown in (k). Furthermore, the output signal So2 of the second edge enhancement processing circuit and the output signal So3 of the third edge enhancement processing circuit in FIG. 5, which is an example of multi-stage connection of edge enhancement processing circuits, are
are shown in FIGS. 10(l) and (m).

First, when comparing the output signal So of the image quality improvement device shown in FIG. 1 in FIG. 7(k) and FIG. 10(k), it is found that the output signal So in FIG. 10(k) when the sampling frequency is four times In this case, the waveform slope is made steeper, and a greater edge enhancement effect is obtained. This is an effect of shifting the sampling frequency to a higher frequency by the interpolation circuit 1. Similarly, the signal So in the image quality improvement device shown in FIG.
2, So3 in Figures 8(d) and (e), and Figure 10(l),
10(m), a greater edge enhancement effect is obtained in FIGS. 10(l) and (m). If the sampling frequency is quadrupled, the frequency range that can be used for edge enhancement processing will further expand (see Figure 9 (c).
), even if the number of edge enhancement processes is increased beyond the three times shown in FIG. 5, a greater edge enhancement effect can be obtained.

As described above, the edge enhancement processing in the apparatus of the present invention is effective by adding frequency components outside the frequency band of the original signal. Therefore, when the input signal is a sampled signal, the sampling frequency of the input signal is shifted to a higher frequency (for example, shifted from 2 times to 4 times) by interpolation processing, and then edge emphasis is performed. By performing the processing, the upper limit value of the newly added frequency component becomes higher, and the apparatus of the present invention can obtain a greater edge enhancement effect. Furthermore, by performing edge enhancement processing multiple times, the device of the present invention can obtain a greater edge enhancement effect. Even when edge enhancement processing is performed multiple times, shifting the sampling frequency of the input signal to a higher frequency by interpolation processing increases the number of times the edge enhancement processing can be performed, which increases the effectiveness of the processing. Can be emphasized. As described above, FIG. 9 shows the expansion of the frequency region that can be used for edge enhancement processing when the sampling frequency of the input signal is shifted to a higher frequency by interpolation processing. Note that the interpolation circuit of the above embodiment is a simple circuit with a configuration based on the quadratic curve approximation method and the cubic curve approximation method as shown in FIGS. 2 and 3, but it can be A circuit that uses a higher-order curve approximation method may also be used. If a high-order curve approximation method is used, interpolation processing can be performed with higher precision.

Next, main parts of the second to fifth embodiments are shown in FIGS. 11 to 14, respectively. In each embodiment, only the first edge enhancement processing circuit, which is different from the first embodiment, is illustrated. The circuit operation of the first edge enhancement processing circuit of the second embodiment shown in FIG.
No. 8273), the explanation thereof will be omitted here. Similarly, the circuit operation of the first edge enhancement processing circuit of the third embodiment shown in FIG.
The circuit operation of the first edge enhancement processing circuit of the fourth embodiment shown in FIG. Since they are described in detail in the Japanese Patent Application No. 3-78441, their explanation will be omitted here. Figure 1
The circuit operation of the first edge enhancement processing circuit of the fifth embodiment shown in FIG.
No. 83420), the explanation thereof will be omitted. As mentioned in the previous patent application, this image quality improvement circuit uses two mixers, so if the mixing ratios of the two mixers are set to different values, the image quality improvement circuit can be adjusted on both sides of the midpoint of the waveform change section. Waveforms can be changed independently. Therefore, this image quality improvement circuit can more finely adjust the amount of edge enhancement.
It can fully meet the various demands of image quality from viewers.

In each of the second to fifth embodiments, as shown in FIG. 5, second and third edge enhancement processing circuits having the same configuration as the first edge enhancement processing circuit may be connected in series. They may be connected to form an image quality improvement device. Furthermore, the number of connected edge enhancement processing circuits may be increased depending on the purpose of use.

In each of the above embodiments, the input signal was mainly assumed to be an NTSC luminance signal band-limited to an upper limit frequency of 4 MHz, but the image quality improvement device of the present invention
T of PAL system, SECAM system, high-definition system, etc.
It can handle all baseband video and image signals such as V signals and RGB signals. This image quality improvement device is also suitable for image processing devices that handle CG (computer graphics) images and natural images. In particular, for digitized image data, contour correction processing and edge enhancement processing equivalent to the present invention can also be realized by software processing using a computer. can also be applied. Furthermore, the present invention is also effective in improving eye pattern deterioration caused by waveform distortion in a digital transmission system.

[0068]

As described above, the image quality improving device of the present invention has the following effects. (b) Edge enhancement is performed by properly adding a waveform step to the midpoint of the slope part of the input signal, and as a result, an output signal with frequency components outside the frequency band of the input signal is obtained. , contour correction of the reproduced image can be performed. (b) This process does not emphasize edges exceeding the amplitude of the original signal, such as preshoot and overshoot, as in conventional contour correction, but emphasizes edges within the amplitude of the original signal. Therefore, even if a device incorporating this image quality improvement device is configured with a digital circuit, the problem of overflow will not occur, and the device can improve the image quality. (c) The degree of edge emphasis for the input signal depends on the frequency of the input signal, regardless of the shift of the sampling frequency in the interpolation circuit, and has a perfect correlation with the input signal, so
This image quality improvement device can improve sharpness and resolution in a natural manner without giving viewers a sense of discomfort. (D) Edge enhancement processing is performed after shifting the sampling frequency of the input signal to a higher frequency through interpolation processing by the interpolation circuit, so a new frequency is added to the slope part of the input waveform. The upper limit value of the component becomes high, and the device of the present invention can obtain a large edge enhancement effect. (E) The image quality improvement device in which the image quality improver is connected in series to the first image quality improvement circuit can perform edge enhancement processing multiple times in succession, so a steeper waveform change section can be obtained, resulting in a stronger image quality improvement effect. is obtained. (F) An image quality improvement device equipped with a first mixer and a second mixer can change the waveform on both sides of the midpoint of the waveform changing section by setting the mixing ratios of the two mixers to different values. can be changed independently. Therefore, this image quality improvement device can more finely adjust the amount of edge enhancement, and can satisfactorily meet various demands regarding image quality from viewers. (G) Each component of the present invention can be configured by combining conventional circuits, so the image quality improvement device of the present invention can be easily manufactured and has a wide range of uses.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a first embodiment.

FIG. 2 is a diagram showing a specific example of the configuration of the interpolation circuit shown in FIG. 1;

FIG. 3 is a diagram for explaining each circuit in the interpolation circuit.

FIG. 4 is a diagram showing a specific configuration example of the control signal forming circuit and signal selection circuit shown in FIG. 1;

FIG. 5 is a diagram for explaining an example of use of the present invention.

FIG. 6 is an explanatory diagram of the operation of the first embodiment shown in FIG. 1;

FIG. 7 is an explanatory diagram of the operation of the first embodiment shown in FIG. 1;

FIG. 8 is an explanatory diagram of the operation of the usage example shown in FIG. 5;

FIG. 9 is an explanatory diagram of the operation of the first embodiment shown in FIG. 1;

FIG. 10 is an explanatory diagram of the operation of the first embodiment shown in FIG. 1;

FIG. 11 is a diagram showing main parts of a second embodiment.

FIG. 12 is a diagram showing main parts of a third embodiment.

FIG. 13 is a diagram showing main parts of a fourth embodiment.

FIG. 14 is a diagram showing main parts of a fifth embodiment.

[Explanation of symbols]

1 Interpolation circuit 2, 3 Delay circuit 4, 5, 6 subtractor 7 Control signal formation circuit 8 Signal selection circuit

Claims (4)

[Claims] 1. An interpolation circuit that generates an interpolation signal having a cycle shorter than a sampling cycle of the input signal by interpolation processing for a sampled input signal; a delay circuit that outputs a second signal obtained by delaying a certain first signal by a predetermined time; and a third signal obtained by delaying the second signal by the predetermined time; and control based on the first signal. A control circuit for forming a signal is supplied with the first, second, and third signals and the control signal, and is configured to obtain an output signal with a waveform step added to a midpoint position of a waveform changing portion of the input signal. and a signal selection circuit that selects and outputs one of the first, second, and third signals according to the control signal. 2. An interpolation circuit that generates an interpolation signal having a cycle shorter than a sampling cycle of the input signal by interpolation processing for a sampled input signal; a delay circuit that outputs a second signal obtained by delaying a certain first signal for a predetermined time; and a third signal obtained by delaying the second signal for the predetermined time; signal and the first
a first mixer that outputs a fourth signal obtained by mixing the second signal and the third signal at a second predetermined ratio; and a fifth signal obtained by mixing the second signal and the third signal at a second predetermined ratio. a second mixer that outputs the input signal; a control circuit that generates a control signal based on the first signal; the second, fourth, and fifth signals and the control signal are supplied; Selecting and outputting one of the second, fourth, and fifth signals according to the control signal so as to obtain an output signal with a waveform step added to the midpoint position of the waveform changing part of the output signal. 1. An image quality improvement device comprising: a signal selection circuit for selecting a signal; 3. An interpolation circuit that generates an interpolation signal having a cycle shorter than a sampling cycle of the input signal by interpolation processing for a sampled input signal, and connected to the interpolation circuit. a first image quality improvement circuit including a delay circuit, a control circuit, and a signal selection circuit; and one or a plurality of series-connected second image quality improvement circuits having the same configuration as the first image quality improvement circuit. and an image quality improver connected in series to the first image quality improvement circuit, the delay circuit transmitting the first signal which is the interpolation signal. The control circuit outputs a second signal delayed by a predetermined time and a third signal obtained by delaying the second signal by the predetermined time, and the control circuit forms a control signal based on the first signal. , the signal selection circuit is supplied with the first, second, and third signals and the control signal, and is configured to obtain an output signal with a waveform step added to a midpoint position of a waveform changing portion of the input signal. ,
An image quality improving device, wherein one of the first, second, and third signals is selected and output according to the control signal. 4. An interpolation circuit that generates an interpolation signal having a cycle shorter than a sampling cycle of the input signal by interpolation processing for a sampled input signal, and connected to the interpolation circuit. a first image quality improvement circuit comprising a delay circuit, a first mixer, a second mixer, a control circuit, and a signal selection circuit; and a first image quality improvement circuit having the same configuration as the first image quality improvement circuit. , one or a plurality of second image quality improvement circuits connected in series, and an image quality improver connected in series to the first image quality improvement circuit, and the delay circuit outputs a second signal obtained by delaying the first signal, which is the interpolated signal, by a predetermined period of time, and a third signal, which is obtained by delaying the second signal by the predetermined period; The mixer outputs a fourth signal obtained by mixing the first signal and the second signal at a first predetermined ratio, and the second mixer outputs a fourth signal obtained by mixing the first signal and the second signal at a first predetermined ratio. The control circuit generates a control signal based on the first signal, and the signal selection circuit outputs a fifth signal obtained by mixing the first signal with the second signal at a second predetermined ratio. The second, fourth, and fifth signals and the control signal are supplied, and according to the control signal, so as to obtain an output signal with a waveform step added to the midpoint position of the waveform changing part of the input signal,
An image quality improvement device that selects and outputs one of the second, fourth, and fifth signals.