JPH04328874A - Electrostatic induction transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a grid and a channel section possessed of a hetero-junction interface excellent in Schottky junction characteristics. CONSTITUTION:A substrate 1 has such a stepped and sloping surface that flat terraces 1a and steps 1b whose risers are vertical to the terraces 1a are provided extending from one side to the other side, and an N-type GaAs semiconductor layer 2 is provided onto the surface of the substrate 1 to form terraces 2a and steps 2b uniform in shape, a vertical superlattice layer which constitutes a grid section 3 and a vertical superlattice layer which forms a channel section 4 are formed on each of the terraces 2a through an atomic layer epitaxy method taking advantage of the steps 2b so as to come into contact with each other, and an I-type GaAs semiconductor layer 5 is laminated thereon.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static induction transistor that controls the amount of carriers injected from a source region to a channel region by controlling a voltage applied to a grid region, and a method for manufacturing the same.

0002

[Prior Art] Figure 3 shows a conventional static induction transistor (Japanese version of Science, published February 1983, Junichi Nishizawa)
This is a cross-sectional structural diagram showing an n-type drain electrode 28, a drain region 22 made of n-type GaAs, and an n-type GaAs on a substrate (not shown).
An s-layer 23 is formed, and impurities are diffused into the n- type GaAs layer 23 in a mesh or lattice pattern to form a p+-type gate region, and on top of this, a source region made of n-type GaAs is formed. 25 is formed, an n+ type source electrode 27 is laminated on this source region 25, and a p+ type gate electrode 29 is further formed in the gate region 24.

0003

[Problems to be Solved by the Invention] However, in such a conventional static induction transistor, the gate region is formed by ion-implanting impurities into the n- type GaAs layer 23, so the gate region, which becomes the grid portion, is At the heterojunction interface between the transistor 24 and the n- type GaAs layer 23 serving as the channel portion, the impurity concentration is distributed in a gradually decreasing manner, resulting in poor Schottky junction characteristics and a limit to improvement in performance as a transistor.

As a countermeasure to this problem, a method has been proposed in which holes are formed at predetermined locations in the n- type GaAs layer 23 by reactive ion etching and filled with grid material. There was a problem in that it became difficult to fill without gaps, and sufficient Schottky junction characteristics could not be obtained at the heterojunction interface between the grid part and the channel part. The present invention has been made in view of the above circumstances, and its purpose is to provide a static induction transistor having a heterojunction interface with good Schottky junction characteristics between a grid portion and a channel portion, and a method for manufacturing the same. be.

[0005]

[Means for Solving the Problems] A static induction transistor according to the present invention includes a substrate having a surface that is gradually inclined from one side to the other side by a terrace having a flat surface and steps perpendicular to the terrace. , a vertical superlattice layer forming a grid section formed on the terrace in a direction perpendicular thereto, and another vertical superlattice layer forming a channel section in contact with the superlattice layer, and both of these layers. The semiconductor layer is stacked over the superlattice layer.

The method for manufacturing a static induction transistor according to the present invention includes a substrate having a surface that is gradually inclined from one side to the other side by terraces having flat surfaces and steps having surfaces perpendicular to the terraces. In addition, two types of vertical semiconductor superlattice layers bonded to each other using atomic layer epitaxy are grown at positions corresponding to the terraces of each substrate to form a grid portion and a channel portion. It is characterized by including a process.

[0007]

[Operation] In the static induction transistor according to the present invention, by using a substrate having a surface inclined from one side to the other side by a terrace having a flat surface and a step having a surface perpendicular to the terrace, By using the step surface, it is possible to bond the vertical superlattice layers that make up the grid section and the channel section on the terrace without any material being mixed in with each other, resulting in excellent Schottky bonding properties between the two. A heterojunction interface is obtained.

Further, in the method for manufacturing a static induction transistor according to the present invention, vertical superlattice layers constituting a grid portion and a channel portion, respectively, are formed independently on the terrace of a substrate by an atomic layer epitaxy method. Therefore, the mutual bonding surfaces become heterojunction interfaces with excellent Schottky bonding characteristics.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings. 1 and 2 are schematic cross-sectional views showing the main manufacturing steps of the method for manufacturing an electrostatic induction transistor according to the present invention, and 1 in the figures indicates a slightly inclined surface substrate. Slightly inclined surface substrate 1 is produced by polishing the surface of an n-type GaAs single crystal substrate at an angle to a predetermined crystal axis, thereby forming a terrace 1a having a flat surface from one side to the other and a step 1b having a vertical surface. It is in a state of inclination in stages.

Although the areas of the terraces 1a are different, they are planes that are substantially parallel to each other, and the terraces 1a have different areas.
is a step equivalent to one molecule or one atom, and the height is approximately constant in both cases. An n-type layer is formed on the surface of such a slightly inclined substrate 1 using atomic layer epitaxy (ALE).
(Impurity concentration: 3×10 17 cm −3 ) A semiconductor layer 2 is formed and shaped so that the terrace 2 a has a substantially constant width of 160 Å and the step 2 b has a height equivalent to one molecule or one atom.

Next, Nix Al1-x is formed to form a grid portion 3 on each terrace 2a by atomic layer epitaxy.
Then, by repeatedly forming the n-type GaAs semiconductor constituting the channel portion 4 by a predetermined number of times with a width equivalent to 1/2 of the terrace and a height equivalent to one molecule or one atom, Nix Al1-x with a width of 80 Å is formed. A grid portion 3 made of a vertical superlattice layer of n-type GaAs having a width of 80 Å and a channel portion 4 made of a vertical superlattice layer of n-type GaAs having a width of 80 Å are formed in contact with each other and have a height of about 80 Å.

Thereafter, using the same atomic layer epitaxy method, an i-type GaA film with a thickness of 100 Å was grown as shown in FIG.
A semiconductor layer 5 made of GaAs is formed to have a substantially uniform thickness, and a semiconductor layer 6 made of n-type GaAs is further formed as shown in FIG. 2(b).
Laminated and formed. Although not shown, electrodes are formed on the lower surface of the slightly inclined substrate 1, on the surface of the semiconductor layer 6 made of n-type GaAs, and on the grid portion 3, respectively.

[0013] In the electrostatic induction transistor and the manufacturing method thereof according to the present invention, the grid portion 3
By applying a negative voltage to the grid part 3, it is possible to cut off the current flowing through the channel part 4, and by applying a zero or positive voltage to the grid part 3, it is possible to make the current flow through the channel part 4. In addition, to form the grid part 3 and channel part 4, the raw material gases are flowed into the chamber alternately without being mixed with each other, so that the adsorption is stopped in a monomolecular layer by a self-stopping function, and the second layer is Since we use the atomic epitaxy method that utilizes the so-called gas molecule adsorption selection effect, in which molecules are not adsorbed even when they arrive, the growth of the grid portion 3 and channel portion 4 progresses one atomic layer at a time for each introduction of the source gas. do.

Therefore, by alternately supplying the raw material gas of Nix Al1-x and the raw material gas of n-type GaAs, a grid is formed on the upper surface of the terrace at a rate of one molecular layer or one atomic layer without the materials mixing with each other. Part 3, Channel part 4
is grown, forming the grid part 3.
1-x vertical superlattice layer and the n-type GaAs vertical superlattice layer constituting the channel part 4 are formed independently in contact with each other, and are formed on a terrace with a width of 160 Å each with a width of 80 Å. From the step side, the grid portion 3 made of Nix Al1-x and the channel portion 4 made of n-type GaAs are stacked in contact with each other, resulting in a heterojunction interface with excellent Schottky junction characteristics.

[0015]

As described above, in the static induction transistor and the manufacturing method thereof according to the present invention, superlattice layers of different types of semiconductors can be formed in a state in which they are in contact with each other without mixing of materials between them. Therefore, it is possible to form a grid portion and a channel portion having a hetero-interface with excellent Schottky junction characteristics, which is effective in improving characteristics and reliability.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing the main manufacturing steps of a method for manufacturing a static induction transistor according to the present invention.

FIG. 2 is a schematic cross-sectional view showing the main manufacturing steps of the method for manufacturing a static induction transistor according to the present invention.

FIG. 3 is a cross-sectional structural diagram showing a conventional static induction transistor.

[Explanation of symbols]

1 Slightly inclined surface substrate 1a Terrace 1b Step 2 Semiconductor layer made of n-type GaAs 2a Terrace 2b Step 3 Grid section 4 Channel part 5 Semiconductor layer made of i-type GaAs 6 Semiconductor layer made of n-type GaAs

Claims (2)

[Claims] 1. A substrate having a surface that is gradually inclined from one side to the other side by a terrace having a flat surface and a step perpendicular to the terrace, and a substrate formed on the terrace in a direction perpendicular to the terrace. , having a vertical superlattice layer constituting a grid portion, another vertical superlattice layer constituting a channel portion in contact with the vertical superlattice layer, and a semiconductor layer laminated across both these superlattice layers. Characteristics of static induction transistors. 2. A step of forming a substrate having a surface gradually sloped from one side to the other by terraces having flat surfaces and steps having surfaces perpendicular to the terraces, each terrace of the substrate comprising: Electrostatic induction comprising the step of growing two types of vertical semiconductor superlattice layers that are bonded to each other at corresponding positions using atomic layer epitaxy to form a grid part and a channel part. Method of manufacturing transistors.