JP2878488B2 - Semiconductor substrate manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly, to a method for manufacturing a semiconductor substrate in an insulated gate bipolar transistor (hereinafter abbreviated as IGBT).

[0002]

2. Description of the Related Art As a conventional method of manufacturing a semiconductor substrate in an IGBT of this type, FIG. 6 schematically schematically shows major steps of a conventional method of manufacturing a semiconductor substrate in an N-channel IGBT by epitaxial growth.

In FIG. 6, a conventional N-channel type I
In a method of manufacturing a semiconductor substrate (hereinafter, also referred to as an IGBT substrate) in a GBT, first, a relatively low-resistance P ⁺ -type silicon substrate 1a is prepared (see (a)), and then the P ⁺ -type silicon substrate 1a is N ⁺ type buffer layer 2 with relatively low resistance to
a is epitaxially grown to a thickness of about 5 to 30 μm (see (b)), and a relatively high resistance N ⁻ -type epitaxial layer 3a is similarly epitaxially grown on the N ⁺ -type buffer layer 2a (( c)), and thus, in the conventional case, the epitaxial growth is reduced to 2
The required IGBT substrate is obtained by performing the process over and over.

FIG. 7 shows a vertical impurity profile of a conventional IGBT substrate manufactured as described above. As is clear from FIG. 7, in the case of the conventional method, Due to the epitaxial growth performed twice, the boundary between the substrate 1a and each of the growth layers 2a and 3a becomes broad.

Then, an N-channel DMOS is formed on the surface of the IGBT substrate,
The desired N-channel IGBT is configured. In FIG.
The basic structure of this N-channel IGBT is shown.

That is, first, P-type impurities are selectively introduced into the surface of the N ⁻ -type epitaxial layer 3a to form each of the P-type base layers 5, and the surface of each of the P-type base layers 5 is formed. By selectively introducing an N-type impurity into each of the N ⁺ -type emitter layers 6,
Each of these N ⁺ -type emitter layers 6 and N ⁻ -type epitaxial layers 3
The surface portions of the respective P-type base layers 5 sandwiched by “a” become the respective channel regions 7.

Next, a gate electrode 9 is formed on each of these channel regions 7 through a series of gate oxide films 8,
Each emitter electrode 10 is formed on a part of the N ⁺ -type emitter layer 6 and the P-type base layer 5, and a collector electrode 12 is formed on the back surface of the P ⁺ -type silicon substrate 1.

[0008] Thus, the N-channel type I
In the GBT, the emitter electrode 10 and the collector electrode 1
A predetermined collector voltage V _CE between 1 and a predetermined gate voltage V _GE between the emitter electrode 10 and the gate electrode 9
Are applied to each other, the channel region 7
The IGBT is turned into N-type, a channel is formed, and the IGBT is turned on. Electrons are injected from the emitter electrode 10 into the N ⁻ -type epitaxial layer 3a through the channel, and the injected electrons cause the P ⁺ -type silicon substrate 1a. and N ^- type between the epitaxial layer 3a (N ⁺ -type buffer layer 2a) is forward biased, and holes are injected from the P ⁺ -type silicon substrate 1a, N ^- resistance type epitaxial layer 3a is greatly It decreases and the current capacity of the element increases.

In the on-state, the gate voltage
When stopping the application of V _GE, the channel region 7 again, there is no injection of electrons from the emitter electrode 10 is returned to the P-type, and P ⁺ -type silicon substrate 1a and the N ^- order of between -type epitaxial layer 3a The directional bias is eliminated, the holes are not injected, and the IGBT is turned off.

[0010] On the other hand, the time off of the IGBT is, N ^-
Since it takes a certain amount of time before the holes injected into the epitaxial layer 3a disappear, the IGB
The current flowing through T completely stops when the holes in the N ⁻ -type epitaxial layer 3a completely disappear.

As described above, in the operation of the IGBT having the above configuration, the holes injected from the P ⁺ type silicon substrate 1a play an important role, and the holes injected are suppressed. N ⁺ -type buffer layer 2 interposed between P ⁺ -type silicon substrate 1a and N ^-- type epitaxial layer 3a
a.

[0012] That is, when high and thickness impurity concentration of the N ⁺ -type buffer layer 2a in thisゝis thick, it is holes from the P ⁺ type silicon substrate 1 a hardly injected, also,
Conversely, when the impurity concentration is low and the layer thickness is small, the holes are easily injected.

[0013]

However, in the case of an IGBT substrate obtained by the above-mentioned conventional manufacturing method, the epitaxial growth is performed twice so that
^The N ⁺ type buffer layer 2 is formed on the ⁺ type silicon substrate 1a.
a and the N ^- since it forms a type epitaxial layer 3a, as shown in the previous Fig. 7, in particular, the profile of impurities in the longitudinal direction in the N ⁺ type buffer layer 2a is a broad mountain-like In addition to this, the disadvantage of auto-doping from the P ⁺ -type silicon substrate 1a to the N ⁺ -type buffer layer 2a accompanying the heat treatment during epitaxial growth is added, and it is difficult to control the impurity concentration and the layer thickness. In addition, the N ⁺ -type buffer layer 2a has a problem that it can be formed only in the same structure in a two-dimensional plane.

The present invention has been made to solve such a conventional problem, and an object of the present invention is to control the impurity concentration and the layer thickness of a buffer layer in an IGBT easily. In addition, a method for manufacturing a semiconductor substrate of this type, which is capable of forming a structure in which a two-dimensionally varied structure is formed in the buffer layer, a method for manufacturing a semiconductor substrate in an IGBT. To provide.

[0015]

In order to achieve the above object, a method of manufacturing a semiconductor substrate according to a first aspect of the present invention is directed to a method of preparing a first semiconductor substrate of a first conductivity type and low resistance. A first step of bonding a second semiconductor layer of a second conductivity type and a low resistance on the first semiconductor substrate;
The bonded second semiconductor layer has a thickness of 5 μm to 50 μm.
A third step of forming a buffer layer by polishing a layer thickness in the range of up to, then, the bonded a third semiconductor layer of high resistance second conductivity type in the polished surface of the buffer layer And a heat treatment other than the bonding process, if necessary, after the completion of the fourth step.

In a method of manufacturing a semiconductor substrate according to a second aspect of the present invention, a first step of preparing a first semiconductor substrate of a first conductivity type is provided separately on the first semiconductor substrate. A second step of bonding a second semiconductor layer of a second conductivity type, a third step of polishing the bonded second semiconductor layer to a required thickness, and the polished second semiconductor layer A fourth step of selectively forming a second semiconductor region of the first conductivity type in a required portion on the layer; and a fourth step of selectively forming the second semiconductor region in which the second semiconductor region is selectively formed. Prepared second
And a fifth step of bonding a conductive type third semiconductor layer.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor substrate, comprising: a first step of preparing a first semiconductor substrate of a first conductivity type;
A second region for selectively forming a first semiconductor region of the second conductivity type;
And a third step of bonding a second semiconductor layer of the second conductivity type separately prepared on the first semiconductor substrate on which the first semiconductor region is selectively formed, and A fourth step of polishing the second semiconductor layer to a required thickness, and a fifth step of bonding a separately prepared third semiconductor layer of the second conductivity type on the polished second semiconductor layer. And at least steps.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor substrate, comprising: a first step of preparing a first semiconductor substrate of a first conductivity type;
A second region for selectively forming a first semiconductor region of the second conductivity type;
And a third step of bonding a second semiconductor layer of the second conductivity type separately prepared on the first semiconductor substrate on which the first semiconductor region is selectively formed, and A fourth step of polishing the second semiconductor layer to a required thickness; and a step of polishing the required portion on the polished second semiconductor layer.
A fifth step of selectively forming a second semiconductor region of two conductivity type, and a second conductive layer separately prepared on the polished second semiconductor layer in which the second semiconductor region is selectively formed. And a sixth step of bonding the third semiconductor layer of the mold.

[0019]

Accordingly, in the method of manufacturing a semiconductor substrate according to the first aspect of the present invention, a second semiconductor layer of the second conductivity type is bonded on the first semiconductor substrate of the first conductivity type, and After polishing to a layer thickness in the range of 5 μm to 50 μm, a second semiconductor layer of the second conductivity type is bonded to the polished second semiconductor layer to manufacture the second semiconductor layer.
It is possible to easily control the impurity concentration and the layer thickness of the semiconductor layer described above, and further perform a heat treatment other than the bonding processing after bonding the third semiconductor layer as necessary. Can be controlled.

In a method of manufacturing a semiconductor substrate according to a second aspect of the present invention, a second semiconductor layer of a second conductivity type is bonded on a first semiconductor substrate of a first conductivity type, After polishing to a layer thickness, a second semiconductor region of the first conductivity type is selectively formed on a required portion of the polished surface,
In order to manufacture a third semiconductor layer of the second conductivity type by bonding it on the second semiconductor layer in which the second semiconductor region is selectively formed, the impurity concentration of the second semiconductor layer and the layer The thickness can be easily controlled and the two-dimensional two-dimensional change for improving the characteristics of the device in the second semiconductor layer can be easily performed.

In the method for manufacturing a semiconductor substrate according to a third aspect of the present invention, the first semiconductor region of the second conductivity type is selectively formed on a required portion of the first semiconductor substrate of the first conductivity type. The second semiconductor layer of the second conductivity type is bonded to the first semiconductor substrate on which the first semiconductor region is formed and selectively formed, and is polished to a required layer thickness. A first semiconductor substrate, a third semiconductor layer of the second conductivity type, for bonding the second semiconductor layer to the third semiconductor layer.
As a result, it is possible to easily control the impurity concentration and the layer thickness of the second semiconductor layer and change the two-dimensional plane for improving the characteristics of the device in the second semiconductor layer.

In the method for manufacturing a semiconductor substrate according to a fourth aspect of the present invention, the first semiconductor region of the second conductivity type is selectively formed in a required portion on the first semiconductor substrate of the first conductivity type. The second semiconductor layer of the second conductivity type is bonded to the first semiconductor substrate on which the first semiconductor region is formed and selectively formed, and is polished to a required layer thickness. A second semiconductor region of the first conductivity type is selectively formed in a required portion on the second semiconductor layer, and the polished second semiconductor region is selectively formed in the second semiconductor region. In order to manufacture by bonding a third semiconductor layer of the second conductivity type on the layer, the impurity concentration of the first semiconductor substrate and the second semiconductor layer, and furthermore, the impurity concentration of the second semiconductor layer itself and the layer 2 for controlling the thickness and improving the characteristics of the device in the second semiconductor layer. A former planar modifications may readily performed.

[0023]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a semiconductor substrate manufacturing method according to an embodiment of the present invention; FIG.

First, FIG. 1 is a sectional view schematically showing main steps of a method of manufacturing a semiconductor substrate in an N-channel IGBT to which the first embodiment of the present invention is applied. It is.

In FIG. 1, N in the first embodiment is shown.
Semiconductor substrate in a channel type IGBT (hereinafter referred to as IGB)
First, the manufacturing method of the T substrate is relatively low resistance.
After preparing a P ⁺ type silicon substrate 1 (see FIG. 1A),
On this P ⁺ type silicon substrate 1, a separately prepared relatively low-resistance N ⁺ type silicon plate 20 is bonded (see FIG. 1B).

Then, the N ⁺ type buffer layer 2 is formed by polishing the N ⁺ type silicon plate 20 to a required layer thickness, for example, a thickness of about 5 to 50 μm (see FIG. 1C).

After that, an N ⁻ type epitaxial layer 3 is formed by bonding a relatively high resistance N ⁻ type silicon plate separately prepared on the N ⁺ type buffer layer 2. Alternatively, after bonding, polishing is performed to adjust the thickness, and the N ^- type epitaxial layer 3 is similarly formed (see FIG. 1D). The required IGBT substrate is obtained by sequentially bonding the plates.

Therefore, the first created as described above
The IGBT substrates in Example, P ⁺ formation of N ⁺ -type buffer layer 2 for type silicon substrate 1, and N to N ⁺ -type buffer layer 2 on ^- forming type epitaxial layer 3 is, by bonding together Therefore, the heat treatment process during the production of the IGBT substrate is only necessary for bonding, which is much smaller than the conventional case of epitaxial growth twice, and at the same time, N ⁺
As for the type buffer layer 2, as in the conventional case, the P ⁺ type silicon substrate 1 accompanying the heat treatment during epitaxial growth is used.
This eliminates the problem of autodoping from a to the N ⁺ -type buffer layer 2a, which can be maintained at the impurity concentration in the preparation stage.

An IGB using this IGBT substrate
The configuration of T, for example, the basic structure of an N-channel IGBT may be exactly the same as the above-described conventional case, and a description thereof will be omitted.

FIG. 2 shows a vertical impurity profile of the IGBT substrate according to the first embodiment prepared as described above. As is apparent from FIG. When comparing with FIG. 7 in the case of the method,
The shape of the N ⁺ -type buffer layer 2 is reduced so that the shape of the N ⁺ -type buffer layer 2 is substantially similar to that of the staircase junction.
Since the setting is made by polishing after bonding, the control is extremely easy.

In the heat treatment during the fabrication of the IGBT substrate in the first embodiment, only the heat treatment necessary for bonding is described. However, the N ⁺ buffer layer 2 and the N ⁺ buffer layer 2 on the P ⁺ silicon substrate 1 are formed. N ⁻ on the N ⁺ type buffer layer 2
It is extremely easy to perform another heat treatment again after each lamination of the type epitaxial layer 3, and it is possible to freely change the vertical impurity profile of the IGBT substrate itself by the subsequent heat treatment. It is possible to arbitrarily select the most preferable state for the characteristics of the IGBT in ゝ.

FIG. 3 is a sectional view schematically showing main steps of a method of manufacturing a semiconductor substrate in an N-channel IGBT to which a second embodiment of the present invention is applied. It is.

Referring to FIG. 3, N in the second embodiment
A method for manufacturing a semiconductor substrate in a channel-type IGBT includes:
First, as in the first embodiment the method described above, a relatively low resistance P ⁺ -type silicon substrate 1 on the prepared (see FIG. 3 (a)), to the P ⁺ -type silicon substrate 1 Even though
A separately prepared relatively low-resistance N ⁺ type silicon plate 20 is bonded (see FIG. 3B).

Then, the N ⁺ type buffer layer 2 is formed by polishing the N ⁺ type silicon plate 20 to a required layer thickness, for example, a thickness of about 5 to 50 μm (see FIG. 3C).

Furthermore, the above N ⁺ -type buffer layer 2, to form a resist pattern 4 such as by lithography, using the mask, the N ⁺ -type buffer layer 2
P-type impurities, for example, boron are implanted or deposited into each of the desired portions for facilitating the injection of holes (see FIG. 3 (d)), and this is thermally diffused as necessary. By doing so, the respective diffusion portions are N ⁺
Each N ⁻ type region portion 21 changed from the type to the N ⁻ type is selectively formed (see FIG. 3E).

[0036] Thereafter, each N ^- including type region portion 21 N ⁺
Against type buffer layer 2 above, thisゝBut as in the first embodiment the method of the above, a relatively high resistance were separately prepared N ^-
By bonding type silicon plate, N ^- or of type epitaxial layer 3, or after bonding, and polishing due to the thickness adjustment, likewise, N ^- of type epitaxial layer 3 (FIG. 3 ( f)). In this way, by sequentially bonding the individual silicon plates to the silicon substrate, in the required IGBT substrate, here, each N ^- type region portion 2
Thus, an IGBT substrate having an N ⁺ -type buffer layer 2 having a selective double structure 1 and an N ⁺ -type buffer layer 2 having a two-dimensionally varied structure is obtained.

Therefore, the IG according to the second embodiment having the above-described structure is used.
In the BT substrate, the same operation as in the first embodiment described above,
In addition to the effect, the N ⁺ -type buffer layer 2 can be formed with each N ⁻ -type region portion 21 having a double structure in which holes from the P ⁺ -type silicon substrate 1 are easily injected. The injection efficiency can be controlled.

Next, FIG. 4 is a sectional view schematically showing main steps of a method of manufacturing a semiconductor substrate in an N-channel IGBT to which a third embodiment of the present invention is applied. It is.

In FIG. 4, N in the third embodiment is
A method for manufacturing a semiconductor substrate in a channel-type IGBT includes:
First, as in the first embodiment the method described above, a relatively low resistance P ⁺ -type silicon substrate 1 on the prepared (see FIG. 4 (a)), on the P ⁺ -type silicon substrate 1, such as by lithography to form a resist pattern 4, using this mask, to the desired corresponding respective portions to difficult to inject holes in the P ⁺ -type silicon substrate 1, N-type impurity, for example, By implanting or depositing arsenic (see FIG. 4B) and thermally diffusing the arsenic as needed, each of the N ⁺ -type regions is changed from the P ⁺ -type to the N ⁺ -type diffusion region. The portion 11 is selectively formed (see FIG. 4C).

Also, a separately prepared relatively low-resistance N ⁺ -type silicon plate 20 is bonded onto the P ⁺ -type silicon substrate 1 including the respective N ⁺ -type region portions 11 (FIG. 4).
(d)).

Next, the N ⁺ type buffer layer 2 is formed by polishing the N ⁺ type silicon plate 20 to a required layer thickness, for example, a thickness of about 5 to 50 μm (see FIG. 4E).

Thereafter, on the N ⁺ -type buffer layer 2, as in the case of the first embodiment,
By bonding a separately prepared relatively high-resistance N ^-- type silicon plate to form an N ^-- type epitaxial layer 3, or after bonding, polishing for thickness adjustment.
Similarly, the N ⁻ -type epitaxial layer 3 is formed (see FIG. 4 (f)). In this manner, by sequentially bonding individual silicon plates to a silicon substrate, a required IGBT substrate, each N ⁺ -type region portion P ⁺ -type silicon substrate 1 by selective double structure 11, and thus, the N ⁺ -type buffer layer 2, in other words, two-dimensional plane to N by gave change structure ⁺ -type buffer layer 2 Is obtained.

Therefore, the IG according to the third embodiment having the above-described configuration is used.
In the BT substrate, the same operation as in the first embodiment described above,
In addition to the effect, the portion of the P ⁺ type silicon substrate 1 for the N ⁺ type buffer layer 2 where holes are easily injected (N ⁺
Mold silicon part) and difficult to inject part (double structure part)
This also makes it possible to control the hole injection efficiency.

FIG. 5 shows a method of manufacturing a semiconductor substrate in an N-channel IGBT according to a fourth embodiment of the present invention in the order of main steps.

In FIG. 5, N in the fourth embodiment
A method for manufacturing a semiconductor substrate in a channel-type IGBT includes:
First, as in the case of the above-described first embodiment method, a relatively low-resistance P ⁺ -type silicon substrate 1 is prepared (see FIG. 5A). Similarly, a resist pattern 4 is formed on the P ⁺ -type silicon substrate 1 by a lithography method or the like, and the resist pattern 4 is used as a mask to make it difficult to inject holes in the P ⁺ -type silicon substrate 1. N-type impurities, for example, arsenic are implanted or deposited into each part (FIG. 5).
(See (b)), and by performing thermal diffusion as necessary, the respective N ⁺ -type region portions 11 in which the respective diffusion portions are changed from P ⁺ -type to N ⁺ -type are also selectively formed. (Figure 5
(c)).

Further, a separately prepared relatively low-resistance N ⁺ -type silicon plate 20 is bonded to the P ⁺ -type silicon substrate 1 including the respective N ⁺ -type region portions 11 (FIG. 5).
(d)).

Next, the N ⁺ type buffer layer 2 is formed by polishing the N ⁺ type silicon plate 20 to a required layer thickness, for example, a thickness of about 5 to 50 μm (see FIG. 5E).

[0048] Further, as in the second embodiment the method described above, on the N ⁺ -type buffer layer 2, to form a resist pattern 4 such as by lithography, using the mask, the N ⁺ -type P-type impurities, for example, boron are implanted or deposited into desired portions of the buffer layer 2 for facilitating the injection of holes (see FIG. 5 (f)), and if necessary, In this case as well, the diffusion region is changed from the N ⁺ type to the N ⁻ type by thermal diffusion to selectively form each N ⁻ type region portion 21 (see FIG. 5G).

[0049] Thereafter, each N ^- N containing type region portion 21 ⁺
Against type buffer layer 2 above, thisゝBut relatively high resistance N separately prepared ^- by bonding type silicon plate, N ^- or of type epitaxial layer 3, or after bonding, the thickness This is polished for alignment to form an N ⁻ -type epitaxial layer 3 (see FIG. 5 (h)). In this way, by sequentially bonding individual silicon plates to a silicon substrate, IGBT substrate,
N ⁺ -type buffer layer 2 having a selective double structure of each N ⁺ -type region portion 11 and a selective double structure of each N ^-- type region portion 21
In other words, N ⁺
This is to obtain an IGBT substrate having the mold buffer layer 2.

Therefore, the IG according to the fourth embodiment having the above-described structure is used.
In the BT substrate, the same operation as in the first embodiment described above,
In addition to the effect, the same operation and effect as those in the above-described second and third embodiments can be obtained.
It becomes possible to control the hole injection efficiency.

In each of the above embodiments, a method of manufacturing a semiconductor substrate in an N-channel IGBT has been described. However, the same method is applied to a method of manufacturing a semiconductor substrate in a P-channel IGBT. Of course, the operation and effect can be obtained.

[0052]

As described above in detail in each embodiment, according to the method for manufacturing a semiconductor substrate of the present invention, a low-resistance second conductive type first semiconductor substrate is provided on a low-resistance first conductive type first semiconductor substrate. Attach the conductive type second semiconductor layer and make it 5 μm
To form a buffer layer by polishing to a layer thickness in the range of up to 50 μm, and then bonding a high-resistance third semiconductor layer of the second conductivity type to the polished surface of the buffer layer. Unlike the conventional method, in which these second (buffer layer) and third semiconductor layers are deposited and formed by epitaxial growth, the heat treatment to be applied is required only at the time of each bonding. And
As a result, there is an advantage that the impurity concentration and the layer thickness of the second semiconductor layer (buffer layer) can be easily controlled, and if necessary, after the third semiconductor layer is bonded, When a heat treatment other than the alignment process is performed, the impurity concentration can be further controlled, and a semiconductor device having excellent characteristics can be easily configured.

After the second semiconductor layer is polished, a second semiconductor region of the first conductivity type is selectively formed in a required portion of the polished surface, or a required portion of the first semiconductor substrate is polished. Then, by selectively forming the first semiconductor region of the second conductivity type, or by performing both of them, the second semiconductor region is formed.
The control of the impurity concentration and the layer thickness of the semiconductor layer and the two-dimensional planar change for improving the characteristics of the device in the second semiconductor layer can be easily performed. In addition, a semiconductor device having excellent characteristics can be easily configured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing a schematic configuration after each step of a method of manufacturing a semiconductor substrate in an N-channel IGBT to which a first embodiment of the present invention is applied.

FIG. 2 is a graph showing an impurity concentration profile of an N-channel IGBT substrate obtained by the method of the first embodiment.

FIG. 3 is a cross-sectional view schematically showing a schematic configuration after each step of a method of manufacturing a semiconductor substrate in an N-channel IGBT to which a second embodiment of the present invention is applied.

FIG. 4 is a cross-sectional view schematically showing a schematic configuration after each step of a method of manufacturing a semiconductor substrate in an N-channel IGBT to which a third embodiment of the present invention is applied.

FIG. 5 is a cross-sectional view schematically showing a schematic configuration after each step of a method for manufacturing a semiconductor substrate in an N-channel IGBT to which a fourth embodiment of the present invention is applied.

FIG. 6 is a cross-sectional view schematically showing a schematic configuration after each step of a method of manufacturing a semiconductor substrate in an N-channel IGBT according to a conventional example.

FIG. 7 shows an N-channel type IG obtained by the conventional method.
4 is a graph showing an impurity concentration profile of a BT substrate.

FIG. 8 is a cross-sectional view schematically showing a schematic configuration of a basic structure of an N-channel IGBT configured using the IGBT substrate.

[Explanation of symbols]

1 P ⁺ -type silicon substrate 2 N ⁺ type buffer layer 3 N ^- -type epitaxial layer 4 a resist pattern 5 P-type base layer 6 N ⁺ -type emitter layer 7 channel region 8 a gate oxide film 9 gate electrode 10 emitter electrode 11 N ⁺ -type region Part 12 Collector electrode 20 N ⁺ type silicon plate 21 N ^- type region part

Claims (5)

(57) [Claims] 1. A first step of preparing a first semiconductor substrate of a first conductivity type and a low resistance, and bonding a second semiconductor layer of a second conductivity type and a low resistance on the first semiconductor substrate. Second
And the step of bonding the second semiconductor layer to 5 μm
A third step of forming a buffer layer by polishing a layer thickness in the range of up to Luo 50 [mu] m, then paste the third semiconductor layer of high resistance second conductivity type in the polished surface of the buffer layer And a fourth step of combining. 2. The method of manufacturing a semiconductor substrate according to claim 1, wherein after the fourth step, a heat treatment other than the bonding process is performed. 3. A first step of preparing a first semiconductor substrate of a first conductivity type, and a step of bonding a second semiconductor layer of a second conductivity type separately prepared on the first semiconductor substrate. Step 2, a third step of polishing the bonded second semiconductor layer to a required thickness, and a second portion of the first conductivity type on a required portion of the polished second semiconductor layer. A fourth step of selectively forming the second semiconductor region, and bonding a second semiconductor layer of the second conductivity type separately prepared on the second semiconductor layer on which the second semiconductor region is selectively formed. And a fifth step of combining. 4. A first step of preparing a first semiconductor substrate of a first conductivity type, and selectively forming a first semiconductor region of a second conductivity type on a required portion on the first semiconductor substrate. A second step of forming, and a third step of bonding a second semiconductor layer of a second conductivity type separately prepared on the first semiconductor substrate on which the first semiconductor region is selectively formed, A fourth step of polishing the bonded second semiconductor layer to a required thickness, and bonding a second semiconductor layer of the second conductivity type separately prepared on the polished second semiconductor layer. And a fifth step of combining. 5. A first step of preparing a first semiconductor substrate of a first conductivity type, and selectively forming a first semiconductor region of a second conductivity type on a required portion on the first semiconductor substrate. A second step of forming, and a third step of bonding a second semiconductor layer of the second conductivity type separately prepared on the first semiconductor substrate on which the first semiconductor region is selectively formed, A fourth step of polishing the bonded second semiconductor layer to a required thickness, and a required portion on the polished second semiconductor layer,
Fifth step for selectively forming the second semiconductor region of the second conductivity type
And a sixth step of bonding a separately prepared second semiconductor type third semiconductor layer on the polished second semiconductor layer in which the second semiconductor region is selectively formed, A method for manufacturing a semiconductor substrate, comprising at least: