JPS61206251A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain high gains with excellent reproducibility while enabling operation at high speed, and to improve load driving capability by forming a first conduction type third region diffused from the surface of an epitaxial layer to the side surface of a second region and demarcating the side surface and base of an epitaxial layer in an island region by the second region and the third region. CONSTITUTION:An N<+> type buried diffusion layer 2 is shaped to a P<-> type silicon substrate 1, an silicon oxide film 10 is formed, and boron ions are implanted while using a resist 11 as a mask, and annealed in an inactive atmosphere. An N-type epitaxial layer 4 is shaped, and isolated by an element isolation silicon oxide film 3. Boron is buried into the N<+> type buried layer 2 in high concentration as a rule at that time, and an active P-type layer is not formed yet. An inactive P-type layer 51 is diffused and shaped to the N-type epitaxial layer 4, boron made to be contained in the buried diffusion layer 2 is diffused upward through the heat treatment of the layer 4 to form an active P-type layer 52, and an N-type layer 6 is isolated from the epitaxial layer 4. A P<+> type layer 7 is diffused and shaped, and the opening of an N<+> layer for the ohmic contact of the N-type layer 6 is bored. The current gains of a PNP transistor are controlled by the diffusion depth of the P<+> type layer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a highly integrated and high-performance piezoelectric semiconductor integrated circuit device.

(Prior Art) FIG. 2 is a cross-sectional structural diagram of a bipolar semiconductor integrated circuit device disclosed in Japanese Patent Application No. 58-104260, where l is a P'''' silicon substrate and 2 is a N''U. embedded layer,
3 is an element isolation silicon oxide film.

Here, an N-R epitaxial layer 4 and a P-type layer 5 are formed on the Nff1 buried layer 2, and this P-type layer 5 has the following characteristics:
An N-type layer 6 is formed.

The P type layer 6 is formed with a P” ffi layer 7 and an N+ type layer 8, where the N type layer 6 is a paste, the P type layer 5 is a collector, and the P type layer 5 is a collector.
The type layer 7 is formed with a PNP transistor serving as an emitter.

In addition, an NPN transistor is formed in which the N-type layer 6 is the emitter, the P-type layer 5 is the base, and the N+-type buried layer 2tl-collector.
N) A run source is formed in a silicon island region surrounded by an isolation oxide film 3, and constitutes an independent r-).

FIG. 3 is an equivalent circuit of the above f-), and Qt-Q- are the above-mentioned PNP) transistor and NPN) transistor, respectively. Also, in Figures 2 and 3, ■ is 0
．． 7-0.9v power supply electrode, G is the ground electrode, G is the input electrode, 0. ,0. ．． 0. is the output electrode, 0,,O,,
A Schottky barrier diode (hereinafter referred to as SB'D) Dt, I) is placed at the interface with the O, CN-epitaxial layer 4.
t and Da and are separated from each other.

As is clear from the equivalent circuit in FIG. 3, the operation of the dart described above is based on the integrated injection logic.
tionLogic: Hereafter! Wired AND (referred to as L), which connects the outputs of multiple darts to each other and inputs them to the next dart.
) It is a saturated desotal logic dart that constitutes logic by D.

Note that the N+ layer 8 in FIG. 2 is provided to ohmically connect the ground electrode G to the N-type layer 6, and becomes unnecessary if the impurity concentration of the N-type layer 6 is sufficiently high. .

Normal work! In L, PNP) lateral transistor Q1, NPN), yy transistor Q
! Since the Q8 is composed of inverted-operation vertical (particle) transistors, the characteristics of both transostors are insufficient.However, in the structure shown in FIG.
, NPN) and Lansostar Q are both constructed of vertical transistors that operate in the head direction, resulting in low reactive power and a structure suitable for high-speed operation.

Therefore, it is possible to realize an integrated circuit device that maintains a high degree of integration comparable to that of I"L and operates at a higher speed than I"L.

(Problems to be Solved by the Invention) However, in order to form the above structure using the existing technology, a triple diffusion transistor in which a P-type layer 5, an N-type layer 6, and a P-salt layer 7 are sequentially diffused is used as a PNP transistor. ) Lansosta Q
It was necessary to use it as 1.

However, it is generally extremely difficult to obtain high-performance transistors by triple diffusion, and there are drawbacks such as poor reproducibility.

In addition, the P-type layer 5 has le, which needs to be formed at a low concentration,
The large pace resistance υ of the (NPN) lannostar Q impedes high-speed operation, and furthermore, the reactive power due to lateral injection is large, making it difficult to obtain a high current amplification factor.

In order to avoid this problem, a new photolithography process and a diffusion process are required to increase the concentration of the inactive paste of the NPN transistor, which has the drawback of complicating the process.

This invention solves the problems of the above-mentioned prior art.
Difficulties in manufacturing high-performance transistors using triple diffusion,
Obstruction of high-speed operation and difficulty in obtaining high current amplification factors,
The present invention provides a method for manufacturing a semiconductor integrated circuit device that solves the problem of process complexity.

(Means for Solving the Problems) The present invention provides a method for manufacturing a semiconductor integrated circuit device.
A second conductive type semiconductor substrate is placed at a predetermined location on the main surface of the first conductivity type semiconductor substrate.
After forming the first conductive region and introducing impurities of the first conductivity type into a part thereof, a second conductive epitaxial layer is grown to perform element isolation to divide it into a plurality of true regions. A second region having a high concentration of the first conductivity type and a first conductive plate impurity are diffused upward to form a third region having the first conductivity, and the epitaxial layer of the island region is side-walled by the second region and the third region. This method introduces a step of dividing the bottom surface into a defined fourth region and a fifth region.

(Function) According to the present invention, since the above-described steps are introduced into the method for manufacturing a semiconductor integrated circuit device, the second region having a high concentration of the first conductivity type is formed from the first region by diffusion, and the second region is formed by diffusion. Depending on the ion implantation dose, the current gain of the PNP transnoster can be controlled independently by the diffusion depth of its emitter, and the low resistance of the third region acts to suppress reactive current deposits in the lateral direction of the second region. , Therefore, the above problem can be eliminated.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor integrated circuit device of the present invention will be described with reference to the drawings. Figure 1 Prisoner or 1st
Figure ■ is a process explanatory diagram of one example. The same parts as in FIG. 2 are given the same reference numerals and explained in FIG.

First, as shown in FIG. 1, an N+ type buried diffusion layer 2 is formed on a p-board silicon substrate 1 as a semiconductor substrate, a thin silicon oxide film 10 is formed on the surface, and a boron layer is formed using a resist 11 as a mask. ion implantation and annealing in an inert atmosphere.

For forming the N+ star buried diffusion layer 2, it is appropriate to use antimony as an impurity, which is less autodoped than the epitaxial layer, and the surface concentration is 10'9 to 10"cm-".
The layer resistance is 50 Ω/mouth or less, preferably 20 to 30
Approximately Ω/mouth is suitable.

In addition, the dose of boron is 1X101A~5X10'
A thickness of about 3 is appropriate, and can also serve as a channel stop layer (not shown) for complete element isolation. Note that as a mask for ion implantation, a thick oxide film or other material may be used.
An N-type epitaxial layer 4 with a thickness of 2 to 3 μm is formed before and after O, and an element isolation silicon oxide film 3 is formed by a known method.
Perform proper separation. Thereafter, an oxide film is formed on the surface of the element region, and an opening for forming an inactive P layer is formed.

At this point, the boron ions implanted in the region indicated by the broken line are usually buried in the highly concentrated N+ type buried layer 2.
The active P-type layer 51 has not yet been formed. Next, as shown in FIG. Diffusion formation and opening for emitter of PNP) lansoster. The inactive P-type layer 51 is formed to have a high surface concentration of about 1019 to 1003-3, and the heat treatment causes boron contained in the buried diffusion layer 2 to diffuse upward and form the active P-type layer 52. is formed and connected to the inactive P-type layer 51 to separate the N-type layer 6 from the epitaxial layer 4 .

Next, as shown in FIG. 1, a PM layer 7 which will become an emitter of a PNP (PNP) lansoster is formed by diffusion, and an opening is made in the N+ layer for an ohmic contact of the N-type layer 6. This P+ type layer 7
The diffusion depth of PNP) controls the current gain of the lansostar.

Subsequently, as shown in FIG. 1 [F], an N+ warm layer 8 is formed by diffusion, and after the usual contact hole opening and metal wiring process,
A semiconductor integrated circuit device similar to that shown in FIG. 2 is completed.

In this way, K, according to the manufacturing method of the embodiment of the present invention, N
The current gain of the PN) transistor can be controlled independently by the boron ion implantation dose, and the current gain of the PNP transistor can be controlled independently by the diffusion depth of the P+ type layer 7, so it is possible to obtain a high gain with good reproducibility. Become.

In addition, the P-type layer is formed by forming two parts, the active P-type layer 52 and the inactive P-type layer 51, and the base resistance of the NPN transistor surrounding the active P-type layer 52, which is the active pace of the NPN transistor, is significantly reduced. In addition, lateral reactive current injection is significantly suppressed, and the switching frequency is improved.
High-speed operation is possible.

As already mentioned, the semiconductor integrated circuit device U shown in FIG.
Same operation as I"L. Normal I"L is PNP)
While the common emitter current gain of a transistor is approximately 1 to 4, in the semiconductor integrated circuit device obtained by the manufacturing method of the present invention, it can easily be increased to 100 or more, and reactive power is reduced. , and since the logic amplitude is approximately halved by the SBD, low power consumption is significantly improved.

On the other hand, when an I"L NPN) run source has multiple collectors, the current gain is 10 or less, usually 5 or less,
Although the cutoff frequency is also low at about 50 MHz, in the semiconductor integrated circuit device obtained by this invention, a gain of 100 or more and a cutoff frequency i of around GHz can be easily obtained, resulting in significantly improved high speed and load driving ability. do.

Furthermore, compared to the conventional triple diffusion method, the manufacturing method of the present invention allows the active P-type layer 52 to be formed at the same time as the formation of the channel gutt layer for device isolation, so that the photolithography process and the diffusion process are substantially the same. There is an advantage that the number of steps is reduced by one and the steps are shortened.

Furthermore, according to the manufacturing method of the present invention, it is possible to form a normal bipolar transistor on the same substrate using the P+ type layer 7 and the Nff1 layer 8.
P) Needless to say, it is possible to form a lansostar and a resistance element.

Therefore, the semiconductor integrated circuit device as shown in FIG. 2 obtained by the manufacturing method of the present invention is suitable for a composite integrated circuit device represented by a digital/analog circuit mixed type, and in particular, its operation is the same as that of I2L. Since it is,
The product range traditionally produced by I"L has a wide range of applications.

! (Effects of the Invention) As described above in detail, according to the present invention, impurities of the first conductive plastic are introduced into the first region of the second conductivity type on the semiconductor substrate of the first conductivity type. An epitaxial layer of a second conductivity type is grown on the epitaxial layer, and an impurity of the first conductivity type is diffused upward into the bottom surface of a part of the epitaxial layer to form a second region, and an epitaxial layer is grown on the side surface of the second region. By forming the third region of the first conductivity type diffused from the surface and defining the side and bottom surfaces of the epitaxial layer of the island region by the second region and the third region, the effects listed below can be achieved. play.

(1) High gain can be obtained with good reproducibility.

(2) High-speed operation is possible and load driving ability is improved.

(3) Low power consumption is significantly improved.

(4) The process is shortened.

[Brief explanation of drawings]

1 to 1 are process explanatory diagrams of an embodiment of the method for manufacturing a semiconductor integrated circuit device of the present invention, FIG. 2 is a sectional view of a conventional semiconductor integrated circuit device, and FIG. FIG. 2 is an equivalent circuit diagram of a semiconductor integrated circuit device of FIG. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... N''ffi buried diffusion layer, 3... Element isolation silicon oxide film, 4... N
type epitaxial layer, 51... inactive P type layer, 52.
...Active Pffi layer, 6...NM layer, 7...PW layer, 8...N type layer. Patent applicant: Oki Electric Industry Co., Ltd. Figure 1 Figure 1 Figure 12 Figure 3

Claims (3)

[Claims] (1) A highly concentrated first region of the second conductivity type is formed on a selected main surface of the first conductivity type semiconductor substrate, and a first conductivity type impurity is introduced into a part of the first region. a step of growing an epitaxial layer of a second conductivity type on one main surface of the semiconductor substrate and performing element isolation of dividing the epitaxial layer into a plurality of island regions; At the same time as forming a highly-concentrated second region of one conductivity type, the first conductivity type impurity is diffused upward to form the second region of high concentration.
forming a third region of the first conductivity type extending in the region; and forming a sixth region of a first conductivity type and a seventh region of a second conductivity type on the surface of the fourth region. Production method. (2) The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor substrate is a silicon substrate and the first conductivity type impurity is boron. (3) the first conductivity type is P type, the second conductivity type is N type,
The sixth region is an emitter, the fourth region is a base, and the second region is an emitter.
A PNP bipolar transistor whose collectors are the region and the third region, and whose emitters are the fourth region and the seventh region.
2nd area and 3rd area as base, 1st area and 5th area as base
3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising forming an NPN bipolar transistor having a region as a collector.