JPH04328386A - Clearing method for graphic memory - Google Patents

Abstract

PURPOSE:To clear the contents of a graphic memory in a short time. CONSTITUTION:A clearing data of by one row is inputted to a SAM port 11 by a clearing circuit (buffer) 7. Thereafter, a write transferring cycle is executed by a clear mode controller 8, by writing the clearing data to a RAM port 12, the data of the RAM port 12 is possible to clear by a row unit and the time required to clear is shortened.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention is a so-called multi-port graphic memory (also called multi-port memory) that combines serial access memory (hereinafter also called SAM port) and random access memory (hereinafter also called RAM port). Regarding the clearing method of

0002

2. Description of the Related Art FIG. 6 shows an outline of a graphic system using a multi-port memory. In the same figure, 1 is S
A multiport memory consisting of an AM port 11 and a RAM port 12, 2 a synchronization signal synthesis circuit, 3 a timing signal generation circuit, 4 a monitor TV, and 5 a processing unit (CP
U), 6 is an input/output section of the SAM port 11. Multiport memory 1 has a row address strobe RAS
, column address strobe CAS, write per bit/write enable WB/WE, data transfer/output enable DT/OE, etc., determines its operation mode. Note that these signals have a meaning at the falling edge. Also, ADDRE
SS indicates an address signal line, and WiO indicates a data line.

[0003] RA from CPU 5 to multiport memory 1
A data write operation to the M port 12 is shown in FIG. First, at time t1, the timing signal generation circuit 3 generates the RAS signal according to the instruction from the CPU 5 as shown in FIG. . Further, at the next time t2, a CAS signal as shown in FIG. 12B is generated, and the column address and data of the RAM port 12 to be written are generated as shown in FIGS. As a result, one dot (one pixel) of data in the RAM port 12 is rewritten.

FIG. 8 shows the operation of the SAM port. Time t
1, one row of data in RAM port 12 is
Transfer to AM port 11 (read transfer cycle (c))
Then, the serial clock SC shown in the same figure (b) is set to SA.
By inputting to M port 11, SAM port 11
Since the serial data SiO for each pixel is output to the synchronization signal synthesis circuit 2, the synchronization signal synthesis circuit 2 combines this data SiO and the synchronization signal CSYNC from the timing signal generation circuit 3 as shown in FIG. and is output to the monitor television 4 as a video signal. Note that, except during the data transfer cycle between the RAM port 12 and the SAM port 11, the RAM port 12 and the SAM port 11 can operate independently and asynchronously.

[0005]

[Problem to be Solved by the Invention] By the way, in such a graphic system, when trying to clear the entire graphic screen or only a certain rectangular area,
The data write operation from the CPU 5 to the RAM port 12 shown in FIG. 6 must be performed for the number of pixels to be cleared. For example, if the number of pixels is 512 (rows) x 512 (columns) ≒ 2
When you want to clear the entire 50,000-pixel screen, you have to repeat the data write operation to RAM port 12 about 250,000 times to clear the entire graphic screen, and as a result, it takes a long time to clear it. There is a problem that it takes. Therefore, an object of the present invention is to make it possible to clear a graphic screen in a short time.

[0006]

[Means for Solving the Problems] In order to solve these problems, the present invention provides a multi-port memory that combines a serial access memory and a random access memory, by providing a clear circuit in the input/output section of the serial access memory. In addition, a control circuit is provided for controlling data transfer between the serial access memory and the random access memory, and after the contents of one row of the serial access memory are set to all 0s by the clear circuit, the control circuit It is characterized in that by transferring all 0 data from the serial access memory to the random access memory under the control of the serial access memory, the contents can be cleared line by line. Further, by providing an area setting circuit in addition to the above, it is also possible to clear only a specific area of the screen.

[0007]

[Operation] The clear circuit inputs one line of clear data to the SAM port, and then the control circuit executes a write transfer cycle to write one line of clear data from the SAM port to the RAM port.
To shorten the time for clearing by making it possible to clear data in a RAM port line by line. Further, by providing an area setting circuit, it is possible to clear data only in a specific area of the RAM port.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in the figure, the circuit shown in FIG. 6 is characterized in that a buffer (clear circuit) 7 and a clear mode control circuit 8 are added. The operation will be explained below with reference to FIG. Here, a case will be described in which the entire graphic screen 20 (number of rows b, number of columns a) as shown in FIG. 3 is cleared, for example.

First, as shown in the same figure (a), the clear mode pulse CLR given from the CPU 5 becomes "low" at time t1.
When the level is reached, buffer 7 is opened and the SiO data is “
0". Next, the clear mode control circuit 8 executes a pseudo write transfer cycle at time t2 as shown in FIG. Next, between times t3 and t4, as shown in FIG.
column) and clear the contents of SAM port 11 (
Set all to 0). After that, between time t5 and t6, line 0~
By executing a write transfer cycle as shown in (c) for each row address of row b, the entire graphic screen can be cleared. Note that when clearing only a certain row, the corresponding row address is shown in Figure 7.
This can be done by sending it together with the row address strobe RAS signal, as in the case of .

FIG. 4 is a block diagram showing another embodiment of the invention. The feature of this embodiment is that a clear area control circuit 9 for setting a clear area is provided in contrast to the one shown in FIG. Others are the same as in FIG. FIG. 5 shows the time chart. Here, a case will be described in which the data in area 21 in FIG. 3 is cleared. First, as shown in FIG. 5(A), when the clear mode pulse CLR given from the CPU 5 becomes a "low" level at time t1, the buffer 7 is opened and the SiO data becomes "0". Next, select the row address c that includes the area 21 you want to clear, which is indicated by the AREA signal from the CPU 5, and
A read transfer cycle is executed at time t2 as shown in FIG. This point is a feature when clearing a specific area, and this is done by first transferring data from RAM port 12 to SAM port 11.
This shows the operation of transferring to. Next, at time t3, the column address is set to the start address (d) of the rectangular area 21 to be cleared, and the pseudo write transfer cycle is started as shown in the same figure (
Execute as in d). After that, the number of pixels in the horizontal direction of the rectangular area 9 for which you want to clear the serial clock SC (e-d)
, as shown in the figure (b) between times t4 and t5, and after initializing the column address to the left end (0) of the graphic screen, change the row address to c and at time t6 as shown in the figure (e). Execute a write transfer cycle. Above is low c
Since the data in columns d to e will be cleared, by repeating this operation for rows c+1 to f, it becomes possible to clear the specific area 21 shown in FIG.

[0011]

[Effect of the invention] According to this invention, from the SAM port
Since clear data for a line is input and the data is transferred to the RAM port at once, the entire graphic screen or a specific area within it can be cleared line by line. As a result, compared to the conventional clearing method for each pixel, there is an advantage that clearing can be performed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the invention.

FIG. 2 is a time chart for explaining the operation of FIG. 1;

FIG. 3 is an explanatory diagram for explaining a graphic screen.

FIG. 4 is a block diagram showing another embodiment of the invention.

FIG. 5 is a time chart for explaining the operation of FIG. 4;

FIG. 6 is a block diagram showing a conventional example of a graphic display system.

FIG. 7 is a time chart for explaining the data write operation in FIG. 6;

FIG. 8 is a time chart for explaining the operation of the SAM port in FIG. 6;

[Explanation of symbols]

1 Multi-port memory 2 Synchronous signal synthesis circuit 3 Timing signal generation circuit 4 Monitor TV 5 Processing unit (CPU) 6 Input/output section 7 Buffer 8 Clear mode control circuit 9 Clear area control circuit 11 SAM port 12 RAM port 20 Graphic screen 21 Specific area

Claims (2)

[Claims] [Claim 1] A multiport memory that combines serial access memory and random access memory,
A clear circuit is provided in the input/output section of the serial access memory, and a control circuit for controlling data transfer between the serial access memory and the random access memory is provided, and the clear circuit clears data for one row of the serial access memory. After setting the contents to all 0's, the data of all 0's is transferred from the serial access memory to the random access memory under the control of the control circuit, thereby making it possible to clear the contents line by line. How to clear graphics memory. [Claim 2] A multiport memory that combines serial access memory and random access memory,
A clear circuit is provided in the input/output section of the serial access memory, and a control circuit for controlling data transfer between the serial access memory and the random access memory, and a setting circuit for setting an area to be cleared, After the contents from a certain column to a certain column corresponding to the set area for one row of the serial access memory are set to all 0 by the clearing circuit and the setting circuit, the serial access memory is set to zero under the control of the control circuit. A method for clearing a graphic memory, characterized in that a specific area can be cleared by repeatedly transferring data from an access memory to a random access memory.