JPH04326484A - Analog multiplying circuit - Google Patents

Abstract

PURPOSE:To enable an operation by means of a low constant voltage source and to secure linearity in a wide in/out level area and a wide dynamic range by providing a common-mode output generating part which imparts the common- mode component of an input signal to a multiplying output generating part so as to remove an opposite phase component. CONSTITUTION:The output of the left half circuit of the circuit incorporated simultaneously the component of the input voltage V1 of an opposite phase input terminal 20 and the multiplying output component of the opposite input voltage V1 and the input voltage V2 of a common-mode input terminal 21. The differential circuit in the right half of the circuit adjusts the value of the constant voltage source 24 and the resistance values of resistors 28 and 29 and adds the opposite phase component of the voltage V1 being the adequate value. Thus, the V1 component in the output voltage V0 component of the output terminal 31 is removed so that only the multiplying component of V1 and V2 is obtained. Then, an analog multiplying circuit used for the modulating/ demodulating circuit of the transmitting/receiving circuit for a radio is constituted of the two stages in the number of the longitudinal load stages of a transistor.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog multiplication circuit that performs analog multiplication of two input signals in a modulation/demodulation circuit used in radio transmitting/receiving circuits and the like.

0002

2. Description of the Related Art FIG. 5 is a circuit diagram showing an example of the configuration of a Gilbert cell used as a conventional analog multiplication circuit. In the figure, transistors 51 and 52 and transistors 53 and 54 form a differential pair, with the bases of transistors 51 and 54 connected to input terminal 55, and the bases of transistors 52 and 53 connected to input terminal 56. The emitters of transistors 51 and 52 and the collector of transistor 57 are connected, and the emitters of transistors 53 and 54 and the collector of transistor 58 are connected. The emitters of transistors 57 and 58 are connected to resistors 59 and 58 respectively.
60, and a current source 61 is connected to the connection point of each resistor.
is connected. Further, the bases of the transistors 57 and 58 are connected to input terminals 62 and 63. The collectors of the transistors 51 and 53 and the collectors of the transistors 52 and 54 are connected to output terminals 64 and 65, respectively, and are also connected via resistors 66 and 67, and a constant voltage source 68 is connected to the connection point of each resistor. is connected.

The operation of the analog multiplication circuit will be explained below. The current flowing into the collector of each transistor 51-54, 57, 58 is I1-I4, I7
, I8, the current of the constant current source 61 is I9, and the current amplification factor of each transistor is β0, then β0 >
>1, the relationship is I1 +I2 =I7 I3 +I4 =I8 I7 +I8 =I9.

[0004] The input voltage of input terminals 55 and 56 is set to V1,
Assuming that the thermal voltage of the transistor is Vt, that V1 is sufficiently small, and that |V1 | Become. However, gm12 and gm34 are the transconductances of each differential pair.

Furthermore, since the above differential pair does not have an emitter negative feedback resistor, the value of the corresponding transconductance is proportional to the bias currents I7 and I8 flowing through each stage, and g
m12 = I7 /Vt gm34 = I8 /Vt. Here, the total differential output voltage VO is the resistor 66
and the resistance value of resistor 67 is RL, then VO = RL
((I1-I2)+(I3-I4)). Therefore, according to the relationship shown above, the total differential output voltage VO is as follows: VO = V1・RL (gm12-gm34)=V1・R
It can be expressed as L(I7-I8)/Vt.

On the other hand, the input voltage of the input terminals 62 and 63 is set to V
2. Let the resistance values of resistors 59 and 60 be RE, and I7.
If RE>>Vt and I8・RE>>Vt, then
The current difference between I7 and I8 is proportional to V2, and I7-I8 = V2/RE is obtained.

[0007] When the above relationship is summarized, the total differential output voltage VO becomes VO = (RL/RE·Vt)·V1·V2, and the product output of the input voltage V1 and input voltage V2 is obtained.

[0008]

However, in such a conventional configuration, if the constant current source 61 is composed of a transistor and a resistor, the number of vertically stacked transistors is three. Therefore, in order to operate this analog multiplication circuit correctly, it is necessary to make the voltage value of the constant voltage source 68 larger than 2.4V.

That is, in the conventional configuration, linearity over a wide input/output level range and wide dynamic It was difficult to secure a microwave. Furthermore, it could not be operated as a multiplier circuit under a constant voltage source of 2V or less. The present invention
It is an object of the present invention to provide an analog multiplier circuit that can operate under a low constant voltage source and can ensure linearity and a wide dynamic range over a wide input/output level range.

0010

[Means for Solving the Problems] The invention as set forth in claim 1 provides a first input terminal connected to the base of the first transistor, and a second input terminal connected to the bases of the second transistor and the third transistor. a third input terminal is connected to the base of the fourth transistor, and the emitters of the first transistor and the second transistor are connected to the third input terminal.
and the emitter of the fourth transistor are connected via a first resistance element and a second resistance element, and a first constant current source is connected to the connection point of each resistance element, and the first transistor and a first output terminal is connected to the collector of the second transistor, a second output terminal is connected to the collectors of the third transistor and the fourth transistor, and a third resistive element and a third resistive element are connected between the respective collectors. a multiplication output generation section that connects via a fourth resistance element and connects a first constant voltage source to the connection point of each resistance element, and outputs the multiplication output of the input signal to the first and second output terminals; , the first input terminal is connected to the base of a fifth transistor, and the sixth transistor and the seventh transistor are connected to each other.
The second resistor is connected to the base of the transistor through the fifth resistor
a constant voltage source is connected to the base of the eighth transistor, the third input terminal is connected to the base of the eighth transistor, and the emitters of the fifth transistor and the sixth transistor are connected to the emitters of the seventh transistor and the eighth transistor. emitter and the 6th
and a seventh resistance element, and a second constant current source is connected to the connection point of each resistance element, and the collectors of the fifth transistor and the sixth transistor are connected to the third transistor. and the collectors of the fourth transistor are connected, and the collectors of the seventh transistor and the eighth transistor are connected to the collectors of the first transistor and the second transistor,
and an in-phase output generation section that applies an in-phase component of the input signal to the multiplication output generation section and removes it.

[0011] In the invention according to claim 2, the first input terminal is connected to the base of the first transistor, the second input terminal is connected to the bases of the second transistor and the third transistor, and the second input terminal is connected to the base of the first transistor. A third input terminal is connected to the base of the transistor No. 4, a first constant current source is connected to the emitters of the first transistor and the second transistor, and a third input terminal is connected to the emitters of the third transistor and the fourth transistor. A second constant current source is connected to the third constant current source, a first resistance element is connected between each emitter, a first output terminal is connected to the collectors of the first transistor and the second transistor, and a first output terminal is connected to the collectors of the first transistor and the second transistor. A second output terminal is connected to the collectors of the transistor and the fourth transistor, and the collectors are connected via a second resistance element and a third resistance element, and a first output terminal is connected to the connection point of each resistance element. a multiplication output generation section connected to a constant voltage source of the input signal and outputting the multiplication output of the input signal to the first and second output terminals; A second constant voltage source is connected to the bases of the transistor and the seventh transistor via a fourth resistance element, the third input terminal is connected to the base of the eighth transistor, and the fifth transistor and a third constant current source is connected to the emitter of the sixth transistor, a fourth constant current source is connected to the emitters of the seventh transistor and the eighth transistor, and a fifth resistor is connected between each emitter. the collectors of the fifth and sixth transistors are connected to the collectors of the third and fourth transistors; the collectors of the seventh and eighth transistors are connected to the collectors of the seventh and eighth transistors; The present invention is characterized by comprising an in-phase output generation section that connects the collectors of the first transistor and the second transistor, and supplies and removes an in-phase component of the input signal to the multiplication output generation section.

0012

According to the present invention, by supplying two multiplication inputs at the same bias level, the multiplication output generation section can obtain an anti-phase input component and a multiplication output of the anti-phase input component and the in-phase input component. Further, the in-phase output generation section receives an anti-phase input component included in the output of the multiplication output generation section.

Therefore, by supplying the anti-phase input component from the in-phase output generation section to the multiplication output generation section, the multiplication output generation section can output only the multiplication output of the anti-phase input component and the in-phase input component. Note that this circuit can be configured with two vertically stacked transistors even when the constant current source is configured with a transistor and a resistor.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing an embodiment of the invention as set forth in claim 1. In the figure, transistors 11,
12, transistors 13, 14, transistors 15, 1
6. The transistors 17 and 18 form a differential pair, with the bases of the transistors 11 and 15 connected to the input terminal 20, the bases of the transistors 14 and 18 connected to the input terminal 21, and the bases of the transistors 12 and 13 connected to the input terminal 20. Each base is connected to an input terminal 22. Transistors 16, 17
Each base of is connected to a constant voltage source 24 via a resistor 23. The emitters of transistors 11 and 12 and the emitters of transistors 13 and 14 are connected via resistors 25 and 26, and a current source 27 is connected to the connection point of each resistor. The emitters of transistors 15 and 16 and the emitters of transistors 17 and 18 are connected to resistors 28 and 29.
A current source 30 is connected to the connection point of each resistor. The collectors of transistors 11 and 12 and the collectors of transistors 17 and 18 are connected to form a connection point A, and the collectors of transistors 13 and 14 are connected to the collectors of transistors 15 and 16 to form a connection point B.
shall be. Connection point A and connection point B each have output terminal 3.
1 and 32 are connected, and each connection point is connected to a resistor 33.
, 34, and a constant voltage source 35 is connected to the connection point of each resistor.

The analog multiplication operation of this embodiment will be explained below with reference to FIG. 2 showing the left half of the embodiment configuration of FIG. 1, and FIG. 3 showing its equivalent half circuit. In FIG. 3, Vin1 and Vin2 are the input voltages of the respective input terminals 20 and 21. RE is the resistance value of resistors 25 and 26,
RL is the resistance value of the resistor 33, and RS is the impedance of the constant current source 27. If rπ is the base-emitter voltage VBE of the transistor and the base current IB, then
It is a resistance where rπ=dVBE/dIB, and V1 and V2 are the voltages across rπ of each transistor. gm1 and gm2 are the transconductances of each transistor, I0 is the current flowing through the resistor 33, and iX
and iy are currents flowing through each rπ, and V0 is an output voltage taken out to the output terminal 31.

[0016] Here, Vin1=V1+(iX+gm1・V1)・RE
…(1) Vi
n2 =V2+(iy+gm2・V2)・(RE+RS
)...(2) V1 = iX・r
π
...(3) V2 = iy
・rπ
...(4) V0 =
-(gm1・V1+gm2・V2)・RL
...(5). therefore,
From equations (1) and (3), V1 = Vin1
/(1+(1/rπ+gm1)RE)
... (6), and according to equations (2) and (4), V2 = Vin2 / (1 + (1/rπ + gm
2)(RE+RS))...(7). From equation (5), if the thermal voltage is Vt, then V0
=-(I1・V1/Vt+I2・V2/Vt)・RL
=-(I0・V1/Vt+I2・V2/Vt
-gm2・V1・V2/Vt)・RL

…(8
). Substituting equations (6) and (7) into equation (8) and rearranging, we get V0 = - [(gm1+gm
2) RL・Vin1/(1+(1/rπ+gm1)RE
) +gm2・RL・Vin2 /(1
+(1/rπ+gm2)(RE+RS))
-gm2・RL・Vin1・Vin2/Vt(1+
(1/rπ+gm1)RE) ・(1+
(1/rπ+gm2)(RE+RS))]
≒-[(1+gm2/gm1)RL・Vin1/RE+
RL・Vin2/(RE+RS) −
RL・Vin1・Vin2/Vt・gm1・RE(RE
+RS)] … (9).

In equation (9), if RS >> RL, the second term becomes RL/(RE+RS) ≒0 and can be ignored, but the third term becomes Vt·gm1≒0, RE(RE+RS)
RS) >> 0, so the coefficient RL/Vt・gm1・
RE (RE+RS) becomes a value that functions as a gain depending on how RL is selected. Therefore, V0 =-
(1+gm2/gm1)RL・Vin1/RE
+RL・Vin1・Vin2/Vt・gm1・
RE (RE+RS) =-α・Vin1+β
・Vin1・Vin2
...(10). Note that α=(1
+gm2/gm1) RL/RE, and β=RL/Vt
・gm1・RE (RE+RS). In other words, it can be seen that the output of the left half of the circuit shown in FIG. 1 simultaneously contains the component of Vin1 on the anti-phase input side and the multiplication output component of Vin1 on the anti-phase input side and Vin2 on the in-phase input side. .

Therefore, in the differential circuit on the right half of the circuit in FIG. 1, the value of the constant voltage source 24 and the resistance values of the resistors 28 and 29 are adjusted, and an appropriate value of the negative phase component of the input voltage Vin1 is added. Therefore, Vin1 in the component of the output voltage V0
The components are removed, and only the multiplied output component of Vin1 on the anti-phase input side and Vin2 on the in-phase input side can be obtained. In such a configuration, even if the constant current sources 27 and 30 are composed of transistors and resistors, the number of vertically stacked transistors is two, making it possible to operate under a low voltage source.

FIG. 4 is a circuit diagram showing an embodiment of the invention according to claim 2. The feature of this embodiment is that the current sources for the transistors forming each differential pair in the configuration shown in FIG. Constant current sources 41, 42, 43, and 44 are connected to each differential pair, a resistor 45 is connected between constant current sources 41 and 42, and a resistor is connected between constant current sources 43 and 44. It is located where the device 47 is connected. Note that the operation as an analog multiplication circuit is the same as that described using FIGS. 1 to 3.

With this configuration, it is possible to reduce the voltage drop caused by the resistors 25, 26, 28, and 29. In other words, even lower voltage operation can be realized as an analog multiplier circuit. In addition, in the embodiment described above, an example was shown in which an NPN transistor was used as a bipolar transistor, but a PNP
The present invention can be similarly implemented using transistors.

[0021]

[Effects of the Invention] As explained above, in the present invention, the number of vertically stacked transistors can be two.
Even a constant voltage source of 2V or less can sufficiently perform the multiplication operation. Therefore, compared to conventional analog multiplication circuits, it is possible to achieve linearity over a wide input/output level range and a wide dynamic range.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the invention according to claim 1.

FIG. 2 is a circuit diagram showing the left half of the embodiment configuration of FIG. 1;

FIG. 3 shows an equivalent half-circuit of the circuit of FIG. 2;

FIG. 4 is a circuit diagram showing the configuration of an embodiment of the invention according to claim 2.

FIG. 5 is a circuit diagram showing a configuration example of a Gilbert cell used as a conventional analog multiplication circuit.

[Explanation of symbols]

11-18 Transistors 20-22 Input terminals 23, 25, 26, 28, 29, 33, 34, 45, 4
6 Resistors 24, 35 Constant voltage sources 27, 30, 41-44 Constant current sources 31, 32 Output terminals 51-54, 57, 58 Transistors 55, 56,
62, 63 Input terminals 59, 60, 66, 67 Resistor 61 Constant current sources 64, 65 Output terminal 68 Constant voltage source

Claims (2)

[Claims] Claim 1: A first input terminal is connected to the base of the first transistor, a second input terminal is connected to the bases of the second transistor and the third transistor, and a second input terminal is connected to the base of the fourth transistor. 3 input terminals are connected, and the emitters of the first transistor and the second transistor and the emitters of the third transistor and the fourth transistor are connected through a first resistive element and a second resistive element. At the same time, a first constant current source is connected to the connection point of each resistance element, and the first transistor and the second
Connect the first output terminal to the collector of the transistor,
A second output terminal is connected to the collectors of the third transistor and the fourth transistor, and the collectors are further connected through a third resistance element and a fourth resistance element, and a connection point of each resistance element. a multiplication output generation section that connects a first constant voltage source to the input signal and outputs multiplication outputs of the input signal to the first and second output terminals; and connects the first input terminal to the base of a fifth transistor. , a second constant voltage source is connected to the bases of the sixth transistor and the seventh transistor via a fifth resistance element, the third input terminal is connected to the base of the eighth transistor, and the third input terminal is connected to the base of the eighth transistor. emitters of a fifth transistor and a sixth transistor;
The emitters of the seventh transistor and the eighth transistor are connected via a sixth resistance element and a seventh resistance element, and a second constant current source is connected to the connection point of each resistance element, and The collectors of the fifth transistor and the sixth transistor are connected to the collectors of the third transistor and the fourth transistor, and the collectors of the seventh transistor and the eighth transistor are connected to the collectors of the first transistor and the second transistor. An analog multiplication circuit comprising: an in-phase output generation section connected to a collector of a transistor, and for applying an in-phase component of an input signal to the multiplication output generation section and removing it. 2. A first input terminal is connected to the base of the first transistor, a second input terminal is connected to the bases of the second transistor and the third transistor, and a second input terminal is connected to the base of the fourth transistor. A first constant current source is connected to the emitters of the first transistor and the second transistor, and a second constant current source is connected to the emitters of the third transistor and the fourth transistor. A first resistive element is connected between each emitter, a first output terminal is connected to the collectors of the first transistor and the second transistor, and the third transistor and the fourth transistor are connected. A second output terminal is connected to the collector of the resistor, and each collector is further connected through a second resistive element and a third resistive element, and a first constant voltage source is connected to the connection point of each resistive element. , a multiplication output generation unit that outputs a multiplication output of an input signal to the first and second output terminals; the first input terminal is connected to the base of a fifth transistor;
The second transistor is connected to the base of the transistor through the fourth resistance element.
a constant voltage source is connected, the third input terminal is connected to the base of the eighth transistor, a third constant current source is connected to the emitters of the fifth transistor and the sixth transistor, and the third constant current source is connected to the emitters of the fifth transistor and the sixth transistor. A fourth constant current source is connected to the emitters of the seventh transistor and the eighth transistor, and a fifth resistive element is connected between the respective emitters, and the collector of the fifth transistor and the sixth transistor is connected to the emitter of the eighth transistor. 3
the collectors of the seventh transistor and the fourth transistor are connected, and the collectors of the seventh transistor and the eighth transistor are connected to the first transistor and the collector of the fourth transistor.
an in-phase output generation section connected to the collector of the transistor, and for applying and removing an in-phase component of the input signal to the multiplication output generation section.