JPH04326440A - Error occurrence history storage device and information processor - Google Patents

Abstract

PURPOSE:To analyze the occurrence cause of a memory protection error. CONSTITUTION:An information fetch part 13 fetches an address which is outputted from a processor 1 through buses 7 and 9 and control information showing writing or reading. A comparison part 17 compares processor bus information 15 from the information fetch part 13 with a memory protection set point 16 from a register part 16, and outputs a match signal 20 when the address which is fetched into the information fetch part 13 is inputted to the range of the address which is held by a register part 14 and control information which is held by register part 14 matches with control information which is fetched by information fetch part 13. Thus, a control part 24 outputs a write stop signal 25 to a storage part 26 so as to stop the write operation of the storage part 26 and outputs a storage completion signal to the processor 1. If fetches the content from the storage part 26 and transfers it to a terminal equipment 3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device that provides information useful for analyzing the cause of a memory protect error when it occurs in an information processing device.

0002

2. Description of the Related Art In some types of conventional information processing apparatuses, memory protect errors have been dealt with as follows using the monitor function of the processor. That is, a register is provided to hold address information representing the address range to be protected and control information representing writing to memory, and the address and control information output to the processor bus are constantly compared with the contents of the register. If the address output to the bus falls within the above address range and the control information matches, the processor is notified of this using an interrupt signal, and if write protection is set, the write process is ignored. to prevent data from being written to memory. With such features,
Memory protect errors that cannot be determined when and to which addresses occur, and in particular, destruction of memory data due to write operations to write-protected areas are prevented.

0003

[Problem to be solved by the invention] However, such functions are limited to "memory protection error detection" and "memory protection error detection".
It prevents memory data from being destroyed by instantaneous post-processing such as "notifying the processor" and "missing write processing", and is useful for analyzing the cause of memory protection errors that occur and restoring the system. It's not something like that.

[0004] A first object of the invention is to provide an error occurrence history storage device that eliminates such drawbacks and makes it possible to analyze the causes of memory protection errors. Furthermore, it is an object of the second invention to provide an information processing apparatus that is capable of analyzing the causes of memory protection errors using the error occurrence history storage device of the first invention.

[0005]

[Means for Solving the Problems] An error occurrence history storage device according to a first aspect of the invention includes a storage means for taking in and storing data, addresses, and control information from a bus of a processor constituting an information processing device; a memory protect error detecting means that takes in the address and the control information, detects a memory protect error based on them, and outputs a predetermined signal; and when the memory protect error detecting means outputs the predetermined signal; The present invention is characterized by comprising a control means for stopping a write operation of the storage means.

An information processing device according to a second aspect of the invention includes a processor, a bus connected to the processor, storage means for taking in and storing data, addresses, and control information from the bus, and a storage means for taking in and storing data, addresses, and control information from the bus, and storing the data, addresses, and control information from the bus. a memory protect error detection means that takes in the control information, detects a memory protect error based on the control information, and outputs a predetermined signal; and when the memory protect error detection means outputs the predetermined signal, The present invention is characterized by comprising a control means for stopping a write operation, and a data retrieval means for retrieving the stored contents from the storage means when the storage means stops the write operation.

[0007]

[Example] Next, an example of the present invention will be described. Figure 1
An example of an information processing apparatus according to a second invention constructed using an example of an error occurrence history storage device according to the first invention is shown in FIG. This information processing device 6, which is a system under test, includes a processor 1 and an existing memory 4 of the system under test connected to the processor 1 by a data bus 8, an address bus 7, and a control bus 9, and further includes an error history storage device. 2. A terminal device 3 is connected to this information processing device 6, and the terminal device 3 has an RS232C
It is connected to the processor 1 through an interface 5.

The error history storage device 2 receives data, addresses, and data from the processor 1 through buses 7 to 9.
and a history storage unit 26 that captures and stores control information for each processing cycle of the processor 1, and a memory protection setting register that holds address information and control information representing a range of addresses and outputs them as memory protection setting values 16. a processor bus information import section 13 that takes in addresses and control information from the buses 7 and 9, respectively, and outputs them as processor bus information 15; and a register section 14 that receives processor bus information 15 and memory protection setting values 16; When the address fetched by the information capture section 13 falls within the range of addresses represented by the address information held by the register section 14, and the control information held by the register section 14 matches the control information fetched by the information capture section 13, a match occurs. A comparator 17 outputs a signal 20, and when this comparator 17 outputs a match signal 20, a write stop signal 25 is output and a memory unit 2
6 and outputs a storage completion signal to the processor 1. The storage device 2 also includes an LED 19 and an LED lighting control section 1.
8, and the control unit 18 is configured such that the comparison unit 17 receives the coincidence signal 20.
When output, the LED 19 lights up.

Next, the operation will be explained. First, register section 1
4 will be explained using the flowchart of FIG. At this time, the processor 1 operates according to the setting processing program 11. When the operator inputs address information representing a range of addresses to be memory protected and control information representing writing and/or reading from the terminal device 3, these are input to the processor 1 through the serial data signal line 12 and the interface 5. When processor 1 receives the information (step 20
1, 202), register section 14 through buffers 7 and 9.
It is output to and held (steps 203, 204).

When the register section 14 is set as described above, the error occurrence history storage device 2 operates as follows. That is, as shown in the flowchart of FIG.
The address output by the processor 1 and the control information representing writing or reading are taken in through the buffers 7 and 9 (step 301). The comparison unit 17 compares the processor bus information 15 from the information acquisition unit 13 and the memory protection setting value 16 from the register unit 16 (step 302), and determines whether the processor bus information 15 from the information acquisition unit 13 is within the range of the address represented by the address information held by the register unit 14 (step 302). contains the address fetched by the information fetching section 13, and when the control information held by the register section 14 and the control information fetched by the information fetching section 13 match, the match signal 20 is sent to the control section 18, processor 1, and output to the control unit 24 (step 30
3,305,307). As a result, the control section 18 outputs the lighting instruction signal 21 to light the LED 19 (step 304), thereby allowing the operator to know that a memory protect error has occurred. Further, the processor 1 starts processing for retrieving the contents from the storage unit 26 by the retrieval processing program 28. On the other hand, the control section 24
outputs the write stop signal 25 to the storage unit 26 (step 308), and then outputs the storage completion signal 27 to the processor 1 (step 310). When the storage unit 26 receives the write stop signal 25, it stops the write operation (step 309).

As shown in FIG. 4, when the processor 1 receives this signal 27 (step 401), it actually starts retrieving the storage content from the storage unit 26 and transfers it to the terminal device 3 (step 402). ). As a result, the storage unit 26 is protected for a certain period of time before a memory protection error occurs.
The data, address, and control information stored by the controller are displayed on the terminal device 3, and by viewing them, the cause of the error can be analyzed (step 403).

0012

Effects of the Invention As explained above, the error occurrence history storage device according to the first invention stores data, addresses, and control information output to the processor bus during a certain period before a memory protection error occurs. It has become. Therefore, by using the error history occurrence storage device of the first invention, when a memory protection error occurs, the cause of the occurrence of the memory protection error can be analyzed using the stored contents as history information of the processor operation. It becomes easier to restore the system after an error occurs.

[0013] Further, the information processing device of the second invention
Since the device is configured using the error occurrence history storage device invented by
Using the stored contents as history information of the processor operation, the cause of the memory protection error can be analyzed, and the system can be easily restored after the error occurs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an information processing device according to a second invention configured using an example of an error occurrence history storage device according to the first invention.

FIG. 2 is a flowchart showing operations when setting an error occurrence history storage device that constitutes the information processing apparatus of FIG. 1;

FIG. 3 is a flowchart showing the operation of an error history storage device that constitutes the information processing apparatus of FIG. 1;

FIG. 4 is a flowchart showing an operation when the processor of the information processing device in FIG. 1 retrieves history information from an error occurrence history storage device.

[Explanation of symbols]

1 Processor 2 Error history storage device 3 Terminal device 4 Existing memory of the system under test 5 RS232C interface 6 Information processing device 7 Address bus 8 Data bus 9 Control bus 11 Setting processing program 12 Serial data signal line 13 Processor bus information import unit 14 Memory Protect setting register section 17 Comparison section 18 LED lighting control section 19 LED 24 History storage control section 26 History storage section 28 Retrieval processing program

Claims (4)

[Claims] 1. A storage means for capturing and storing data, addresses, and control information from a bus of a processor constituting an information processing device; and a control means for stopping the write operation of the storage means when the memory protection error detection means outputs the predetermined signal. Features an error history storage device. 2. A processor, a bus connected to the processor, storage means for fetching and storing data, addresses, and control information from the bus, and a storage means for fetching and storing data, addresses, and control information from the bus; a memory protect error detecting means for detecting a memory protect error based on the memory protect error and outputting a predetermined signal; and a control means for stopping the write operation of the storage means when the memory protect error detecting means outputs the predetermined signal. An information processing apparatus comprising: data retrieval means for retrieving the stored contents from the storage means when the storage means stops writing operation. 3. The memory protection error detection means comprises:
register means for holding address information representing a range of said addresses and said control information; bus information import means for taking in said addresses and said control information from said bus; and a range of addresses represented by said address information held by said register means. and a comparison means for outputting the predetermined signal when the control information held by the register means and the control information fetched by the information capture means match. 2. The error occurrence history storage device according to claim 1, further comprising: an error occurrence history storage device; 4. The memory protection error detection means comprises:
register means for holding address information representing a range of said addresses and said control information; bus information import means for taking in said addresses and said control information from said bus; and a range of addresses represented by said address information held by said register means. and a comparison means for outputting the predetermined signal when the control information held by the register means and the control information fetched by the information capture means match. 3. The information processing apparatus according to claim 2, further comprising information setting means for causing said register means to hold said address information and said control information.