JPH04325993A - Memory card - Google Patents

Abstract

PURPOSE:To reduce the number of pins at the memory card by using the pin for designating the write enable and read enable of the memory card also as a pin for showing the high-order bit of a bit showing the address space of a memory. CONSTITUTION:Pins M0, M1, ST1 and ST2 at the memory card are set for designating high-order bits D-D as shown in the Figure. Thus, access can be performed until FFFFFFFF. It is also avaiable to provide the automatic increment mechanism of an address in the card for continuously reading/writing data on the address. Namely, after the address is once designated, each time the M1 and M0 are turned to (0,0), ST0(for the case of write) and ST1 (for the case of reading) to HI, the address is updated in the card and the data are read and written. Thus, a large memory space is accessed with the small number of pins.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to memory cards.

0002

[Prior Art] Currently, memory cards such as (JEI
Some devices have input/output pins of a type called DA Ver. 4.0).

0003

[Problem to be Solved by the Invention] However, in the above example, the number of pins is 68, so if it is attached to the camera body as a memory for a digital camera as an electronic device, the connector becomes large, or each pin There are problems such as reduced contact reliability.

[0004] In view of this point, an object of the present invention is to provide a memory card with improved reliability.

[0005]

[Means for Solving the Problems] In order to achieve the above-mentioned object, the memory card of the present invention uses a pin for specifying the write enable and read enable of the memory card as a pin for specifying the address space of the memory. A memory card that is characterized by:

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1(1) and 1(2) show a memory card according to an embodiment of the present invention, and show the types and functions of pins when a 20-pin memory card is used.

FIG. 2 shows the state of each pin for accessing the memory within the card.

FIG. 3 is a timing chart for data writing, FIG. 4 is a timing chart for data reading, and FIG. 5 is a timing chart for data reading.
6 shows an example of the contents of status 0.1, FIG. 6 shows an example of the memory map in the card, and FIG. 7 shows an example of card control data.

First, memory access within the card will be explained. In both writing and reading of data, addresses are specified by setting the M1, M0, ST1, and ST0 pins as shown in FIG. It is possible to access up to FFFFFFFF (HEX) which can be pointed with a maximum of 32 bits. For example, address FEDCBA98 (HEX) is 76 (H
When writing the data EX), the output of each pin can be controlled at the timing shown in Figure 3.

[0010] Also in the case of reading, the procedure shown in FIG. 4 may be used.

[0011] Address designation may be omitted depending on the memory capacity of the card. Further, an address auto-increment function may be provided in the card in order to continuously read and write data on the address. In other words, once you specify an address, the subsequent data will be M1, M
Set the 0 pin to (0,0) and ST0 (for writing),
Each time ST1 (for reading) is set to Hi, the address is automatically updated within the card, and data is read and written. Since this address auto-increment function is well known, detailed explanation will be omitted here.

The auto-increment function can be set or canceled by providing a mode register in the card, and writing a predetermined value into this register to switch the addressing mode.

Next, Read STATUS0 in FIG.
, 1 will be explained.

[0014] This is a register (memory) that can be read without addressing, and the card status is assigned to each bit. For example, as shown in Figure 5, E of bit 0 of STATUSO
R is an error bit that is set when some kind of error occurs in the card. Bits 1 to 3 RDY0, 1, and 2 are ready bits that indicate that writing has been completed or access is possible. Bits 4 to 6 are BL0 and 1. , 2 is a battery level bit indicating the degree of battery consumption in the case of a card with a built-in battery, and bit 7 EP is an erase protect bit indicating that the card is erased or write-protected.

[0015] ER0 to 3 of STATUS1 are STATUS
When the S0 ER bit is set, the error bit shows the specific details in detail, and the other bits are allocated as a reserve.

[0016] This makes it possible to read the card status as quickly as possible.

Next, memory allocation within the card will be described. An example of this memory map is shown in FIG.

Attribute data of the card is written in an area with a small address. In FIG. 6, an area of 100000H or less is temporarily allocated to the attribute data area, and the rest is used as the user data area. In this embodiment, even if different types of memories are mixed in the card, reading and writing is possible. That is, for example, SRAM is used as memory 1, PROM is used as memory 2,
Assume that the memory 3 includes a flash ROM. Each capacity is memory 1, 64K bytes, memory 2
is 1M byte, and memory 3 is 4M byte. Then, as shown in Figure 6, memory 1
, 2, 3.

In this case, the areas of memories 1 and 2, and areas 2 and 3 do not necessarily have to be continuously connected. For example, memory 1
from 100000 (HEX) to 10FFFF (HEX)
Up to 64K bytes Memory 2 is 200000 (HEX) to 2FFFF (H
EX) to 1M byte memory 3 is 300,000 (HEX) to 700,000 (
HEX) up to 4 Mbytes may be allocated.

In such a case, the type of memory and the start address and end address of the memory area are written in the attribute area as shown in FIG. One set of these is prepared for each type of memory. Therefore, as shown above, memory 1 and 2
, 3, if there are three, write the attributes for the three sets.

Then, for example, 1 byte of zero is set as the attribute information end code of each memory. In addition to the start and end addresses, access speed erase voltage, write and read voltages, etc. are written in this attribute area. All attribute data ends when the attribute end code is repeated twice.

When the card is inserted into the camera body as described above, by reading this attribute information, it is possible to immediately determine what type of memory it has and how much capacity it has. Based on this, reading and writing can be performed according to a predetermined memory management style.

(Other Embodiments) In this embodiment, a 20-pin card has been described, but other numbers of pins may be used.

Further, although the data bus is made 8 bits, it may also be any number of bits.

Depending on the type of memory, multiple power supplies may be required; in this case, pins for each power supply voltage may be provided.

Furthermore, the polarity of each pin during control does not have to be according to this embodiment. For example, in this embodiment, the card is enabled when CE is High, but it may be enabled when CE is Low. Status types other than those in this example can be added or changed as desired.

According to the present embodiment described above, the functions of address pins A0 to A25, write enable (WE), and output enable (OE) for the conventional memory space are shared, and four pins (card enable and This makes it possible to access a large amount of memory capacity only with

Therefore, by multiplexing the pin functions, it has become possible to access a large capacity memory space with a relatively small number of pins. Therefore, it has become possible to attach a large capacity memory card to a camera without impairing the reliability of pin contact or increasing the size of the connector.

[0029] It has also become possible to congest multiple types of memories within one card.

In this embodiment, the M0 and M1 pins are connected to D0 to D.
Although it is used as the upper bit of 7, it is not limited to this and may be a lower bit or another pin.

[0031]

As explained above, according to the present invention, the number of pins of a memory card can be reduced and reliability can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing examples of pin names and functions of a card implementing the present invention.

FIG. 2 is a diagram for explaining internal access functions of a card implementing the present invention.

FIG. 3 is a diagram showing an example of write timing for a card implementing the present invention.

FIG. 4 is a diagram showing an example of reading timing of a card implementing the present invention.

FIG. 5 is a diagram showing an example of status information of a card implementing the present invention.

FIG. 6 is a diagram showing an example of a memory map of a card implementing the present invention.

FIG. 7 is a diagram showing an example of an attribute area of a card implementing the present invention.

[Explanation of symbols]

D0 to D7 Bidirectional data bus M0, M Select input pin

Claims (2)

[Claims] 1. A memory card characterized in that a pin for specifying write enable and read enable of the memory card is also used as a pin for specifying an address space of the memory. 2. Claim 1, wherein the pin is a pin for specifying an upper bit of an address space.
memory card.