JPH04324956A - Semiconductor device - Google Patents

Abstract

PURPOSE:To effectively use all chip so as to enable a semiconductor device to be lessened in size and cost by a method wherein the wiring region of a signal wiring which links logic circuits each other is reduced to the irreducible minimum, and the logic circuit region is enlarged as much as possible. CONSTITUTION:A power supply wiring or a grounding wiring 2 is partially bent at an obtuse angle and laid along logic circuits 1A, 1B, 1C,... connected together in series. The power supply wiring or the grounding wiring 2 is bent, and in result, a recess is formed on the side opposite to the logic circuits 1A, 1B, 1C,.... Then, signal wirings 5 which connect the logic circuits 1B and 1C together are provided in the recess concerned. By this setup, the wiring region of signal wirings can be reduced to the irreducible minimum, so that a semiconductor device can be miniaturized and lessened in cost.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a novel wiring pattern, particularly for use as a pattern for a plurality of wirings connected to a logic circuit.

0002

2. Description of the Related Art Conventionally, a plurality of wires connected to a logic circuit are wired in a pattern as shown in FIG. 4, for example. In FIG. 4, a plurality of independent logic circuits 1A, 1B, 1C, . . . are arranged on a semiconductor substrate. A power supply wiring (or ground wiring) 2 is formed along the plurality of logic circuits 1A, 1B, 1C, . . . . Further, for example, the logic circuit 1A is connected to the logic circuit 1B by a signal wiring 3. The logic circuit 1B is connected to the logic circuit 1C by the signal wiring 4.
It is connected to the. Logic circuit 1C is again connected to logic circuit 1B by signal wiring 5. Here, the signal wiring 5 must be routed bypassing the logic circuit 1B,
Therefore, it is necessary to pass over the power supply wiring 2. Therefore,
When the signal wiring 5 passes over the power supply wiring 2, it is replaced by, for example, a diffusion layer wiring formed in a semiconductor substrate, a polysilicon wiring formed on the power supply wiring 2, or the like. Note that the signal wirings 3 to 5 are made of metal (for example, aluminum).
It consists of

However, in such a case, since the signal wiring 5 is routed around the logic circuit 1B, a separate wiring area is required, which has the disadvantage that the ratio of the wiring area to the entire chip area increases. Moreover, when considering the area surrounded by the broken line in FIG. 4, a blank area A in which nothing is formed is formed in the wiring area. This blank area A has the disadvantage that it becomes a wasted area because a logic circuit or the like cannot be formed therein. In addition, when the circuit pattern with the above configuration is formed continuously,
This blank area A becomes enormous and cannot be ignored.

[0004] Also, adjacent logic circuit 1A and logic circuit 1
For example, as shown in FIG.
There is a drawback that it is limited by the minimum interval C between the polysilicon interconnects 6 formed above. This is polysilicon wiring 6
This is due to the fact that the distance D1 between the top and the logic circuit 1A and the distance D2 between the bottom and the logic circuit 1B must be provided by a certain distance. This has the disadvantage that the ratio of the logic circuit area to the total area of the chip becomes small, which results in an increase in manufacturing costs. Note that 7 and 8 indicate metal wiring, respectively.

[0005]

[Problem to be solved by the invention] In this way, conventionally,
As the number of signal lines increases, the proportion of the wiring area in the overall chip area increases, and it has become virtually impossible to expand the logic circuit area.
There were drawbacks that hindered the miniaturization and cost reduction of semiconductor devices.

The present invention has been made in order to solve the above-mentioned drawbacks, and it is possible to minimize the wiring area of signal wiring connecting a plurality of logic circuits to each other, eliminate so-called blank areas, and further increase the logic circuit area. The aim is to effectively utilize the entire chip by expanding the size of the chip as much as possible, thereby achieving smaller size and lower cost of semiconductor devices.

[0007]

[Means for Solving the Problems] In order to achieve the above object, a semiconductor device of the present invention includes a plurality of logic circuits connected in series, a part of which is wired along the plurality of logic circuits, and a semiconductor device of the present invention. a power supply or ground wiring that is bent at an obtuse angle, and a recess formed on the power supply or ground wiring and on the side opposite to the plurality of logic circuits by the bend of the power supply or ground wiring; The logic circuit includes a plurality of signal wirings that connect the logic circuit and other logic circuits.

[0008]

[Function] According to the above configuration, a part of the power supply or ground wiring is bent at an obtuse angle, and one logic circuit is placed in the recess formed on the opposite side of the plurality of logic circuits due to the bend. A plurality of signal wirings are wired to connect the logic circuit and other logic circuits. As a result, it is possible to minimize the wiring area of signal wirings that interconnect a plurality of logic circuits, eliminate blank areas, and effectively utilize the entire chip.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 schematically shows a circuit pattern of a semiconductor device according to an embodiment of the present invention. In FIG. 1, in order to make the explanation easier to understand, FIG.
The same reference numerals are given to the corresponding parts. Also,
With the power supply wiring 2 as a reference, the side on which the logic circuit is arranged will be referred to as the inside, and the opposite side will be referred to as the outside.

A plurality of independent logic circuits 1A, 1B, 1C, . . . are connected in series by signal wirings 3, 4 on the semiconductor substrate. Multiple logic circuits 1A, 1B, 1C
The power supply wiring 2 is wired along... So far,
Same as before. However, the power supply wiring 2 does not extend linearly as in the conventional case, but is partially bent at an obtuse angle. Furthermore, as a result of bending a portion of the power supply wiring 2, a recessed portion is formed on the outside of the power supply wiring 2. The signal wiring 5 is wired in this recessed portion, and the wasteful wiring area (blank area) that conventionally existed can be eliminated. on the other hand,
Inside the power supply wiring 2, the useless wiring area can be completely incorporated into the logic circuit area (for example, area D). This makes it possible to eliminate unnecessary wiring areas and expand the logic circuit area.

[0012] In FIG. 1, the part surrounded by a broken line is shown in FIG.
This corresponds to the part surrounded by the broken line. That is, in the present invention, the conventional blank area A formed outside the power supply wiring can be eliminated, and a new area D can be formed in the logic circuit area.

Furthermore, the distance B between the logic circuit 1A and the logic circuit 1B, which was conventionally limited to the minimum distance between the polysilicon wirings on the power supply wiring, can be further reduced by adopting a configuration as shown in FIG. 2, for example. Can be done. That is, it is clear from the resistance value that the width of the metal wiring 7 is narrower than the width of the polysilicon wiring 6. Therefore, the mutual spacing between the plurality of metal wires 7 wired between the logic circuit 1A and the logic circuit 1B is reduced to the minimum. Note that it is effective to wire the plurality of metal wires 7 in a stepwise manner. In this way, the distance B between the logic circuit 1A and the logic circuit 1B is limited to the maximum by the minimum distance C' between the metal wirings 7. In other words, the distance between the logic circuit 1A and the logic circuit 1B can be reduced by C-C' at the maximum compared to the conventional one. This allows the logic circuit area to be further expanded. In FIG. 2, the position of the logic circuit 1A can be appropriately selected depending on the size of the logic circuit 1A, the number of signal wirings, the method of supplying power, and the like.

[0014]

As described above, the semiconductor device of the present invention provides the following effects.

The chip area can be made sufficiently small by minimizing the wiring area of the signal lines that interconnect multiple logic circuits, eliminating so-called blank areas, and further expanding the logic circuit area as much as possible (FIG. 3). reference)
, miniaturization and cost reduction of semiconductor devices can be achieved.

[Brief explanation of drawings]

FIG. 1 is a plan pattern diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a planar pattern diagram of a semiconductor device according to another embodiment of the present invention.

FIG. 3 is a diagram showing the effects of the present invention.

FIG. 4 is a planar pattern diagram of a conventional semiconductor device.

FIG. 5 is a planar pattern diagram of a conventional semiconductor device.

[Explanation of symbols]

1A, 1B, 1C...: Logic circuit, 2: Power supply wiring, 3, 4
, 5: Signal wiring, 6: Polysilicon wiring, 7, 8: Metal wiring.

Claims (5)

[Claims] [Claim 1] A plurality of logic circuits connected in series;
A power supply or ground wiring that is wired along the plurality of logic circuits and a part of which is bent at an obtuse angle, and a power supply or ground wiring that is formed on the side opposite to the plurality of logic circuits by bending the power supply or ground wiring What is claimed is: 1. A semiconductor device comprising: a plurality of signal wires that are wired at least in a recessed portion and connect one logic circuit to another logic circuit. 2. The plurality of signal wirings include a plurality of polysilicon wirings routed on the power supply or ground wiring;
a plurality of first metal wires wired in a recess formed on a side opposite to the plurality of logic circuits by bending the power supply or ground wire; one end connected to the plurality of polysilicon wires; 2. The semiconductor device according to claim 1, further comprising a plurality of second metal wirings whose ends are connected to a predetermined logic circuit and which are wired in a stepped manner from the one end side to the other end side. . 3. The plurality of signal wirings are formed on a side opposite to the plurality of logic circuits by a plurality of diffusion layer wirings formed under the power supply or ground wiring and bending of the power supply or ground wiring. a plurality of first metal wirings wired in the recessed portions, one end of which is connected to the plurality of diffusion layer wirings;
2. The semiconductor according to claim 1, further comprising a plurality of second metal wirings whose other ends are connected to a predetermined logic circuit and which are wired in a stepped manner from the one end side to the other end side. Device. [Claim 4] A plurality of logic circuits connected in series;
A power supply or ground wiring line that is routed along the plurality of logic circuits, a plurality of polysilicon wirings that are routed on the power supply or ground wiring, one end of which is connected to the plurality of polysilicon wirings, and the other end of which is connected to the plurality of polysilicon wirings; 1. A semiconductor device comprising: a plurality of metal wires connected to a predetermined logic circuit and wired in a stepped manner from the one end side to the other end side. [Claim 5] A plurality of logic circuits connected in series;
A power supply or ground line wired along the plurality of logic circuits, a plurality of diffusion layer wirings formed under the power supply or ground wirings, one end connected to the plurality of diffusion layer wirings, and the other end connected to the plurality of diffusion layer wirings. 1. A semiconductor device comprising: a plurality of metal wires connected to a predetermined logic circuit and wired in a stepped manner from the one end side to the other end side.