JPH04323866A - Mos static memory cell - Google Patents

Abstract

PURPOSE:To reduce in size a chip by employing transfer transistors as thin films transistors and laminating them. CONSTITUTION:Driving transistors in which load transistors Q3, Q4 of CMOS SRAM are formed on a semiconductor substrate, and a gate electrode 5 are shared for use. Further, a silicon thin film 13 is provided, and sources, drains of the Q3, Q4 are formed. In addition, source, drains of transfer transistors Q5, A6 are provided on a silicon thin film 13, and a gate electrode (word line 16) is laminated thereon.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to MOS static RA
Regarding M, particularly the structure of a MOS static memory cell.

0002

2. Description of the Related Art In recent years, semiconductor integrated circuit devices have become significantly larger in capacity, higher in density, and faster in speed.

It is no exaggeration to say that the basis of this remarkable performance improvement, particularly in devices such as memories, which are composed of repeated cells, lies in the design of the cells. For example, simply by making the memory cells smaller, it is possible to increase capacity, reduce chip size, increase speed, and reduce power consumption all at once.

Here, the conventional configuration of a MOS static memory cell, which has a large cell size among memory devices,
Explain the structure. FIG. 11 is a plan view showing the transistor arrangement of a conventional MOS static memory cell. In the figure, MOS transistors QA and QB are memory cell driving transistors. QC and QD are transistors for transmitting cell data, and contact holes 2
0 and 21 to a high-resistance element (not shown) for supplying a high potential reference voltage (hereinafter referred to as VDD) disposed in the upper layer, and connected to a bit line (not shown) through contact holes 22 and 23. There is. Considering the dimensional margin at the design level with a minimum dimension standard of 0.8 μm, the contact holes 22 and 23 have a width of 0.5 μm between the transistor parts QC and QD for connection with the bit line (metal wiring) in the upper layer. ~1μ
Since QA and AB have a channel width of 1 μm and a channel length of approximately 1 μm, the contact hole 23
, 24 are shared with adjacent cells, the length of the area E indicated by the dotted line in the long side direction of the cell is 2 to 3 μm. On the other hand, the long side size of the memory cell is 0.8
Since it is about 8 to 9 μm according to the μm rule, the proportion of the E section in the memory cell is about 30%.

In addition, in recent years, MOS static memory cells using thin film transistors (TFT) have been published in the International Journal of Solid State Circuits (
IEEE JOURNAL OF SOLID-
STATE CIRCUITS), Vol. 24, No. 6, December 1989, pages 1708 to 1713, etc. This is also similar to the conventional example described above, in which memory cells are placed on the surface of a semiconductor substrate. Since both a transfer transistor and a drive transistor are formed, a region corresponding to the portion E in FIG. 6 is included in the memory cell.

Next, MOS is a three-dimensional device that has recently been attracting attention as an approach to increasing the density of integrated circuit devices.
Figure 1 shows a conceptual diagram of a proposed example applied to static RAM (1985 Spring Proceedings of the Japan Society of Applied Physics, 30p-C-12).
Shown in 2. Here, the MOS static RAM is divided into a memory cell part and a peripheral circuit part, and is divided into a lower layer and an upper layer IC.
Memory cell data is arranged in each layer, and memory cell data is transferred between the upper and lower layers.
Decoded signals are exchanged. In this way, this type of device is characterized by the ability to electrically separate the upper and lower layers to form independent circuits on the upper and lower layers. In addition to the need to provide a completely planarized insulating layer, the transistor manufacturing process is performed separately for the upper and lower layers, making the lamination technology very complex and difficult, and it is difficult to form contact holes between the upper and lower layers. In addition, the chip area reduction rate cannot be greater than the cell occupation area in a single layer, and there is an inherent contradiction in reduction efficiency in that if the cell occupation area increases due to high density, the chip area reduction rate decreases. ing.

[0007]

As described above, in the conventional MOS static memory cell, since the transfer transistor of the memory cell is formed in the same layer as the drive transistor, the transfer portion (section E in FIG. 6) 30% of the cell area
This fact is hindering the reduction of chip area. In addition, when trying to reduce the chip area using three-dimensional devices, it is necessary to overcome the complicated and difficult stacking technology.
There is a problem in that it is necessary to optimize the chip area reduction efficiency.

[0008]

Means for Solving the Problems The present invention provides a first drive transistor whose drain is connected to a first node, whose gate is connected to a second node, and whose source is connected to a first power source that supplies a reference potential. and a second drive transistor having a drain connected to the second node, a gate connected to the first node, and a source connected to the first power supply, the drain connected to the first node, and the gate connected to the first node. A first load transistor having a source connected to the second power source is connected to the second node, a drain is connected to the second node, and a gate is connected to the first load transistor.
a second load transistor having a source connected to the second power supply, a drain connected to the first bit line, a gate connected to the word line, and a source connected to the first node; A MOS static memory cell having a first transfer transistor and a second transfer transistor having a drain connected to a second bit line, a gate connected to the word line, and a source connected to the second node. , the sources or drains of the first and second drive transistors are formed on the surface of the semiconductor substrate, and the sources or drains of the first and second load transistors and the first and second transfer transistors are formed on the surface of the semiconductor substrate. The source or drain is formed on a silicon thin film provided on the semiconductor substrate with an insulating film interposed therebetween.

[0009]

[Embodiment] Fig. 1 is a plan view showing an embodiment of the present invention, Fig. 2
1 is a sectional view taken along the line AA in FIG. 1, and FIG. 3 is a sectional view taken along the line BB in FIG. Further, FIG. 4 is a circuit diagram of one embodiment. FIG. 5 is a plan view of a transfer transistor section in one embodiment, and FIG. 6 is a plan view of a load transistor section in one embodiment.

Referring to FIGS. 1 to 6, this embodiment:
The drain is connected to the first node N1, and the gate is connected to the second node N2.
, a first drive transistor Q1 whose source is connected to a first power supply supplying a reference potential GND, a drain connected to a second node N2, a gate connected to a first node N1, and a source connected to a first power supply. (GND) respectively connected to
drive transistor Q2 whose drain is connected to the first node N1
, the gate is connected to the second node N2, and the source is connected to the second power supply V
first load transistors Q3 each connected to CC;
and a second load transistor Q4 whose drain is connected to the second node N2, whose gate is connected to the first node N1, and whose source is connected to the second power supply VCC, whose drain is connected to the first bit line, and whose gate is connected to the first bit line. is connected to the word line 16, and the source is connected to the first node N1.
5 and a second transfer transistor Q6 whose drain is connected to the second bit line 16, whose gate is connected to the word line 16, and whose source is connected to the second node N2. and second drive transistor Q
1, the source or drain of Q2 is a P-type silicon substrate 1
The sources or drains of the first and second load transistors Q3, Q4 and the sources or drains of the first and second transfer transistors Q5, Q6 are formed on the (P-type silicon) substrate 1. It is formed on a silicon thin film 13 provided through an insulating film (gate oxide film 4, interlayer insulating films 7, 14).

Next, a manufacturing method of one embodiment will be explained.

First, as shown in FIGS. 7(a) and 7(b),
A field oxide film 2 is selectively formed on the surface of a P-type silicon substrate 1 to define active regions 3. A gate oxide film 4 is formed on the active region 3, an opening is made at a predetermined location (6), a gate electrode 5 is formed, and a source/drain region (N-type diffusion layer (18 in FIG. 3)) is formed by ion implantation. form. In this way, the memory cell drive transistors Q1, Q
2 are formed, and the drain portions of both are connected to the gate electrode of the other. Next, as shown in FIGS. 8(a) and 8(b), a second wiring layer (tungsten silicide film) is formed and patterned to form a ground potential (hereinafter referred to as GND) wiring 9 and a VDD wiring 8. establish. At this time, the source portions of the transistors Q1 and Q2 are connected to the GND wiring 9 via the contact hole 11. In addition, interlayer insulating films 7, 1
0 is formed by a low-pressure CVD method so that the total thickness of both films is uniform at several tens of nanometers. Next, FIG. 9(a)
), (b), a silicon thin film 13 is formed. This silicon thin film 13 is produced by depositing a polysilicon thin film and by a melt recrystallization method, and is patterned as shown in FIG. 9(a). Further, a low concentration of phosphorus is introduced into the silicon thin film in advance. Furthermore, in regions other than region C, after laminating and patterning the wiring layer (polycrystalline silicon film) of the word line 16 as shown in FIGS. 1 and 2, high concentration boron is selectively introduced using a resist film. Ru. The sources of Q3 and Q4 are connected to VD through the contact hole 15.
The drain is connected to Q2 through the contact hole 12 to the D wiring 8.
, Q1, respectively. Further, gate control of Q3 and Q4 is performed by the lower layer gate electrode 5 as shown in FIG. Further, gate control of Q3 and Q4 is performed by the lower layer gate electrode 5 as shown in FIG. That is, the gate potentials of transistors Q3 and Q4 will be equal to the gate potentials of Q1 and Q2, respectively, and will be connected as load transistors of the memory cell. On the other hand, as shown in FIGS. 1 and 5, the transistor Q provided in the silicon thin film 13 directly under the word line
5, Q6 uses the word line as the gate, and the source part is Q3,
It has the same potential as Q4. Although not shown in each figure, by providing a bit line with metal wiring in the upper layer and connecting it to the drains of transistors Q5 and Q6 through contact holes 17, the circuit configuration shown in FIG. 4 is obtained with this structure. Note that the gate insulating films of Q3 and Q4 are interlayer insulating films 7 and 10.
The gate insulating film of Q5 and Q6 is an interlayer insulating film 14. Here, the transmission transistors Q5 and Q6 of the memory cell are P-type MOS transistors, but by selecting the word line with the word potential "Low" and setting the bit line "Low" to perform the read operation, it is possible to It is clear that the operation is equivalent to that of a memory cell using an N-type MOS transistor as a transfer transistor.

The area of the memory cell of this embodiment can be reduced by about 30% compared to the area of the conventional memory cell described above, since the portion corresponding to FIG. 11 is provided on the upper layer of the semiconductor substrate. Further, it does not require complicated processes unlike three-dimensional devices.

The case where Q1 and Q2 are N-type MOS transistors and Q3, Q4, Q5, and Q6 are P-type MOS transistors has been described above, but as shown in FIG. By introducing a low concentration of boron (introducing a low concentration of phosphorus into the regions other than D of the silicon thin film 13) and introducing arsenic into the region D after word line patterning, Q5 and Q6 are made into N-type MOS transistors. It can be done. In this case, areas C and D
Boron is introduced into the other silicon thin films 13.

[0015]

[Effects of the Invention] As explained above, according to the present invention,
The transfer transistor of the memory cell can be provided on the upper layer of the semiconductor substrate without using complicated steps, and the area of the conventional memory cell can be reduced by about 30%. This contributes to a reduction in chip size and, in turn, can improve chip performance.

[Brief explanation of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA in FIG. 1;

FIG. 3 is a sectional view taken along the line BB in FIG. 1;

FIG. 4 is a circuit diagram of one embodiment.

FIG. 5 is a plan view showing a transfer transistor section in one embodiment.

FIG. 6 is a plan view showing a load transistor section in one embodiment.

FIG. 7 is a plan view (
FIG. 7(a)) and a cross-sectional view (FIG. 7(b)).

FIG. 8 is a plan view (
FIG. 8(a)) and a cross-sectional view (FIG. 8(b)).

FIG. 9 is a plan view (
FIG. 9(a)) and a cross-sectional view (FIG. 9(b)).

FIG. 10 is a plan view used to explain a modification of one embodiment.

FIG. 11 is a plan view used to explain the prior art.

FIG. 12 is a conceptual diagram used to explain the prior art.

[Explanation of symbols]

1 P-type silicon substrate 2 Field oxide film 3 Active region 4 Gate oxide film 5, 51, 52 Gate electrode (of Q1, Q2) 6
Gate electrode-N type diffusion layer connection part 7 Interlayer insulation film 8 VDD wiring 9 GND wiring 10 Interlayer insulation film 11 Contact hole 12 between GND wiring 9 and N type diffusion layer Contact hole 13 between gate electrode 5 and silicon thin film 13 Silicon thin film 14 Interlayer insulating film 15 Contact hole 16 between VDD wiring 8 and silicon thin film 13 Word line 17 Contact hole 18 between bit line and silicon thin film 1 N-type diffusion layer 19 Active region

Claims (5)

[Claims] 1. A first drive transistor having a drain connected to a first node, a gate connected to a second node, and a source connected to a first power supply supplying a reference potential; a second drive transistor having a gate connected to the first node and a source connected to the first power supply; a drain connected to the first node; a gate connected to the second node; are connected to a second power source, and a second load transistor has a drain connected to the second node, a gate connected to the first node, and a source connected to the second power source. a load transistor; a first transistor having a drain connected to the first bit line, a gate connected to the word line, and a source connected to the first node;
a transfer transistor whose drain is connected to the second bit line,
A MO comprising a second transfer transistor having a gate connected to the word line and a source connected to the second node.
In the S static memory cell, the sources or drains of the first and second drive transistors are formed on the surface of the semiconductor substrate, and the sources or drains of the first and second load transistors and the A MOS static memory cell characterized in that sources or drains of the first and second transfer transistors are formed on a silicon thin film provided on the semiconductor substrate with an insulating film interposed therebetween. 2. The MOS static memory cell according to claim 1, wherein the sources or drains of the first and second load transistors and the source or drain of the second transfer transistor are formed in the same silicon thin film. 3. The gate electrodes of the first and second load transistors are made of the same layer as the gate electrodes of the first and second drive transistors, and the gate electrodes of the first and second transfer transistors are made of the same layer as the gate electrodes of the first and second drive transistors. 2. The MOS static memory cell according to claim 1, further comprising a conductor layer provided over a silicon thin film on which the drain is formed, with an insulating film interposed therebetween. 4. The M according to claim 1, wherein the first and second drive transistors are N-type MOS transistors, and the first and second load transistors are P-type MOS transistors.
OS static memory cell. 5. The MOS static memory cell according to claim 1, wherein the first and second transfer transistors and the first and second drive transistors are N-type MOS transistors.