JPH043228A - Error correcting circuit for computing element - Google Patents

Abstract

PURPOSE:To prevent the deterioration of a function of a system incorporating a computing element even if an error is generated by operating in parallel plural computing elements having an error detecting circuit, and selecting the output of the computing element in which an error is not detected by using each detecting signal of the error detecting circuit. CONSTITUTION:Each of plural computing elements 1, 2 is provided with error detecting circuits 3, 4, plural computing elements 1, 2 are operated in parallel, and a means 6 for selecting and outputting the output of the computing element in which an error is not detected in the computing elements 1, 2 by using output signals of the error detecting circuits 3, 4 is provide. In this case, a control signal is sent from a control circuit 5 to a selector 6 so that when an error is detected in only the error detecting circuit 3, the output of the computing element 2 is selected and outputted by the selector 6, and when an error is detected in only the error detecting circuit 4, the output of the computing element 1 is selected and outputted by the selector 6. In such a manner, it can be prevented that the function of the whole system incorporating the computing elements stops remarkably due to the generation of an error.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an error correction circuit for an arithmetic unit, and in particular, uses error detection information of an error detection circuit to select and output an arithmetic unit output with no error Q. This invention relates to an error correction circuit for an arithmetic unit.

(Prior Art) Conventionally, error p-check ratio circuits have been known as a countermeasure against errors in arithmetic units often used in information processing equipment and the like, but there is no method for correcting errors.

(The problem to be solved by the invention is that the above-mentioned conventional arithmetic unit only detects errors using an error detection circuit and does not have a correction function.

The disadvantage is that the function of the entire system including the computing unit is significantly degraded due to the occurrence of an error.

The object of the present invention is to eliminate such drawbacks.

An object of the present invention is to provide an error correction circuit for an arithmetic unit in which the function of a system including the arithmetic unit does not deteriorate even if an error occurs.

(Ninth means for solving <-"i@) In order to achieve the above object, the error 9 correction circuit of the arithmetic unit of the present invention includes an error p detection circuit 3.2 for each of the plurality of arithmetic units 1.2. A plurality of arithmetic units 1.2t are operated in parallel, and using the output signal of the error detection circuit 3.4, the arithmetic units 1.2t-4 are operated in parallel.
2, the configuration includes means 6 for selecting and outputting the output of the arithmetic unit in which no error has been detected.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The embodiment shown in FIG. 1 is a case in which the arithmetic units 1 and 2t are operated in parallel, and an error force detection circuit 3 detects vAp in the arithmetic operation of the arithmetic unit 1 and detects an error in the arithmetic operation of the arithmetic unit 2. There is an erroneous force detection circuit 4 that does this.

There is also a selector 6 that switches and outputs the outputs of the arithmetic units 1 and 2, and an erroneous force control circuit 5 that inputs the outputs of the erroneous force detection circuits 3 and 4 and controls the selector 6.

Note that 7.8 is an operand register and %9 is a result register.

Next, the operation will be explained.

When the square and operand are set in the registers 7 and 8, the error control circuit 5 is activated.

Next, arithmetic unit 1. The arithmetic unit 2 starts all calculations using the value of the f''LL parallel disk 7 and disk 8, respectively.

Also, the error force detection circuit 3. The error detection circuit 4 detects errors in the calculation results of the arithmetic unit 1 and the arithmetic unit 2, respectively. The error force control circuit 5 monitors each error detection signal from the error detection circuit 3 and the error detection circuit 4 at the timing when the operation of the arithmetic unit 11 and the arithmetic unit 2 is completed.

At this time, the error detection circuit 3. If no error is detected in either of the error detection circuits 4, the selector 6 continues to output the arithmetic unit output selected so far, and if an error is detected only in the error detection circuit 3, the selector 6 outputs the output of the arithmetic unit 2. 6 selects and outputs, and if only vA detection circuit 4 detects an error,
A control signal is sent from the error control circuit 5 to the selector 6 so that the selector 6 selects and outputs the output of the arithmetic unit 1. Also, the error detection circuit 3. When the error detection circuit 4 detects an error 9, an uncorrectable signal is sent from the error control circuit 5 to an operation section of the system (not shown).

(Effects of the Invention) As explained above, the present invention operates a plurality of arithmetic units having an error detection circuit in parallel, and uses the detection signal of each of the error detection circuits to detect an error in the arithmetic unit that is not detected. By selecting the output of , it is possible to correct errors that were not possible with conventional arithmetic units.

Therefore, by using this method, the functionality of the entire system including the computing unit can be greatly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1.2... Arithmetic unit 3.4... Error detection circuit 5.
...vA control circuit 6...Selector 7.8.9
...Register fang] Figure patent applicant NEC Corporation

Claims (1)

[Claims] Each of the plurality of arithmetic units is provided with an error detection circuit, the plurality of arithmetic units are operated in parallel, and the output signal of the arithmetic unit in which no error is detected is determined by using the output signal of the error detection circuit. An error correction circuit for an arithmetic unit, comprising means for selecting and outputting.