JPH04322514A - Oscillation circuit - Google Patents

Oscillation circuit

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Publication number
JPH04322514A
JPH04322514A JP3116623A JP11662391A JPH04322514A JP H04322514 A JPH04322514 A JP H04322514A JP 3116623 A JP3116623 A JP 3116623A JP 11662391 A JP11662391 A JP 11662391A JP H04322514 A JPH04322514 A JP H04322514A
Authority
JP
Japan
Prior art keywords
circuit
terminal
output
resistor
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3116623A
Other languages
Japanese (ja)
Inventor
Kiminari Tamiya
公成 田宮
Satoshi Sasaki
智 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP3116623A priority Critical patent/JPH04322514A/en
Publication of JPH04322514A publication Critical patent/JPH04322514A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To obtain a triangle wave oscillation circuit whose oscillated waveform is subjected to optional DC, shift, whose circuit scale is not increased and whose output is connected to a next stage. CONSTITUTION:The 1st output terminal of a current control circuit 2 is connected to the noninverting terminal of a comparator 1 and to a reference voltage source 4 via a 1st resistor 3, and the 2nd output terminal of a current control circuit 2 and a capacitor 6 are connected to the inverting terminal of the comparator 1 to form the triangle wave oscillation circuit. A 1st transistor(TR) 12 whose base and collector are short-circuited is provided between the noninverting terminal of the comparator 1 and the 1st resistor 3. A 1st power supply circuit 14 is connected between the power supply and the noninverting terminal. The inverting terminal and the base of a 2nd TR 13 are connected, the collector is connected to the power supply and the emitter is connected to a 2nd power supply circuit 15. A 2nd resistor 16 is provided between the emitter of a 2nd TR 13 and the 2nd current source 15. The oscillating waveform is subjected to optical DC shift, the result is extracted and the oscillation circuit is connected to a next stage.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は三角波を発振する発振回
路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit that oscillates a triangular wave.

【0002】0002

【従来の技術】図5は従来の三角波を発振する回路の一
例の構成を示す図である。図5に示す例において、コン
パレータ1の非反転端子には、コンパレータ1の出力が
“H”になれば、電流I1 が流れ、出力が“L”にな
れば電流I2 が流れる電流制御回路2の出力1が接続
され、抵抗3を介して基準電圧4が接続されている。一
方、反転端子には、コンパレータ1の出力が“H”にな
れば電流I3 が流れ、出力が“L”になれば電流I4
 が流れる電流制御回路2の出力2が接続され、コンデ
ンサ6が接続され、反転端子とコンデンサ6間に出力端
子7が接続された構成をとっている。
2. Description of the Related Art FIG. 5 is a diagram showing the configuration of an example of a conventional triangular wave oscillating circuit. In the example shown in FIG. 5, when the output of comparator 1 becomes "H", current I1 flows through the non-inverting terminal of comparator 1, and when the output becomes "L", current I2 flows through the non-inverting terminal of current control circuit 2. Output 1 is connected, and reference voltage 4 is connected via resistor 3. On the other hand, current I3 flows to the inverting terminal when the output of comparator 1 becomes "H", and current I4 flows when the output becomes "L".
is connected to the output 2 of the current control circuit 2 through which the current flows, a capacitor 6 is connected, and an output terminal 7 is connected between the inverting terminal and the capacitor 6.

【0003】次に、図5に示す従来回路の動作について
以下に述べる。図5において、電源を印加した瞬間、出
力端子7の電圧vC はコンデンサ6が充電されていな
いから、vC =0と考える。よって、19の電圧vR
 とvC の関係はvR >vC であるから、コンパ
レータ1の出力は“H”レベルとなる。このとき電流I
1 が流れ、19の電圧vRHは、 vRH=VREF +R1 I1     −−−−−
−(1)となる。また電流I3 により、コンデンサ6
が充電される。この充電によりvC の電位がしだいに
上昇し、vRHの値を越えると、コンパレータ1の出力
電圧は“L”レベルになる。このとき電流I2 が流れ
る。よって19の電圧vRLは、 vRL=VREF −R1 I2         −
−−−−−(2)となる。また、コンデンサ6は電流I
4 によって放電状態となり、vRL>vC となると
、コンパレータの出力が“H”となり、上記同様の動作
をくり返す。このように、コンデンサ6の充放電で、図
6に示すように、vRHからvRL間で三角波を発振す
る。また、コンデンサC、抵抗R1,I1,I2,I3
,I4 により、三角波のスレッシュホールド、発振周
波数を決めることができる。このとき発振周波数fは、 となる。
Next, the operation of the conventional circuit shown in FIG. 5 will be described below. In FIG. 5, the voltage vC at the output terminal 7 is considered to be 0 at the moment when the power is applied because the capacitor 6 is not charged. Therefore, the voltage vR of 19
Since the relationship between and vC is vR > vC, the output of comparator 1 becomes "H" level. At this time, the current I
1 flows, and the voltage vRH of 19 is: vRH=VREF +R1 I1 -------
−(1). Also, due to the current I3, the capacitor 6
is charged. Due to this charging, the potential of vC gradually rises, and when it exceeds the value of vRH, the output voltage of comparator 1 becomes "L" level. At this time, current I2 flows. Therefore, the voltage vRL of 19 is: vRL=VREF −R1 I2 −
-----(2). Also, the capacitor 6 has a current I
4, it enters a discharge state, and when vRL>vC, the output of the comparator becomes "H" and the same operation as above is repeated. In this way, by charging and discharging the capacitor 6, a triangular wave is oscillated between vRH and vRL, as shown in FIG. Also, capacitor C, resistors R1, I1, I2, I3
, I4, the threshold and oscillation frequency of the triangular wave can be determined. At this time, the oscillation frequency f is as follows.

【0004】0004

【発明が解決しようとする課題】しかし、上述した従来
の発振回路では、端子7に流れる電流の出入が無視でき
ないような回路が接続された場合、発振波形が変化する
。そのため、端子7を次段へつなぐことができない問題
があった。そこで図7に示すように、端子7をエミッタ
フォロワで端子8に出力することが考えられる。しかし
ながらこの方法では、発振周波数は変化しないが、端子
7の電圧をVout1、端子8の電圧をVout2、ト
ランジスタ9のベース・エミッタ間の電圧をVBE9 
とすると、Vout2=Vout1−VBE9    
           −−−−−−(4)となり、D
C電圧がシフトしてしまう問題があった。また、図8に
示すように、端子7をバッファ10を介して次段へつな
ぐことも考えられる。しかしながらこの方法では、発振
周波数も電圧も変化しないが、バッファを構成する分、
回路規模が大きくなってしまう問題があった。
However, in the above-described conventional oscillation circuit, when a circuit is connected in which the current flowing into and out of the terminal 7 cannot be ignored, the oscillation waveform changes. Therefore, there was a problem that the terminal 7 could not be connected to the next stage. Therefore, as shown in FIG. 7, it is conceivable to output terminal 7 to terminal 8 using an emitter follower. However, with this method, the oscillation frequency does not change, but the voltage at terminal 7 is Vout1, the voltage at terminal 8 is Vout2, and the voltage between the base and emitter of transistor 9 is VBE9.
Then, Vout2=Vout1−VBE9
--------(4), and D
There was a problem that the C voltage shifted. Furthermore, as shown in FIG. 8, it is also conceivable to connect the terminal 7 to the next stage via the buffer 10. However, with this method, the oscillation frequency and voltage do not change, but since the buffer is configured,
There was a problem that the circuit scale became large.

【0005】本発明の目的は上述した課題を解消して、
発振波形を任意にDCシフトでき、かつ回路規模を大き
くせずに出力を次段に接続することのできる三角波の発
振回路を提供しようとするものである。
[0005] The purpose of the present invention is to solve the above-mentioned problems,
The present invention aims to provide a triangular wave oscillation circuit which can arbitrarily DC shift the oscillation waveform and whose output can be connected to the next stage without increasing the circuit scale.

【0006】[0006]

【課題を解決するための手段】本発明の発振回路は、コ
ンパレータの非反転端子に電流制御回路の第1の出力端
子を接続し、第1の抵抗を介して基準電圧を接続し、反
転端子には電流制御回路の第2の出力端子を接続し、コ
ンデンサを接続した三角波発振回路において、コンパレ
ータの非反転端子と第1の抵抗間にベース・コレクタ短
絡の第1のトランジスタを設け、電源と非反転端子間に
第1の電流源回路を接続し、反転端子と第2のトランジ
スタのベースを接続し、コレクタを電源に接続し、エミ
ッタを第2の電流源回路に接続し、第2のトランジスタ
のエミッタと、第2の電流源回路間に第2の抵抗を設け
たことを特徴とするものである。
[Means for Solving the Problems] The oscillation circuit of the present invention connects the first output terminal of the current control circuit to the non-inverting terminal of the comparator, connects the reference voltage via the first resistor, and connects the inverting terminal to the first output terminal of the current control circuit. is connected to the second output terminal of the current control circuit, and in a triangular wave oscillation circuit connected to a capacitor, a first transistor with a base-collector short circuit is provided between the non-inverting terminal of the comparator and the first resistor, and the power supply is connected to the second output terminal of the current control circuit. A first current source circuit is connected between the non-inverting terminals, the inverting terminal and the base of the second transistor are connected, the collector is connected to the power supply, the emitter is connected to the second current source circuit, and the second current source circuit is connected between the non-inverting terminals. This is characterized in that a second resistor is provided between the emitter of the transistor and the second current source circuit.

【0007】[0007]

【作用】上述した構成において、第2のトランジスタの
エミッタと第2の電流源回路間に設けた第2の抵抗によ
り、発振波形を任意にDCシフトできるとともに、特性
が同じトランジスタを使用しIC化を容易にした状態で
発振周波数を安定させて次段からの影響をなくすことが
でき、さらにバッファ等の大きな回路を必要としないた
め回路規模を小さくすることができる。
[Operation] In the above configuration, the oscillation waveform can be arbitrarily DC shifted by the second resistor provided between the emitter of the second transistor and the second current source circuit, and the IC can be implemented using transistors with the same characteristics. It is possible to stabilize the oscillation frequency while making it easy to eliminate the influence from the next stage, and furthermore, since there is no need for large circuits such as buffers, the circuit scale can be reduced.

【0008】[0008]

【実施例】図1は本発明の発振回路の一実施例の構成を
示す図である。図1に示す実施例において、コンパレー
タ1の非反転端子には、電源VCCと非反転端子間に電
流源回路14が接続され、非反転端子と抵抗3の間にベ
ース・コレクタ短絡のトランジスタ12を設け、トラン
ジスタ12のエミッタは抵抗3に接続され、電流制御回
路2の出力1に接続されている。また抵抗3の一端は基
準電圧4に接続されている。さらに、電流制御回路2の
出力1は、コンパレータ1の出力が“H”になれば電流
I6 が流れ、出力が“L”になれば電流I7 が流れ
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing the configuration of an embodiment of an oscillation circuit according to the present invention. In the embodiment shown in FIG. 1, a current source circuit 14 is connected between the power supply VCC and the non-inverting terminal of the comparator 1, and a base-collector shorted transistor 12 is connected between the non-inverting terminal and the resistor 3. The emitter of the transistor 12 is connected to the resistor 3 and to the output 1 of the current control circuit 2. Further, one end of the resistor 3 is connected to a reference voltage 4. Further, in the output 1 of the current control circuit 2, a current I6 flows when the output of the comparator 1 becomes "H", and a current I7 flows when the output becomes "L".

【0009】一方、コンパレータ1の反転端子には、電
流制御回路2の出力2が接続され、コンデンサ6が接続
されている。また、トランジスタ13が設けられ、トラ
ンジスタ13のベースは反転端子に接続され、コレクタ
はVCCに接続され、エミッタは抵抗16を介して電流
源回路15に接続されている。また、抵抗16の両端に
は端子17,18が設けられている。なお、電流制御回
路2の出力2は、コンパレータ1の出力が“H”になれ
ば電流I8 が流れ、出力が“L”になれば電流I9 
が流れる。
On the other hand, an output 2 of a current control circuit 2 is connected to an inverting terminal of the comparator 1, and a capacitor 6 is connected thereto. Further, a transistor 13 is provided, the base of the transistor 13 is connected to an inverting terminal, the collector is connected to VCC, and the emitter is connected to a current source circuit 15 via a resistor 16. Furthermore, terminals 17 and 18 are provided at both ends of the resistor 16. Note that the current I8 flows through the output 2 of the current control circuit 2 when the output of the comparator 1 becomes "H", and the current I9 flows when the output becomes "L".
flows.

【0010】次に、図1に示す本発明の実施例の動作に
ついて述べる。電源を印加した瞬間、21の電圧vC 
′はコンデンサ6が充電されていないからvC ′=0
 と考える。よって、20の電圧vR ′とvC ′の
関係は、vR ′>vC ′であるから、コンパレータ
1の出力は“H”レベルとなる。このとき、電流I6 
が流れる。よって、抵抗R1 を流れる電流は、電流源
回路の定電流I5 と電流I6 の和になるので、20
の電圧vRH′は    vRH′=VREF +R1
(I5+I6) +VBE12           
 −−−−−−(5) となる。ただし、VBE12は
トランジスタ12のベース・エミッタ間の電圧である。 このとき、端子17の充電時の最終到達点の電圧v17
H は、トランジスタ13のベース・エミッタ間の電圧
をVBE13とすれば、    v17H =VREF
 +R1(I5+I6) +VBE12−VBE13 
         =VREF +R1(I5+I6)
                     −−−−
−−(6) となる。また電流I8 によってコンデン
サ6が充電される。この充電によりvC の電位がしだ
いに上昇し、vRH′の値を越えると、コンパレータ1
の出力電圧は“L”レベルになる。このときの20の電
圧vRL′は    vRL′=VREF +R1(I
5−I7) +VBE12     (I5>I7) 
−−−−(7) となり、電流I9 によってコンデン
サ6は放電状態となるので、端子17の放電時の最終到
達点の電圧v17L は    v17L =VREF
 +R1(I5−I7) +VBE12−VBE13 
         =VREF +R1(I5−I7)
                   −−−−−−
(8) となる。
Next, the operation of the embodiment of the present invention shown in FIG. 1 will be described. At the moment when the power is applied, a voltage of 21 vC
' is vC '=0 because capacitor 6 is not charged.
I think so. Therefore, since the relationship between the voltages vR' and vC' of 20 is vR'>vC', the output of the comparator 1 becomes "H" level. At this time, the current I6
flows. Therefore, the current flowing through the resistor R1 is the sum of the constant current I5 and the current I6 of the current source circuit, so it is 20
The voltage vRH' is vRH'=VREF +R1
(I5+I6) +VBE12
--------(5) It becomes. However, VBE12 is the voltage between the base and emitter of the transistor 12. At this time, the voltage v17 at the final point when charging the terminal 17
If the voltage between the base and emitter of transistor 13 is VBE13, then H is v17H = VREF
+R1 (I5+I6) +VBE12-VBE13
=VREF +R1 (I5+I6)
------
--(6) becomes. Further, the capacitor 6 is charged by the current I8. Due to this charging, the potential of vC gradually rises, and when it exceeds the value of vRH', the comparator 1
The output voltage of becomes "L" level. The voltage vRL' at 20 at this time is vRL'=VREF +R1(I
5-I7) +VBE12 (I5>I7)
-----(7) Since the capacitor 6 is in a discharge state due to the current I9, the voltage v17L at the final point when the terminal 17 is discharged is v17L = VREF
+R1 (I5-I7) +VBE12-VBE13
=VREF +R1 (I5-I7)
--------
(8) becomes.

【0011】ここで、式(1),(2),(6),(8
) から      I1 =I5 +I6     
                        −
−−−−−(9)     −I2 =I5 −I7 
                         
   −−−−−(10) となるように、I5,I6
,I7 の電流値を決めれば、従来回路と同等の電圧が
得られることになる。さらに、端子17から次段へつな
ぐことができる。また、抵抗16を介して端子18を設
けると、端子18の電圧v18は、    v18=v
17−R2 I10                
          −−−−−(11) となり、v
17の電圧をレベルシフトして端子18に出力すること
ができる。vC ′及びv17の発振波形を図2に示す
Here, equations (1), (2), (6), (8
) from I1 = I5 + I6

-----(9) -I2 =I5 -I7

------(10) I5, I6
, I7, a voltage equivalent to that of the conventional circuit can be obtained. Furthermore, the terminal 17 can be connected to the next stage. Furthermore, when the terminal 18 is provided via the resistor 16, the voltage v18 of the terminal 18 is v18=v
17-R2 I10
−−−−−(11) So, v
17 can be level-shifted and output to terminal 18. The oscillation waveforms of vC' and v17 are shown in FIG.

【0012】本発明の変形例として、図3に図1に示す
回路と同じ回路をPNPトランジスタ22, 23によ
り構成したときの回路図を示す。また、図4に図1の回
路のコンパレータ1および電流制御回路2の実際の例の
一例を示す。実際にIC化する際は、図4に示すように
回路を作製すれば本発明を実施することができる。
As a modification of the present invention, FIG. 3 shows a circuit diagram in which the same circuit as that shown in FIG. 1 is constructed using PNP transistors 22 and 23. Further, FIG. 4 shows an example of an actual example of the comparator 1 and the current control circuit 2 of the circuit of FIG. When actually integrated into an IC, the present invention can be implemented by fabricating a circuit as shown in FIG.

【0013】[0013]

【発明の効果】以上説明したように、本発明の三角波の
発振回路においては、発振波形を任意にDCシフトした
ものを各出力から取り出すことができ、かつ回路規模を
大きくせず、出力を次段へつなぐことができる効果があ
る。また、本回路は構成する各電流源及び各素子のペア
性を利用しているため、IC化回路として有効である。
[Effects of the Invention] As explained above, in the triangular wave oscillation circuit of the present invention, an oscillation waveform obtained by arbitrarily DC shifting can be extracted from each output, and the output can be transferred to the next output without increasing the circuit scale. It has the effect of being able to connect to tiers. Further, since this circuit utilizes the pairing characteristics of each current source and each element, it is effective as an IC circuit.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の発振回路の一実施例の構成を示す図で
ある。
FIG. 1 is a diagram showing the configuration of an embodiment of an oscillation circuit of the present invention.

【図2】本発明の発振回路における三角波の発生状態を
示す図である。
FIG. 2 is a diagram showing the state of triangular wave generation in the oscillation circuit of the present invention.

【図3】本発明の発振回路の他の実施例の構成を示す図
である。
FIG. 3 is a diagram showing the configuration of another embodiment of the oscillation circuit of the present invention.

【図4】図1に示す本発明の発振回路の具体的な例を示
す図である。
FIG. 4 is a diagram showing a specific example of the oscillation circuit of the present invention shown in FIG. 1;

【図5】従来の発振回路の一実施例の構成を示す図であ
る。
FIG. 5 is a diagram showing the configuration of an embodiment of a conventional oscillation circuit.

【図6】従来の発振回路における三角波の発生状態を示
す図である。
FIG. 6 is a diagram showing a triangular wave generation state in a conventional oscillation circuit.

【図7】従来の発振回路の他の例の部分を示す図である
FIG. 7 is a diagram showing a portion of another example of a conventional oscillation circuit.

【図8】従来の発振回路のさらに他の例の部分を示す図
である。
FIG. 8 is a diagram showing a portion of still another example of a conventional oscillation circuit.

【符号の説明】[Explanation of symbols]

1  コンパレータ 2  電流制御回路 3  抵抗R1  4  リファレンス電圧 6  コンデンサ 7, 8, 11, 17, 18  出力端子9, 
12, 13  NPNトランジスタ10  バッファ
回路 14, 15  電流源回路 16  抵抗R2  22, 23  PNPトランジスタ
1 Comparator 2 Current control circuit 3 Resistor R1 4 Reference voltage 6 Capacitor 7, 8, 11, 17, 18 Output terminal 9,
12, 13 NPN transistor 10 Buffer circuit 14, 15 Current source circuit 16 Resistor R2 22, 23 PNP transistor

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  コンパレータの非反転端子に電流制御
回路の第1の出力端子を接続し、第1の抵抗を介して基
準電圧を接続し、反転端子には電流制御回路の第2の出
力端子を接続し、コンデンサを接続した三角波発振回路
において、コンパレータの非反転端子と第1の抵抗間に
ベース・コレクタ短絡の第1のトランジスタを設け、電
源と非反転端子間に第1の電流源回路を接続し、反転端
子と第2のトランジスタのベースを接続し、コレクタを
電源に接続し、エミッタを第2の電流源回路に接続し、
第2のトランジスタのエミッタと、第2の電流源回路間
に第2の抵抗を設けたことを特徴とする発振回路。
Claim 1: A first output terminal of a current control circuit is connected to the non-inverting terminal of the comparator, a reference voltage is connected via a first resistor, and a second output terminal of the current control circuit is connected to the inverting terminal. In a triangular wave oscillation circuit in which a capacitor is connected to , connect the inverting terminal and the base of the second transistor, connect the collector to the power supply, connect the emitter to the second current source circuit,
An oscillation circuit characterized in that a second resistor is provided between the emitter of the second transistor and the second current source circuit.
JP3116623A 1991-04-22 1991-04-22 Oscillation circuit Withdrawn JPH04322514A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3116623A JPH04322514A (en) 1991-04-22 1991-04-22 Oscillation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3116623A JPH04322514A (en) 1991-04-22 1991-04-22 Oscillation circuit

Publications (1)

Publication Number Publication Date
JPH04322514A true JPH04322514A (en) 1992-11-12

Family

ID=14691777

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3116623A Withdrawn JPH04322514A (en) 1991-04-22 1991-04-22 Oscillation circuit

Country Status (1)

Country Link
JP (1) JPH04322514A (en)

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