JPH0432234A - Bump structure for flip-chip bonding - Google Patents
Bump structure for flip-chip bondingInfo
- Publication number
- JPH0432234A JPH0432234A JP13886990A JP13886990A JPH0432234A JP H0432234 A JPH0432234 A JP H0432234A JP 13886990 A JP13886990 A JP 13886990A JP 13886990 A JP13886990 A JP 13886990A JP H0432234 A JPH0432234 A JP H0432234A
- Authority
- JP
- Japan
- Prior art keywords
- solder bump
- semiconductor element
- point side
- substrate
- solder bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 43
- 230000008018 melting Effects 0.000 claims abstract description 29
- 238000002844 melting Methods 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000000155 melt Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体素子の電気的接続の手法に関し、特に
フリップチップホンディングに用いるバンプの構造の改
良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for electrically connecting semiconductor devices, and particularly to improving the structure of bumps used in flip chip bonding.
〔従来の技術]
第2図(a)〜(C)は、従来のフリップチ・スプボン
ディング用バイブ構造及びその動作を示す断面図であり
、図において、1は半導体素子、2はこの半導体素子1
を搭載する基板、3は上記半導体素子1と基板2を電気
的に接続するためのソルダーバンプである。[Prior Art] FIGS. 2(a) to 2(C) are cross-sectional views showing a conventional flip chip bonding vibe structure and its operation. In the figures, 1 is a semiconductor element, and 2 is a semiconductor element 1.
3 are solder bumps for electrically connecting the semiconductor element 1 and the substrate 2.
次に動作について説明する。Next, the operation will be explained.
例えば蒸着法などによりソルダーバンプ3を各々形成し
た半導体素子1と基板2を位置合わせする(図(a))
。For example, the semiconductor element 1 and the substrate 2 each having a solder bump 3 formed thereon by a vapor deposition method are aligned (FIG. (a))
.
次いで、両者を所定の荷重で押し合わせる(図(b))
。Next, press both together with a predetermined load (Figure (b))
.
最後に全体をソルダーバンプ3の融点以上の温度に加熱
して、両側のソルダーバンプを溶融、接合する(図(C
))。Finally, the whole is heated to a temperature higher than the melting point of solder bump 3 to melt and join the solder bumps on both sides (Figure (C)
)).
〔発明が解決しようとする課題]
従来のフリップチップボンディング用バンプ構造は以上
のように構成されているので、溶融接合後のソルダーバ
ンプの形状は第2図(C)に示すように、高さが減少し
幅が増加する。この形状変化のため、例えば高さが減少
することにより接合の耐ヒートサイクル性が劣化したり
、また例えば、幅が増加することにより隣接するソルダ
ーバンプとのピッチを小さくすることができないなどの
問題点があった。[Problem to be Solved by the Invention] Since the conventional bump structure for flip chip bonding is configured as described above, the shape of the solder bump after melt bonding has a height as shown in FIG. 2(C). decreases and width increases. Due to this shape change, for example, the heat cycle resistance of the bond deteriorates due to a decrease in height, and the pitch between adjacent solder bumps cannot be reduced due to an increase in width, for example. There was a point.
この発明は上記のような問題点を解消するためになされ
たもので、接合後においてもほとんど形状変化のないフ
リップチップボンディング用バンプ構造を得ることを目
的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a bump structure for flip chip bonding that hardly changes in shape even after bonding.
この発明に係るフリップチップボンディング用バンプ構
造は、融点の異なる二種のソルダーバンプを各々半導体
素子と基板とに形成し、かつ低融点側のソルダーバンプ
を溶融接合するのに必要最小限のサイズにしたものであ
る。The bump structure for flip chip bonding according to the present invention forms two types of solder bumps with different melting points on a semiconductor element and a substrate, respectively, and reduces the size of the solder bump on the lower melting point side to the minimum size necessary for melting and bonding. This is what I did.
この発明においては、融点の異なる二種のソルダーバン
プを各々半導体素子と基板とに形成し、かつ低融点側の
ソルダーバンプを必要最小限のサイズにして、低融点側
のソルダーバンプのみを溶融させて接合するようにした
ので、接合後においてもほとんど形状変化を生じること
がない。In this invention, two types of solder bumps with different melting points are formed on the semiconductor element and the substrate, respectively, and the solder bumps on the lower melting point side are reduced in size to the minimum necessary size, and only the solder bumps on the lower melting point side are melted. Since the parts are joined together, almost no change in shape occurs even after joining.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図(a)〜(C)は、本発明によるフリップチップ
ホディング用バンプ構造及びその動作を示す断面図であ
り、第2図と同一符号は同一または相当部分を示し、4
Aは半導体素子1上に形成された高融点側のソルダーバ
ンプ、4Bは基板2上に形成された低融点側のソルダー
バンプである。1(a) to 1(C) are cross-sectional views showing the bump structure for flip chip hoarding and its operation according to the present invention, and the same reference numerals as in FIG. 2 indicate the same or corresponding parts, and 4
A is a solder bump on the high melting point side formed on the semiconductor element 1, and 4B is a solder bump on the low melting point side formed on the substrate 2.
次に動作について説明する。Next, the operation will be explained.
高融点側のソルダーバンプ4Aを形成した半導体素子1
と、低融点側のソルダーバンプ4Bを形成した基板2を
位置合わせする(図(a))。Semiconductor element 1 with solder bumps 4A formed on the high melting point side
and the substrate 2 on which the solder bumps 4B on the low melting point side are formed are aligned (FIG. (a)).
次いで、両者を所定の荷重で押し合わせる(図(b))
。Next, press both together with a predetermined load (Figure (b))
.
最後に全体をソルダーバンプ4Bの融点以上かつソルダ
ーバンプ4Aの融点未満の温度に加熱して、低融点側の
ソルダーバンプ4Bのみを溶融させて接合する。Finally, the whole is heated to a temperature higher than the melting point of the solder bumps 4B and lower than the melting point of the solder bumps 4A to melt and join only the solder bumps 4B on the lower melting point side.
このように本実施例においては、半導体素子1上に、こ
れと対向するソルダーバンプ4Bよりも融点の高いソル
ダーバンプ4Aを設け、かつ上記低融点側ソルダーバン
プ4Bの形状を溶融接合を行なうのに必要最小限のサイ
ズとしたので、半導体素子1と基板2とを溶融接合した
後の接合部における高さの減少や幅の低下が起こるのを
低減することができ、そのため接合の耐ヒートサイクル
性の劣化を低減でき、またソルバーバンプ同志のピッチ
を小さくすることができる。In this embodiment, the solder bumps 4A having a higher melting point than the opposing solder bumps 4B are provided on the semiconductor element 1, and the shape of the lower melting point side solder bumps 4B is adapted to perform melt bonding. Since the size is set to the minimum necessary size, it is possible to reduce the reduction in height and width at the bonded portion after the semiconductor element 1 and substrate 2 are melt-bonded, thereby improving the heat cycle resistance of the bond. deterioration of the solver bumps can be reduced, and the pitch between the solver bumps can be reduced.
なお、上記実施例では高融点側のソルダーバンプ4Aを
半導体素子l上に、低融点側ソルダーバンプ4Bを基板
2上に各々形成する例を示したが、これとは逆に、低融
点側のソルダーバンプ4Bを半導体素子1上に、高融点
側ソルダーバンプ4Aを基板2上に各々形成してもよい
。In the above embodiment, the solder bumps 4A on the high melting point side are formed on the semiconductor element 1, and the solder bumps 4B on the low melting point side are formed on the substrate 2. The solder bumps 4B and the high melting point side solder bumps 4A may be formed on the semiconductor element 1 and the substrate 2, respectively.
また、上記実施例では半導体素子1と基板2とを接合す
る例を示したが、ソルダーバンプを用いて接合するも、
例えば、半導体素子同士または基板同士等を接合する場
合にも用いることができることは言うまでもない。Further, in the above embodiment, an example was shown in which the semiconductor element 1 and the substrate 2 were bonded, but even if they were bonded using solder bumps,
For example, it goes without saying that it can also be used to bond semiconductor elements or substrates together.
〔発明の効果]
以上のように本説明に係るフリップチップボンディング
用バンプ構造によれば、融点の異なる二種のソルダーバ
ンプを用い、かつ低融点側のソルダーバンプを必要最小
限のサイズにして、この低融点側のソルダーバンプのみ
を溶融させて接合するようにしたから、溶融接合後にお
いてもほとんど形状変化が発生せず、接合の耐ヒートサ
イクル性が劣化することもなく、またソルダーバンプの
ピッチも小さくすることができるという効果がある。[Effects of the Invention] As described above, according to the bump structure for flip chip bonding according to the present description, two types of solder bumps with different melting points are used, and the solder bump on the lower melting point side is made to the minimum necessary size, Since only the solder bumps on the low melting point side are melted and bonded, there is almost no change in shape even after melt bonding, there is no deterioration in the heat cycle resistance of the bond, and the pitch of the solder bumps is This has the effect that it can also be made smaller.
第1図(a)〜(C)はこの発明の一実施例によるフリ
ップチップボンディング用バンプ構造およびその動作を
示す断面図、第2図(a)〜(C)は従来のフリップチ
ップボンディング用バンプ構造及びその動作を示す断面
図である。
1は半導体素子、2は基板、4Aは高融点側ソルダーバ
ンプ、4Bは低融点側ソルダーバンプである。
なお図中同一符号は同−又は相当部分を示す。
第1図FIGS. 1(a) to (C) are cross-sectional views showing a bump structure for flip chip bonding and its operation according to an embodiment of the present invention, and FIGS. 2(a) to (C) are cross-sectional views of a conventional bump for flip chip bonding. FIG. 3 is a cross-sectional view showing the structure and its operation. 1 is a semiconductor element, 2 is a substrate, 4A is a solder bump on the high melting point side, and 4B is a solder bump on the low melting point side. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 1
Claims (1)
続するために上記半導体素子及び基板の表面に形成され
たソルダーバンプにおいて、 融点の異なる二種のソルダーバンプを各々、上記半導体
素子及び基板の表面に形成し、かつ低融点側のソルダー
バイプを溶融接合するのに必要最小限の大きさとしたこ
とを特徴とするフリップチップボンディング用バンプ構
造。(1) In the solder bumps formed on the surfaces of the semiconductor element and the substrate for electrically connecting the semiconductor element and the substrate on which it is mounted, two types of solder bumps with different melting points are used for the semiconductor element and the substrate on which the semiconductor element is mounted. A bump structure for flip chip bonding, which is formed on the surface of a substrate and has a minimum size necessary for melting and bonding a solder pipe on the low melting point side.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13886990A JPH0432234A (en) | 1990-05-28 | 1990-05-28 | Bump structure for flip-chip bonding |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13886990A JPH0432234A (en) | 1990-05-28 | 1990-05-28 | Bump structure for flip-chip bonding |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0432234A true JPH0432234A (en) | 1992-02-04 |
Family
ID=15232024
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13886990A Pending JPH0432234A (en) | 1990-05-28 | 1990-05-28 | Bump structure for flip-chip bonding |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0432234A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0678908A1 (en) * | 1994-04-19 | 1995-10-25 | International Business Machines Corporation | Low temperature ternary C4 method |
-
1990
- 1990-05-28 JP JP13886990A patent/JPH0432234A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0678908A1 (en) * | 1994-04-19 | 1995-10-25 | International Business Machines Corporation | Low temperature ternary C4 method |
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