JPH04321260A - Electronic-circuit module - Google Patents

Electronic-circuit module

Info

Publication number
JPH04321260A
JPH04321260A JP3090224A JP9022491A JPH04321260A JP H04321260 A JPH04321260 A JP H04321260A JP 3090224 A JP3090224 A JP 3090224A JP 9022491 A JP9022491 A JP 9022491A JP H04321260 A JPH04321260 A JP H04321260A
Authority
JP
Japan
Prior art keywords
circuit pattern
dam frame
circuit board
conductor circuit
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3090224A
Other languages
Japanese (ja)
Inventor
Hisato Tanaka
寿人 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP3090224A priority Critical patent/JPH04321260A/en
Publication of JPH04321260A publication Critical patent/JPH04321260A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To lower an interconnection density on a board around a chip and to easily and simply design a conductor circuit pattern or constitute the conductor circuit pattern at an electronic-circuit module in which a semiconductor bare chip is sealed with an insulating resin filled into a dam frame. CONSTITUTION:A dam frame 7 in which a second conductor circuit pattern 6 is formed on its outer circumferential face is bonded and arranged so as to surround a semiconductor bare chip 3 mounted on the face of a circuit board 2; the end part of the conductor circuit pattern 6 of the dam frame 7 is connected electrically to a connecting pad 9 on the face of the circuit board 2. An insulating resin 11 is injected and filled into said dam frame 7; the semiconductor bare chip 3 is sealed airtightly with the resin 11. That is to say, one part (the second conductor circuit pattern 6) of a conductor circuit pattern 1 at the peripheral part of the mounted semiconductor bare chip 3 is formed on the face of the dam frame 7 forming an airtightly sealed region. Thereby, the main point is that an interconnection density on the face of the circuit board 2 is reduced and that the degree of freedom of an interconnection is enhanced.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】[発明の目的][Object of the invention]

【0002】0002

【産業上の利用分野】本発明は電子回路モジュールに係
り、特にCOB(Chip on Board )タイ
プやCOG(Chip on Glass)タイプなど
配線密度の高い電子回路モジュールに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electronic circuit modules, and particularly to electronic circuit modules with high wiring density such as COB (Chip on Board) type and COG (Chip on Glass) type.

【0003】0003

【従来の技術】従来、次のように構成されたCOBもし
くはCOGタイプの電子回路モジュールが開発され、ま
た実用に供されている。すなわち、図4に展開して斜視
的に示すように、主面に導体回路パターン1が形成され
た回路基板2上の所定の位置に、半導体ベアチップ3を
ダイボンドし、ワイヤボンディングなどにより実装し、
さらに回路基板2上に、たとえば合成樹脂製のダム枠4
を、半導体チップ3を囲むように配置・接着され、前記
半導体チップ3の保護のために、ダム枠4内には絶縁性
の樹脂(図示を省略。)を注入充して、この樹脂により
半導体チップ3を気密に封止した構成の電子回路モジュ
ールが知られている。
2. Description of the Related Art Conventionally, COB or COG type electronic circuit modules configured as follows have been developed and put into practical use. That is, as shown in expanded perspective in FIG. 4, a semiconductor bare chip 3 is die-bonded to a predetermined position on a circuit board 2 having a conductive circuit pattern 1 formed on its main surface, and mounted by wire bonding or the like.
Further, on the circuit board 2, a dam frame 4 made of, for example, synthetic resin is placed.
are arranged and bonded to surround the semiconductor chip 3. In order to protect the semiconductor chip 3, an insulating resin (not shown) is injected into the dam frame 4, and the semiconductor An electronic circuit module having a structure in which a chip 3 is hermetically sealed is known.

【0004】0004

【発明が解決しようとする課題】しかし、上記構成の電
子回路モジュールにおいては、実用上次のような不都合
な問題がある。すなわち、回路基板2面に搭載・実装さ
れた半導体チップ3周辺部は、特に導体回路パターン1
の配設密度が高くなるため、導体回路パターン設計に多
大な時間と労力を要する。また、どうしても回路基板2
面だのみに、所要の導体回路パターン1を形成し得ない
ため、多層配線を行わなければならない場合が生じ、導
体回路パターン層数を増大せざるを得ないという問題が
あった。本発明はこれらの問題を解決するためになされ
たもので、導体回路パターンの設計が容易で、また設計
に要する時間と労力が低減され、かつ導体回路パターン
層数の増大を伴わない電子回路モジュールの提供を目的
にする。
However, the electronic circuit module having the above structure has the following practical problems. That is, the peripheral area of the semiconductor chip 3 mounted and mounted on the circuit board 2 surface is particularly exposed to the conductor circuit pattern 1.
Since the arrangement density of the conductor circuits increases, it takes a great deal of time and effort to design conductor circuit patterns. Also, if the circuit board 2
Since the required conductor circuit pattern 1 cannot be formed on only one surface, multi-layer wiring may be required, and there is a problem in that the number of conductor circuit pattern layers must be increased. The present invention has been made to solve these problems, and is an electronic circuit module in which the design of a conductor circuit pattern is easy, the time and labor required for the design is reduced, and the number of layers of the conductor circuit pattern is not increased. The purpose is to provide.

【0005】[発明の構成][Configuration of the invention]

【0006】[0006]

【課題を解決するための手段】本発明に係る電子回路モ
ジュールは、主面に導体回路パターンが形成された回路
基板と、前記回路基板面上に搭載・実装された半導体チ
ップと、前記搭載・実装された半導体チップを囲繞する
ように回路基板面上に接着配置されたダム枠と、前記ダ
ム枠内を充填して半導体チップを封止する絶縁性樹脂層
とを備えた電子回路モジュールにおいて、前記ダム枠の
外周面に第2の導体回路パターンが形成されるとともに
回路基板面上に設けられている接続パッドに電気的に接
続して成ることを特徴としている。
[Means for Solving the Problems] An electronic circuit module according to the present invention includes a circuit board on which a conductive circuit pattern is formed on the main surface, a semiconductor chip mounted/mounted on the surface of the circuit board, and a semiconductor chip mounted/mounted on the surface of the circuit board. An electronic circuit module comprising a dam frame adhesively arranged on a circuit board surface so as to surround a mounted semiconductor chip, and an insulating resin layer filling the inside of the dam frame and sealing the semiconductor chip, A second conductive circuit pattern is formed on the outer peripheral surface of the dam frame and is electrically connected to connection pads provided on the circuit board surface.

【0007】[0007]

【作用】上記の用に構成された本発明の電子回路モジュ
ールにおいては、半導体チップを囲繞して回路基板面上
に配置されたダム枠の外周面に、所要の導体回路パター
ンが形成され、かつ回路基板面上の接続パッドに電気的
に接続されている。つまり、所定の導電回路パターンう
ち一部がダム枠に形成された構造を成しているため、ダ
ム枠面に形成された配線の分だけ、回路基板上の半導体
チップ周辺の導体回路パターン構成を簡略化することが
可能となり、その領域における配設密度の低減を図り得
る。したがって、配線パターンの設計が容易になり、設
計に要する時間と労力を低減することができるし、また
導体回路パターン層数の増大を抑えることも可能となる
[Function] In the electronic circuit module of the present invention configured as described above, a required conductive circuit pattern is formed on the outer peripheral surface of the dam frame that surrounds the semiconductor chip and is placed on the circuit board surface, and Electrically connected to connection pads on the surface of the circuit board. In other words, since a part of the predetermined conductive circuit pattern is formed on the dam frame, the structure of the conductor circuit pattern around the semiconductor chip on the circuit board is changed by the amount of wiring formed on the dam frame surface. It becomes possible to simplify the arrangement, and it is possible to reduce the arrangement density in that area. Therefore, the wiring pattern can be easily designed, the time and labor required for the design can be reduced, and it is also possible to suppress an increase in the number of conductive circuit pattern layers.

【0008】[0008]

【実施例】以下図1〜図3を参照して本発明の実施例を
説明する。
Embodiments An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

【0009】図1は、本発明に係る電子回路モジュール
の一構成例の要部を斜視的に示すもので、2は主面に導
体回路パターン1が形成された回路基板、3は前記回路
基板2面の所定位置に搭載・実装された半導体チップで
ある。しかして、前記半導体チップ3は、回路基板2面
の導体回路パターン1のパッド部にボンディングワイヤ
5によって電気的に接続されている。また、7は前記回
路基板2面上には、合成樹脂製で外周面(上面および側
周面)に所要(所望)の第2の導体回路パターン6が設
けられた矩形のダム枠で、前記実装された半導体チップ
3を囲むように配置・固定されている。このダム枠7の
取付け構造を詳述すると、ダム枠7の底面は、図2に拡
大して断面的に示すように、接着剤8を介して回路基板
2面に接着・固定されるとともに、回路基板2面上の所
定の位置(所定の導体回路パターン6の端部)には、そ
れぞれ接続パッド9が設けられており、ダム枠7外周面
上の第2の導体回路パターン6の各端部がそれぞれこれ
らの接続パッド9に半田10により接合され、電気的に
接続されている。さらに、11はダム枠7内において、
前記実装された半導体チップ3を気密に封止する絶縁性
樹脂層で、たとえば絶縁性の液状樹脂を注入充填し、硬
化させることによって形成されている。
FIG. 1 is a perspective view showing a main part of an example of the configuration of an electronic circuit module according to the present invention, in which 2 is a circuit board on which a conductor circuit pattern 1 is formed on the main surface, and 3 is the circuit board. It is a semiconductor chip mounted and mounted at predetermined positions on two sides. Thus, the semiconductor chip 3 is electrically connected to the pad portion of the conductor circuit pattern 1 on the circuit board 2 by the bonding wire 5. Reference numeral 7 denotes a rectangular dam frame made of synthetic resin and having a required (desired) second conductor circuit pattern 6 on the outer peripheral surface (top surface and side peripheral surface) on the surface of the circuit board 2; It is arranged and fixed so as to surround the mounted semiconductor chip 3. Describing the mounting structure of the dam frame 7 in detail, the bottom surface of the dam frame 7 is adhered and fixed to the circuit board 2 surface via an adhesive 8, as shown in an enlarged cross-sectional view in FIG. Connection pads 9 are provided at predetermined positions on the surface of the circuit board 2 (ends of the predetermined conductor circuit patterns 6), and each end of the second conductor circuit pattern 6 on the outer peripheral surface of the dam frame 7 is provided with connection pads 9. The portions are respectively bonded to these connection pads 9 by solder 10 and electrically connected. Furthermore, 11 is within the dam frame 7,
This is an insulating resin layer that hermetically seals the mounted semiconductor chip 3, and is formed by, for example, injecting and filling an insulating liquid resin and curing it.

【0010】なお、上記構成例において、ダム枠7外周
面に配設した第2の導体回路パターン6の形成は、たと
えば次のような手段で容易に達成し得る。すなわち、図
3に斜視的に示すように、ダム枠7の所定面に導電性ペ
ーストなどにより所要の導体回路パターン6を形成した
後、その端部にスルーホール7aを穿説し、スルホール
接続層(導体層)6aを形成してから、このスルーホー
ル7aの中心部を境にして、一点鎖線で示す切断線に沿
って端の部分を切断除去する。こうして、スルーホール
7a内壁面に形成された導体層6aをそのまま配線に利
用し、側周面への導体回路パターン6が形成される。
In the above configuration example, the formation of the second conductive circuit pattern 6 disposed on the outer peripheral surface of the dam frame 7 can be easily achieved, for example, by the following means. That is, as shown perspectively in FIG. 3, after forming a required conductive circuit pattern 6 on a predetermined surface of the dam frame 7 using conductive paste or the like, through holes 7a are punched at the ends thereof, and a through hole connection layer is formed. After the (conductor layer) 6a is formed, the end portion is cut and removed along the cutting line indicated by the dashed line, with the center of the through hole 7a as the border. In this way, the conductor layer 6a formed on the inner wall surface of the through hole 7a is used as it is for wiring, and the conductor circuit pattern 6 is formed on the side peripheral surface.

【0011】上記構成の電子回路モジュールにおいては
、ダム枠7の外周面に第2の導体回路パターン6が形成
され、かつ回路基板2面上に設けられた接続パッド9と
電気的に接続され、半導体チップ3周辺部の導体回路パ
ターンの一部として機能する構成と成っている。つまり
、回路基板2の主面を用いずに半導体チップ3周辺の配
線密度を実質的に高くした構成を成すため、回路基板2
面上の導体回路パターン1設計の簡略化や、大幅な自由
度を付与し得ることになる。
In the electronic circuit module having the above configuration, the second conductor circuit pattern 6 is formed on the outer peripheral surface of the dam frame 7 and is electrically connected to the connection pad 9 provided on the surface of the circuit board 2. It is configured to function as a part of the conductive circuit pattern around the semiconductor chip 3. In other words, in order to achieve a configuration in which the wiring density around the semiconductor chip 3 is substantially increased without using the main surface of the circuit board 2,
The design of the conductive circuit pattern 1 on the surface can be simplified and a large degree of freedom can be provided.

【0012】0012

【発明の効果】以上説明したように、本発明の電子回路
モジュールによれば、基板上の半導体チップ周辺の導体
回路パターンを簡略化すると同時に、全体の配線密度を
上げることができる。したがって、回路基板におけるパ
ターン設計が容易になり、設計に要する時間と労力を低
減することができ、かつパターン層数の増大も抑えられ
る。
As described above, according to the electronic circuit module of the present invention, the conductor circuit pattern around the semiconductor chip on the substrate can be simplified, and at the same time, the overall wiring density can be increased. Therefore, pattern design on the circuit board becomes easy, the time and labor required for the design can be reduced, and an increase in the number of pattern layers can also be suppressed.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明に係る電子回路モジュールの一構成例の
要部を示す斜視図。
FIG. 1 is a perspective view showing a main part of an example of the configuration of an electronic circuit module according to the present invention.

【図2】図1に図示する構成例の要部を拡大して示す断
面図。
FIG. 2 is a cross-sectional view showing an enlarged main part of the configuration example shown in FIG. 1;

【図3】本発明に係る電子回路モジュールの構成に用い
るダム枠面に第2の導電回路パターンを形成する方法例
を模式的に示す斜視図。
FIG. 3 is a perspective view schematically showing an example of a method for forming a second conductive circuit pattern on a dam frame surface used in the configuration of an electronic circuit module according to the present invention.

【図4】従来の電子回路モジュールの構造を展開して示
す斜視図。
FIG. 4 is an exploded perspective view showing the structure of a conventional electronic circuit module.

【符号の説明】[Explanation of symbols]

1…回路基板面上の導体回路パターン    2…回路
基板    3…半導体チップ 4、7…ダム枠    5…ボンディングワイヤ   
 6…第2の導電回路パターン    6a…スルホー
ル接続層    7a…スルホール    8…接着剤
    9…接続パッド    10…半田    1
1…封止樹脂層出願人            株式会
社  東芝代理人    弁理士    須  山  
佐  一(ほか1名)
1... Conductor circuit pattern on the circuit board surface 2... Circuit board 3... Semiconductor chips 4, 7... Dam frame 5... Bonding wire
6... Second conductive circuit pattern 6a... Through hole connection layer 7a... Through hole 8... Adhesive 9... Connection pad 10... Solder 1
1... Sealing resin layer Applicant Toshiba Corporation Agent Patent attorney Suyama
Saichi (1 other person)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  主面に導体回路が形成された回路基板
と、前記回路基板上に搭載・実装された半導体チップと
、前記搭載・実装された半導体チップを囲繞するように
回路基板面上に接着配置されたダム枠と、前記ダム枠内
に充填され半導体チップを封止する絶縁性樹脂層とを備
えた電子回路モジュールにおいて、前記ダム枠の外周面
に第2の導体回路を設けるとともに回路基板上に設けら
れている接続パッドと電気的に接続して成ることを特徴
とする電子回路モジュール。
Claim 1: A circuit board having a conductor circuit formed on its main surface, a semiconductor chip mounted/mounted on the circuit board, and a semiconductor chip mounted/mounted on the circuit board surface so as to surround the mounted/mounted semiconductor chip. In an electronic circuit module comprising an adhesively arranged dam frame and an insulating resin layer filled in the dam frame and sealing a semiconductor chip, a second conductor circuit is provided on the outer peripheral surface of the dam frame, and a circuit is provided. An electronic circuit module characterized by being electrically connected to connection pads provided on a substrate.
JP3090224A 1991-04-22 1991-04-22 Electronic-circuit module Withdrawn JPH04321260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3090224A JPH04321260A (en) 1991-04-22 1991-04-22 Electronic-circuit module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3090224A JPH04321260A (en) 1991-04-22 1991-04-22 Electronic-circuit module

Publications (1)

Publication Number Publication Date
JPH04321260A true JPH04321260A (en) 1992-11-11

Family

ID=13992518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3090224A Withdrawn JPH04321260A (en) 1991-04-22 1991-04-22 Electronic-circuit module

Country Status (1)

Country Link
JP (1) JPH04321260A (en)

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Legal Events

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A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19980711