JPH04321249A - Mmic oscillator - Google Patents

Mmic oscillator

Info

Publication number
JPH04321249A
JPH04321249A JP3001358A JP135891A JPH04321249A JP H04321249 A JPH04321249 A JP H04321249A JP 3001358 A JP3001358 A JP 3001358A JP 135891 A JP135891 A JP 135891A JP H04321249 A JPH04321249 A JP H04321249A
Authority
JP
Japan
Prior art keywords
output
oscillation
wafer
resistance
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3001358A
Other languages
Japanese (ja)
Inventor
Toshihiko Kaneko
俊彦 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3001358A priority Critical patent/JPH04321249A/en
Publication of JPH04321249A publication Critical patent/JPH04321249A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To measure an RF characteristic on a wafer without an oscillation stop and a frequency jump by a method wherein a resistance which has been connected between an interconnection extracting an oscillation output and an oscillation pad inside each chip is connected to an electrode, for probe use, which is composed of an ohmic metal inside a scribing region between individual chips. CONSTITUTION:A plurality of chips 1 for MMIC oscillators are arranged on a semiconductor wafer; each resistance contact 4 and each resistance 5 are connected between each output inter-connection 3 and each output pad 2; each electrode 6, for probe use, which is formed of an ohmic metal is connected to the other end of the resistance 5 inside each scribing region. A probe, for on-wafer probing, whose characteristic impedance is at 50OMEGA is connected to the electrode 6 for probing. Since an oscillation output is dropped, the correlation between it and an action state that an intrinsic load is connected is investigated, and the upper limit and the lower limit which judge whether the output is good or not are decided. Thereby, problems such as an oscillation stop and a frequency jump are not caused, and an RF characteristic can be measured on a wafer.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明はＭＭＩＣ（Ｍｉｃｒｏｗ
ａｖｅ　Ｍｏｎｏｌｉｔｈｉｃ　ＩＣ　）化発振器に関
し、特にハイインピーダンス入力負荷のＭＭＩＣ化発振
器に関するものである。[Industrial Application Field] The present invention relates to MMIC (Micro
The present invention relates to a monolithic IC oscillator, and particularly to an MMIC oscillator with a high impedance input load.

【０００２】0002

【従来の技術】ハイインピーダンス入力負荷を前提とし
て設計されているマイクロ波回路を測定する際、広く用
いられている特性インピーダンスが５０Ωの測定系を接
続すると、発振停止や発振周波数のジャンプなどの問題
が発生する。[Prior Art] When measuring a microwave circuit designed with a high-impedance input load in mind, if a widely used measurement system with a characteristic impedance of 50Ω is connected, problems such as oscillation stop and oscillation frequency jumps occur. occurs.

【０００３】そのため発振器出力と測定系との間にシリ
ーズに数百〜数ｋΩの抵抗を挿入して測定されている。[0003] Therefore, measurements are performed by inserting a resistor of several hundred to several kΩ in series between the oscillator output and the measurement system.

【０００４】ＭＭＩＣのＲＦ特性の評価方法として、オ
ン・ウェーハ・プロービングがコストが低く効率が優れ
ている。On-wafer probing is a low-cost and highly efficient method for evaluating the RF characteristics of MMICs.

【０００５】マイクロ波帯、特にＸ帯以上の周波数にな
るとプローブが分布定数線路的な振る舞いをするので、
ハイインピーダンス・プローブの実用化は極めて難しい
。[0005] At frequencies above the microwave band, especially the X band, the probe behaves like a distributed constant line.
Practical use of high-impedance probes is extremely difficult.

【０００６】オン・ウェーハ・プロービング用プローブ
の特性インピーダンスは５０Ωが大半を占めていて、ハ
イインピーダンス負荷の発振器を評価することができな
い。そのためウェーハをスクライブしたのち、個々のチ
ップ単位でチップキャリアあるいはセラミックパッケー
ジに実装した状態で評価を行なっているのが実情である
。The characteristic impedance of probes for on-wafer probing is mostly 50Ω, making it impossible to evaluate oscillators with high impedance loads. Therefore, after scribing the wafer, the actual situation is to evaluate each chip individually mounted on a chip carrier or ceramic package.

【０００７】例えば図２に示すように、ＩＣチップ１、
電源またはバイアスライン上への高周波の回り込みを防
ぐためのマイクロチップコンデンサ９およびセラミック
基板１０，１１をろう材あるいは導電性接着剤を用いて
マウントし、ＩＣチップ１上の各パッドとマイクロチッ
プコンデンサ９およびセラミック基板１０上の出力取出
用５０Ω線路１２、電源またはバイアス供給用線路１４
，１５の間をボンデイングワイヤで接続した状態で測定
する方法がある。ＩＣチップ１とセラミック基板１０上
の５０Ω線路１２との間には５０Ω線路側のインピーダ
ンスを高くするために薄膜抵抗１３が挿入されている。For example, as shown in FIG. 2, an IC chip 1,
A microchip capacitor 9 and ceramic substrates 10 and 11 are mounted using brazing material or conductive adhesive to prevent high frequency waves from entering the power source or bias line, and each pad on the IC chip 1 and the microchip capacitor 9 are mounted using a brazing material or conductive adhesive. and a 50Ω line 12 for output output on the ceramic substrate 10, a line 14 for power supply or bias supply
, 15 is connected with a bonding wire. A thin film resistor 13 is inserted between the IC chip 1 and the 50Ω line 12 on the ceramic substrate 10 in order to increase the impedance on the 50Ω line side.

【０００８】[0008]

【発明が解決しようとする課題】従来技術によるＭＭＩ
Ｃ化発振器のＲＦ評価方法では、サンプル抜き取りによ
るパイロット判定になる。オン・ウェーハ・プロービン
グのようにウェーハ上の全チップの良否を判定すること
ができない。評価サンプルを組み立ててから評価するの
で、評価コストが高い。[Problem to be solved by the invention] MMI according to prior art
In the RF evaluation method for C-based oscillators, pilot determination is performed by sampling. Unlike on-wafer probing, it is not possible to determine the quality of all chips on a wafer. Evaluation costs are high because evaluation samples are assembled and then evaluated.

【０００９】従来ＭＭＩＣはパッケージに実装してＲＦ
特性を全数検査して良品のみ出荷していた。[0009] Conventionally, MMIC is mounted in a package and
The characteristics of all products were inspected and only good products were shipped.

【００１０】衛星放送の進展に伴ない、低雑音増幅、局
部発振、混合、中間周波増幅の機能をもつ数個のＭＭＩ
Ｃをチップの状態で組み合わせて低雑音コンバータを構
成するようになってきた。こうなると従来のパイロット
判定による評価方法ではチップ単体の特性評価ができな
い。一定の割合で不良品が混入したまま出荷することに
なり大きな問題となっている。With the development of satellite broadcasting, several MMIs with the functions of low-noise amplification, local oscillation, mixing, and intermediate frequency amplification have been developed.
Low-noise converters have come to be constructed by combining C in the form of chips. In this case, the characteristics of a single chip cannot be evaluated using the conventional evaluation method using pilot judgment. This has become a major problem as a certain percentage of products are shipped with defective products mixed in.

【００１１】[0011]

【課題を解決するための手段】本発明のＭＭＩＣ化発振
器は、半導体ウエーハ上の各チップ内の発振出力を引き
出す配線と出力パッドとの間に一端が接続された抵抗の
他端が前記各チップ間のスクライブ領域内のオーミック
メタルからなる探針用電極と接続されている。[Means for Solving the Problems] In the MMIC oscillator of the present invention, one end of a resistor is connected between an output pad and a wiring for drawing out an oscillation output in each chip on a semiconductor wafer, and the other end of the resistor is connected to each chip. It is connected to a probe electrode made of ohmic metal in the scribe area between the two.

【００１２】0012

【実施例】本発明の一実施例について、半導体ウェーハ
の一部を示す平面図である図１を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. 1, which is a plan view showing a portion of a semiconductor wafer.

【００１３】半導体ウェーハ上では複数個のＭＭＩＣ化
発振器のチップ１が配置され、各チップ１はスクライブ
領域７で仕切られている従来各発振器チップ１内では、
出力配線３、出力パッド２を介して取り出されていた。 本発明ではさらに出力配線３と出力パッド２との間に抵
抗コンタクト４および抵抗５とを接続し、その抵抗５の
他端にはオーミックメタルで形成された探針用電極６を
スクライブ領域内７で接続している。A plurality of MMIC oscillator chips 1 are arranged on a semiconductor wafer, and each chip 1 is partitioned by a scribe area 7. In each conventional oscillator chip 1,
It was taken out via the output wiring 3 and the output pad 2. In the present invention, a resistor contact 4 and a resistor 5 are further connected between the output wiring 3 and the output pad 2, and a probe electrode 6 made of ohmic metal is connected to the other end of the resistor 5 within the scribe area. It is connected with

【００１４】図１ではチップ内の発振回路の詳細は省略
し、出力部のみを示している。通常抵抗５はイオン注入
により形成され、抵抗値は数百〜数ｋΩのオーダーとな
り、発振周波数の波長に応じて注入条件を選択すること
により十分小さくすることができる。In FIG. 1, details of the oscillation circuit within the chip are omitted, and only the output section is shown. The resistor 5 is usually formed by ion implantation, and its resistance value is on the order of several hundred to several kilohms, and can be made sufficiently small by selecting implantation conditions depending on the wavelength of the oscillation frequency.

【００１５】特性インピーダンスが５０Ωのオン・ウェ
ーハ・プロービング用プローブを出力パッド２ではなく
、探針用電極６に接触させる。発振出力は低下するので
、本来の負荷を接続したときの動作状態との相関を調べ
て良否判定の上限・下限を決めておく。そうすれば発振
停止や周波数ジャンプの問題を生じることなく、ウェー
ハ上でＲＦ特性の測定が可能になる。An on-wafer probing probe having a characteristic impedance of 50Ω is brought into contact with the probe electrode 6 instead of the output pad 2. Since the oscillation output decreases, the upper and lower limits for pass/fail judgment should be determined by examining the correlation with the operating state when the original load is connected. This makes it possible to measure RF characteristics on the wafer without causing problems such as oscillation stoppage or frequency jumps.

【００１６】[0016]

【発明の効果】発振停止や周波数ジャンプを生じること
なく、ウェーハ上でＲＦ特性を測定することができる。 したがって評価時にチップキャリアやセラミックパッケ
ージなどの部品材料が不要になった。組立工数を削減し
て評価コストを低減することができた。[Effects of the Invention] RF characteristics can be measured on a wafer without stopping oscillation or causing frequency jumps. Therefore, component materials such as chip carriers and ceramic packages are no longer required during evaluation. We were able to reduce assembly man-hours and evaluation costs.

【００１７】ウェーハ上の全チップの良否判定ができる
ので、チップ出荷の場合でもチップ単体の特性保証が可
能となる。Since the quality of all chips on a wafer can be judged, it is possible to guarantee the characteristics of individual chips even when shipping chips.

【００１８】本発明で新たに追加した抵抗、探針用電極
はスクライブ領域に配置されるので、チップサイズが従
来と変らないという利点もある。Since the resistors and probe electrodes newly added in the present invention are placed in the scribe area, there is also the advantage that the chip size remains the same as before.

【図面の簡単な説明】[Brief explanation of drawings]

【図１】本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.

【図２】従来技術によるＭＭＩＣ化発振器のＲＦ特性の
評価に用いる評価用治具を示す平面図である。FIG. 2 is a plan view showing an evaluation jig used for evaluating the RF characteristics of an MMIC oscillator according to the prior art.

【符号の説明】[Explanation of symbols]

１　　　　ＩＣチップ ２　　　　出力パッド ３　　　　出力配線 ４　　　　抵抗コンタクト ５　　　　抵抗 ６　　　　探針用電極（オーミックメタル）７　　　　
スクライブ領域 ８　　　　チップキャリア ９　　　　高周波バイパス用マイクロチップコンデンサ
１０，１１　　　　セラミック基板 １２　　　　５０Ω線路 １３　　　　薄膜抵抗1 IC chip 2 Output pad 3 Output wiring 4 Resistor contact 5 Resistor 6 Probe electrode (ohmic metal) 7
Scribe area 8 Chip carrier 9 High frequency bypass microchip capacitors 10, 11 Ceramic substrate 12 50Ω line 13 Thin film resistor

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　ハイインピーダンス入力負荷をもつＭ
ＭＩＣ化発振器において、半導体ウエーハ上の各チップ
内の発振出力を引き出す配線と出力パッドとの間に一端
が接続された抵抗の他端が前記各チップ間のスクライブ
領域内のオーミックメタルからなる探針用電極と接続さ
れていることを特徴とするＭＭＩＣ化発振器。Claim 1: M with high impedance input load
In an MIC oscillator, one end of a resistor is connected between the output pad and the wiring for drawing out the oscillation output in each chip on the semiconductor wafer, and the other end is a probe made of ohmic metal within the scribe area between the chips. An MMIC oscillator characterized in that the MMIC oscillator is connected to an electrode.
JP3001358A 1991-01-10 1991-01-10 Mmic oscillator Pending JPH04321249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3001358A JPH04321249A (en) 1991-01-10 1991-01-10 Mmic oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3001358A JPH04321249A (en) 1991-01-10 1991-01-10 Mmic oscillator

Publications (1)

Publication Number Publication Date
JPH04321249A true JPH04321249A (en) 1992-11-11

Family

ID=11499277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3001358A Pending JPH04321249A (en) 1991-01-10 1991-01-10 Mmic oscillator

Country Status (1)

Country Link
JP (1) JPH04321249A (en)

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