JPH04321147A - Storage - Google Patents

Abstract

PURPOSE:To reduce the limitation for arrangement of elements on a printed board and to improve the data processing speed by setting a parity circuit into a one-chip storage to perform such operations as the parity generation, the parity check, etc. CONSTITUTION:A main memory 1 serves as a data storage part which stores the data of one word length inputted through the I/O ports 10-17 in each memory cell for each bit. A parity circuit 5 includes a parity bit generating circuit and a parity check circuit. Then a parity memory 6 serves as a parity bit storage part which stores the parity bits produced by the circuit 5. These memory 1, circuit 5 and memory 6 are contained in a single chip. Therefore the data are not exchanged with an external circuit before a parity bit is produced from the input data and the parity check is carried out. Thus the data processing speed is increased. In addition, the reliability of the circuits can be improved owing to the reduction of wiring jobs carried out on a printed board.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device composed of an IC, an LSI, or the like.

0003

2. Description of the Related Art Conventionally, a memory device used in a computer is constructed by incorporating a memory cell and ancillary circuits such as an address recorder, a buffer amplifier, and a timing controller into a single chip.

By the way, as the storage capacity of such storage devices increases, in order to increase the reliability of stored data,
When reading data from a storage device, a method is used in which data is checked using a separately provided data checking circuit element and the data is output. Parity checking is generally used as a method for checking data. Parity check generates a parity bit based on the data to be stored, aligns and maintains the overall number of bits of the data as an odd or even number, and checks the correctness of the stored data by checking the parity when reading the data. It's a method.

In order to execute this parity check on a circuit, it is necessary to repeatedly exchange data between the storage device and a separately provided data check circuit element.

However, providing the circuit element for data checking outside the storage device increases the number of wiring lines for data exchange on the printed circuit board, making the circuit redundant. As a result, space constraints are imposed, which is not desirable from the viewpoint of data processing speed.

[0007]

SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and provides a storage device that can contribute to alleviating restrictions on element arrangement on a printed circuit board and improving data processing speed. The purpose is to provide.

[Configuration of the invention]

[0009]

[Means for Solving the Problems] A storage device of the present invention includes a data storage section that stores input data, and a parity bit generation circuit that generates a parity bit based on the data stored in the data storage section. , a parity bit storage unit that stores the parity bits generated by the parity bit generation circuit, and a parity bit storage unit that stores the data and the parity bit corresponding to the data from the data storage unit and the parity bit storage unit based on an external command. The same chip includes a parity check circuit that extracts the bits and performs a parity check.

0010

[Operation] The storage device according to the present invention includes a data storage section for storing input data, a parity bit generation circuit, a parity bit storage section, and a parity check circuit all on the same chip.

Therefore, according to the storage device of the present invention,
There is no need to exchange data with an external circuit until a parity bit is generated from input data and a parity check is performed, so data processing can be performed quickly. In addition, circuit reliability (MTBF; M
ean Time Between Failure
) also rises.

0012

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram for explaining the configuration of a storage device according to an embodiment of the present invention.

In the figure, 1 indicates I/O ports 10 to 1.
This is a main memory serving as a data storage unit that stores one word length data input from 7 in bit units in individual memory cells. Reference numeral 2 denotes an address decoder which selects a memory cell on the main memory 1 by decoding the address signal inputted through the address signal ports 18 and 19 and sending an address selection signal to the main memory 1. 3 is a data controller that controls data input/output. A timing controller 4 controls the operation timing of the entire storage device based on various control signals input from an external CPU (not shown). 5 is a parity circuit including a parity bit generation circuit that generates parity bits and a parity check circuit. A parity memory 6 serves as a parity bit storage section that stores parity bits generated by the parity circuit 5. 7a~
7d is a buffer amplifier that converts the voltage level of data. 8 is the select signal from the timing controller 4 and the error signal from the parity circuit 5.
This is an AND gate that takes an ND and outputs a parity error signal.

Note that 20 to 25 are chip selection ports of the timing controller 4 to which a chip selection signal from an external CPU is input, 26 is a write enable port of the timing controller 4 to which a write enable signal is input from the external CPU, and 27 31 are output enable ports of the timing controller 4 to which output enable signals from an external CPU are input, and 32 is a parity error signal port that outputs a parity error signal.

Next, data write/read operations of the storage device of this embodiment will be explained.

First, when a chip selection signal and a write enable signal are input from the CPU (not shown) to the chip selection port (any one of 20 to 25) and write enable port 26 of the timing controller 4, the timing controller 4 sends a timing control signal to the data controller 3 and parity circuit 5. Meanwhile, at the same time, an address signal from the CPU is input to the address decoder 2. Then, address decoder 2 decodes the input address signal, generates address selection signals for main memory 1 and parity memory 6, and sends these to main memory 1 and parity memory 6. As a result, a group of memory cells in which data is to be written in main memory 1 is selected, and a 1-bit cell in parity memory 6 is also selected. After this, I/O
Data is input to this storage device through ports 10 to 17, its voltage level is converted by buffer amplifiers 7a and 7b, and the data is written to each memory cell on main memory 1 by a data controller. On the other hand, in the parity circuit 5, the parity bit generation circuit is activated under the control of the timing controller 4, and when the parity bit generation circuit receives 8-bit data from the data controller 3, it generates a parity bit based on this. Execute.

[0018] Generation of parity bits will now be explained.

When generating parity bits, addition of "0" or "1" bits changes depending on the parity check method. There are two types of parity check methods: even parity check and odd parity check, and the present invention uses the even parity check method as an embodiment. Therefore, the total sum of the 8-bit data and parity bits sent is an even number.
”. In other words, add all the data modulo 2, that is, perform the exclusive OR, and use the resulting value as the parity bit. For example, out of the 8 bits of data excluding the parity bit to be added, ” If the number of data is an even number, a “0” parity bit is added, and if it is an odd number, a “1” parity bit is added after the 8-bit data, so that the total number of “1” bits is an even number. The parity bit thus generated is written into the parity memory cell at the end of the write control signal.

Next, the case of reading will be explained.

The chip selection signal and output enable signal from the CPU are sent to the chip selection port (any one of 20 to 25) and output enable port (20 to 25) of the timing controller 4.
7 to 31), the timing controller 4 sends the timing control signal to the data controller 3 and the parity circuit 5. Meanwhile, at the same time, an address signal is input from the CPU to the address decoder 2. Then, address decoder 2 decodes the input address signal, generates address selection signals for main memory 1 and parity memory 6, and sends these to main memory 1 and parity memory 6. As a result, a memory cell group from which data is to be read is selected, and a 1-bit cell on the parity memory 6 is also selected. Then, the data and parity bit held in each memory cell are read out by the data controller and sent to the parity circuit 5. In the parity circuit 5, a parity check is executed because the parity check circuit is activated under the control of the timing controller 4.

[0022] Parity check will now be explained.

[0023] Parity check is executed by calculating the sum of all bits constituting one word length data including the parity bit and checking the parity of the sum. That is, similar to the generation of parity bits, the exclusive OR value of all bits is calculated. Furthermore, the correctness of the data is checked by comparing (exclusive OR) the value of the data read from the main memory 1 and the value of the calculated parity bit. For example, if the data read from the memory and the calculated parity bit value are the same, it will be "0", and if they are different, it will be "1". Therefore, the parity check result is “0” if there is no error in the stored data.
”, if there is an error, “1” is output as an error signal.The AND gate 8 ANDs this error signal and the select signal and outputs it as a parity error signal.In other words, if there is an error in the parity check, and A parity error signal will be output when a control signal from the CPU is input to the chip selection port (any one of 20 to 25) and the output enable port (any one of 27 to 31). If there is no error, "0" is output as a parity error signal. With this signal, data is read from the main memory 1 and sent to the buffer amplifier 7.
The voltage level is converted by the I/O ports 10 to 17, and the data is output from the I/O ports 10 to 17.

In the packaged state, the parity error signal port 32 only gates the parity error signal by chip selection and output enable, but does not perform three-state control. Therefore, when not in use, it can be treated as an unconnected pin. Also, if there are any remaining pins on the package,
This surplus pin can also be used to control the output of the parity error signal. For example, if the parity circuit 5 is not used,
By fixing the unnecessary parity error signal port 32 to either "H" or "L" with this surplus pin, the generation of noise can be suppressed.

Thus, according to this embodiment, everything from inputting data to generating parity, checking parity, and outputting a parity error signal can be executed within the same chip. As a result, restrictions on element placement on the printed circuit board can be reduced, and data processing can now be performed quickly.

[0026]

[Effects of the Invention] As described above, according to the memory device of the present invention, by incorporating a parity circuit that performs operations such as parity generation and parity check into a one-chip memory device, restrictions on element placement on a printed circuit board are reduced. , and data processing speed has improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining the configuration of a storage device according to an embodiment of the present invention.

[Explanation of symbols]

1... Main memory, 2... Address decoder, 3... Data controller, 4... Timing controller, 5... Parity circuit, 6... Parity memory, 8... AND gate.

Claims (1)

[Claims] 1. A data storage unit that stores input data, a parity bit generation circuit that generates a parity bit based on the data stored in the data storage unit, and a parity bit generation circuit that generates a parity bit based on the data stored in the data storage unit. A parity bit storage unit that stores parity bits; and a parity check that retrieves the data and parity bits corresponding to the data from the data storage unit and the parity bit storage unit based on an external command, and performs a parity check. 1. A storage device comprising a circuit and a circuit on the same chip.