JP2845804B2 - Data memory retention confirmation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data memory holding / confirming circuit and a method for checking the same, and more particularly to a data memory holding / confirming circuit for monitoring and checking a data content change due to a power supply voltage fluctuation and a method for checking the same.

[0002]

2. Description of the Related Art Conventionally, as one of such data memory holding confirmation methods, a parity bit is added for each word,
There is a checksum confirmation method for simultaneously writing a parity bit at the time of data writing and also reading a parity bit at the time of data reading to confirm that the value is correct. For example, FIG. 8 is a block diagram showing a data memory holding confirmation circuit according to this method.

A brief description will be given with reference to FIG. This data memory holding confirmation circuit has a checksum calculation and comparator 50 and a checksum storage memory 51, and is connected to the data memory 52. At the time of writing the data, the data is written to the data memory 52, and at the same time, the checksum of the write data is calculated by the checksum calculation and comparator 50 and written to the checksum storage memory 51. On the other hand, when data is read, data is read from the data memory 52, and at the same time, the checksum storage memory 5 is read.
The checksum is also read from 1, and the checksum calculation and comparator 50 calculates the checksum of the data read from the data memory 52 and compares it with the checksum read from the checksum storage memory 51. As a result of the comparison, when the checksums are different, an interrupt signal, a reset signal, and the like are generated.

As another conventional data memory retention confirmation method, a power supply voltage which replaces data memory retention confirmation by detecting a power supply voltage fluctuation of a data memory and confirming that there is no power supply voltage fluctuation. This is a fluctuation confirmation method. For example, FIG. 9 is a block diagram showing a data memory holding confirmation circuit according to this method. The data memory holding confirmation circuit has a power supply voltage detector, detects when the power supply voltage has dropped below a certain value, and generates a reset signal and the like.

[0005]

In a checksum confirmation method, which is one of the conventional data memory retention confirmation methods, a checksum is set when writing data to a data memory, and a checksum is confirmed for data read when reading data from a data memory. It is carried out. Therefore, when the data memory is not read, for example, the C
When the PU is operating in the standby mode, there is a problem that it cannot be checked.

Further, if the checksum of the data in the data memory is to be checked at all times, not at the time of reading the data memory, there is a problem that a huge circuit is required.

Further, in the power supply voltage fluctuation confirmation method which is another one of the conventional data memory retention confirmation methods, a power supply voltage fluctuation of the data memory is detected to generate an interrupt signal, a reset signal, and the like, and the data memory retention confirmation is performed. Has been substituted. Therefore, even if the data memory does not invert the data due to the power supply voltage fluctuation, an interrupt signal or the like may be generated.
In some cases, the data memory is inverted, and there has been a problem in improving the accuracy of the correlation between the actual data inversion of the data memory and the power supply voltage fluctuation.

Accordingly, an object of the present invention is to solve at least one of the higher technical problems by improving the accuracy of the correlation between the actual data inversion of the data memory and the power supply voltage fluctuation, and by constantly monitoring the data. It is to improve the reliability of the memory.

[0009]

SUMMARY OF THE INVENTION Therefore, the present invention provides a data memory holding confirmation method for confirming whether or not the data content of a data memory for writing and reading data via an internal bus has changed due to power supply voltage fluctuation. A circuit disposed adjacent to the data memory and connected to each power line and each bit line in the data memory and connected to a word line parallel to each word line in the data memory via the internal bus. A dummy cell unit including a plurality of dummy cells from which data is not read out, and a dummy cell monitoring circuit that constantly monitors the dummy cell unit by inputting data of each of the dummy cells and detecting a change in data content thereof.

The dummy cell monitoring circuit further includes a parity calculation unit for detecting data content change by inputting data of each of the dummy cells and calculating parity, and a signal requesting a process corresponding to the data content change. Is output as the monitoring output.

Alternatively, each of the dummy cells is connected to a word line parallel to a word line in the data memory, and is set or reset by a reset signal input to the word line.

Further, as the above-described lower-level solution, the P / N of each P / N transistor pair in each of the dummy cells is set.
The size ratio is the corresponding P / N of the cell in the data memory.
Different from the size ratio, they are set asymmetrically.

The L / W ratio of the inverter to the transistor in each of the dummy cells is set smaller than the corresponding L / W ratio of the cell in the data memory.

[0014]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a data memory holding confirmation circuit of the present invention. The data memory holding and confirming circuit 1 of the present embodiment constantly monitors a dummy cell section 11 adjacent to the data memory 2 for writing / reading data via the internal bus 3 and a change in the data content of the dummy cell section 11 and outputs an interrupt signal. And a dummy cell monitoring circuit 12 for outputting the same. FIG. 2 is a circuit diagram showing a detailed configuration example of the data memory holding confirmation circuit 1 of FIG.
With reference to FIG. 2, the configuration of the data memory holding confirmation circuit 1 will be described.

The dummy cell section 11 is composed of a plurality of dummy cells arranged adjacent to the data memory 2 for writing / reading data via the internal bus 3 and not reading data via the internal bus 3. Each of these dummy cells shares a bit line with each cell in the data memory 2, is connected to a word line parallel to each word line in the data memory 2, and has a common VDD (not shown) with each cell in the data memory 2. line,
Each is connected to a GND line. Therefore, the electrical characteristics of each of these dummy cells can approach the electrical characteristics of the cells in the data memory 2 without limit. Each of these dummy cells is written via the internal bus 3 and an initial value is set.

The dummy cell monitoring circuit 12 includes a parity calculator 121 and other logic elements 122 to 126. The parity calculation unit 121 receives data of each dummy cell in the dummy cell unit 11, calculates a parity, and detects a change in data content. Other logic elements 122
To 126 are outputs S1 and RES of the parity calculator 121.
An ET signal and a SET signal are input, and when a change in data content of each dummy cell in the dummy cell section 11 is detected, an interrupt signal or the like is output.

FIG. 3 shows the data memory holding confirmation circuit 1
FIG. 6 is a waveform chart showing an operation example of FIG. Referring to FIGS. 2 and 3,
The operation of the data memory holding confirmation circuit 1 of the present embodiment will be described. First, the RESET signal causes the latch circuit 123
Becomes "0", and the interrupt signal output from the AND circuit becomes "0". Next, since the initial value of each dummy cell in the dummy cell unit 11 is undefined, the dummy cell is written via the internal bus 3 by a processor instruction or the like, and the initial value is set. The parity calculation unit 121 calculates the parity of the initial value data, and the output S1 of the parity calculation unit 121 is “0”.
Next, when the SET signal rises, the output S3 of the latch circuit 124 is determined to be “0 or 1”, and the output S4 of the EXOR circuit 125 becomes “0”. After the initial value is set, the data rises only once, and the subsequent rises become invalid. S1 is inverted, and the output S4 of the EXOR circuit 125 and the interrupt signal become "1".

FIG. 4 is a circuit diagram showing Embodiment 2 of the data memory holding and confirming circuit of the present invention. As in the first embodiment, the data memory holding / confirming circuit 1 of this embodiment includes a data memory 2 for writing / reading data via the internal bus 3.
And a dummy cell portion 11 adjacent to the dummy cell portion 11.
And a dummy cell monitoring circuit 12 that constantly monitors changes in the data content of the data and outputs an interrupt signal and the like. However, the configuration in each block is different.

Since each dummy cell of the dummy cell section 11 of this embodiment has a RESET signal input to a word line parallel to the word line in the data memory 2, the dummy cell is set or reset by the RESET signal, and an initial value is set. .
Other configurations are the same as those of the first embodiment, and a duplicate description will be omitted.

Further, the dummy cell monitoring circuit 1 of the present embodiment
Reference numeral 2 includes a parity calculation unit that inputs data of each dummy cell in the dummy cell unit 11, calculates a parity, and detects a change in data content.

Data memory holding confirmation circuit 1 of this embodiment
Detects whether the initial value set for each cell in the dummy cell section 11 has changed due to power supply voltage fluctuation after reset,
Since this is output as an interrupt signal, it can be realized with a small-scale circuit.

FIG. 5 is a layout diagram showing a third embodiment of the data memory holding and confirming circuit of the present invention. The data memory retention confirmation circuit of the present embodiment includes a dummy cell unit 11 and a dummy cell monitoring circuit 12 as in the first and second embodiments, but the arrangement in the dummy cell unit 11 is different from that of the first and second embodiments. Each is different.

Referring to FIG. 5, a dummy cell unit 11 of the present embodiment is divided into dummy cell units 117 which are divided and arranged vertically or horizontally adjacent to data memory 2 for writing / reading data via internal bus 3. , 118.
Each cell in these dummy cell sections 117 and 118 has the same electrical characteristics as the cells in the data memory 2. For this reason, each cell arrangement corner section 21, 22, 23, 24
Wiring lengths from the DD terminal and the GND terminal are located at the positions indicating the longest and shortest combinations, respectively, and are easily affected by power supply voltage fluctuation. Other configurations and operations are the same as those of the first and second embodiments, and a duplicate description will be omitted.

FIG. 6 is a partial circuit diagram showing Embodiment 4 of the data memory holding and confirming circuit of the present invention. As in the first to third embodiments, the data memory holding and confirming circuit of the present embodiment includes a dummy cell unit 11, a dummy cell monitoring circuit 12,
However, the P / N size ratio of the P / N type transistors constituting the inverters of the cells in the dummy cell portion 11 and the configuration in the dummy cell portion 11 are different from those of the first to third embodiments. Referring to FIG. 6, for example, P of inverters 211 and 212 constituting a cell in data memory 2 are connected to each other.
Assuming that the / N size ratio is 1, the P / N size ratios of the inverters 111 and 112 constituting the dummy cells in the dummy cell unit 11 are set to 2 and 0.5, respectively, and the other dummy cell units 11 Inverters 113 and 114 constituting the dummy cells are 0.5 and 2 respectively.
Is set to By symmetrically changing the P / N size ratio of the inverters constituting the dummy cells in the dummy cell section 11, the dummy cell section 11 is more susceptible to power supply voltage fluctuations than the data memory 2.
Other configurations and operations are the same as those of the first to third embodiments, and a duplicate description will be omitted.

FIG. 7 is a partial circuit diagram showing Embodiment 5 of the data memory holding and confirming circuit of the present invention. As in the first to fourth embodiments, the data memory retention confirmation circuit of the present embodiment includes a dummy cell unit 11, a dummy cell monitoring circuit 12,
However, the L / W ratios of the transistors constituting the inverters of the cells in the dummy cell section 11 are different from those of the first to fourth embodiments. Referring to FIG. 7, for example,
Inverters 213 and 2 constituting cells in data memory 2
Assuming that the L / W ratio of 14 is 1, the L / W size ratio of the inverters 115 and 116 constituting the dummy cells in the dummy cell section 11 is set to 2. These dummy cell portions 11
By making the L / W size ratio of the inverter constituting the inner dummy cell smaller than that of the data memory 2, the L / W size ratio of the inverter is proportional to the drive capability of the inverter. And is susceptible to power supply voltage fluctuations. Other configurations and operations are the same as those of the first to third embodiments, and a repeated description is omitted.

It should be noted that the configurations in the above embodiments can be combined. Thereby, the dummy cell unit 1
1 can be made more susceptible to power supply voltage fluctuations as compared to the data memory 2.

[0027]

As described above, the data memory holding / confirming circuit according to the present invention is provided with a dummy cell portion adjacent to a data memory for writing / reading data via an internal bus, and changes in data contents of the dummy cell portion. Is constantly monitored and an interrupt signal is output. Therefore, it is possible to improve the correlation accuracy between the actual data inversion of the data memory and the power supply voltage fluctuation.

Further, the operation of the CPU, that is, always monitoring independently of the data writing / reading of the data memory, and performing the interrupt processing and the reset operation, thereby improving the reliability of the data memory. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a data memory retention confirmation circuit of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration example of a data memory holding confirmation circuit 1 of FIG. 1;

FIG. 3 is a waveform chart showing an operation example of the data memory holding confirmation circuit 1 of FIG.

FIG. 4 is a circuit diagram showing Embodiment 2 of a data memory holding confirmation circuit of the present invention.

FIG. 5 is a layout diagram showing a data memory holding confirmation circuit according to a third embodiment of the present invention;

FIG. 6 is a partial circuit diagram showing a fourth embodiment of the data memory holding confirmation circuit of the present invention.

FIG. 7 is a partial circuit diagram showing Embodiment 5 of the data memory holding confirmation circuit of the present invention.

FIG. 8 is a block diagram showing a configuration example 1 of a conventional data memory holding confirmation circuit.

FIG. 9 is a block diagram showing a configuration example 2 of a conventional data memory holding confirmation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data memory holding confirmation circuit 2 Data memory 3 Internal bus 11, 117-118 Dummy cell section 12 Dummy cell monitoring circuit 18 Checksum calculation and comparator 19 Checksum storage memory 111-116, 122 Inverter 121 Parity calculation section 123-124 Latch Circuit 125 EXOR circuit 126 AND circuit S1 to S4 Output signal

Continuation of front page (58) Fields investigated (Int.Cl. ⁶ , DB name) G11C 29/00 G11C 16/06 G06F 11/30 G06F 12/16

Claims (5)

(57) [Claims] 1. A data memory holding / confirming circuit for confirming whether or not the data content of a data memory for writing and reading data via an internal bus has changed due to a power supply voltage fluctuation, is adjacent to the data memory. A dummy cell arranged and connected to each power supply line and each bit line in the data memory, connected to a word line parallel to each word line in the data memory, and formed of a plurality of dummy cells not reading data via the internal bus. And a dummy cell monitoring circuit for constantly monitoring the dummy cell section by inputting data of each of the dummy cells and detecting a change in the data content thereof. 2. A signal requesting a process corresponding to the data content change, wherein the dummy cell monitoring circuit has a parity calculation unit for detecting data content change by inputting data of each of the dummy cells and calculating parity. 2. The data memory retention confirmation circuit according to claim 1, wherein the data memory retention confirmation circuit outputs a monitoring output as a monitoring output. 3. The data memory according to claim 1, wherein each of the dummy cells is connected to a word line parallel to a word line in the data memory, and is set or reset by a reset signal input to the word line. Hold confirmation circuit. 4. The P / N size ratio of each P / N transistor pair in each of the dummy cells is different from the corresponding P / N size ratio of a cell in the data memory, and is set asymmetrically. Or the data memory holding confirmation circuit according to 3. 5. The data according to claim 1, wherein an L / W ratio of an inverter to a transistor in each of the dummy cells is set smaller than a corresponding L / W ratio of a cell in the data memory. Memory retention confirmation circuit.