JP2006092634A - Semiconductor memory apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory apparatus in which a data write-in time is shortened. <P>SOLUTION: This apparatus is provided with: a memory cell array 2; an input circuit DR1 to which first data having first data width and second data having second data width being shorter than the first data width; a generating circuit 8 generating a code generated with the first data width as a unit and correcting errors of the first data and the second data; a first write-in circuit writing the first data in the memory cell array 2; a second write-in circuit in which latency being a time from specifying an address of the second data to writing it in the memory cell array is made longer than latency of the first data and which writes the second data in the memory cell 2, and a control circuit 11 writing the first data in the memory cell array 2 prior to the second data when the first data is inputted after the second data is inputted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including an ECC (Error Check and Correct) circuit.

  A DRAM (Dynamic Random Access Memory) memory cell is composed of, for example, one cell transistor and one cell capacitor. When reading data stored in the memory cell, first, the cell transistor is turned on by activating the word line. The charge held in the cell capacitor is charge-shared with the parasitic capacitance associated with the bit line, and then the charge is amplified by the sense amplifier. Then, data is read by connecting the selected bit line to an input / output (I / O) bus.

  Further, since the electric charge held by the leak current escapes from the cell capacitor, the memory cell is selected every refresh cycle time, and the electric charge held in the cell capacitor is amplified. Currently, the capacitance capacity of DRAM memory cells has been reduced in response to the reduction in memory cell size, and if the refresh cycle time so far is applied, an error may occur in reading data.

  Therefore, a memory macro having high reliability in which a 1-bit error does not appear in reading has been developed by adding a SEC-DED (Single Error Correction-Double Error Detection) type ECC circuit to the memory macro. The memory macro represents a block that functions as a memory in a system LSI (Large Scale Integrated Circuit) in which a memory, logic, and the like are integrated on one semiconductor chip.

  An example of a DRAM having this type of ECC circuit is shown in FIGS. FIG. 9 is a diagram when the write command is issued to the DRAM, and the data path is indicated by a bold line in the figure. When a write command is input, the write data is written as it is into the data memory cell array 2a. The parity bit generation circuit 8 generates a parity bit from the input write data, and the generated parity bit is written into the code memory cell array 2b.

  On the other hand, FIG. 10 is a diagram when a read command is issued to the DRAM, and the data path is indicated by a bold line in the figure as in FIG. When a read command is input, data and parity bits before error correction are read from the memory cell array 2a and the memory cell array 2b. The check bit generation circuit 9 generates a check bit from the read data before correction and the parity bit. When a 1-bit error exists, the correction circuit 10 corrects data. The corrected data is output to the outside as read data.

  In addition, a check bit indicating that a correction has been performed due to the presence of a 1-bit error or a 2-bit error is also output to the outside. As described above, in writing or reading with data having a data width necessary for the operation of the ECC circuit, the ECC function is realized by having a data path as shown in FIGS. Also, reading of data having a data width shorter than the data width necessary for the ECC circuit to operate is realized by having the same data path as in FIG. 10 and finally selecting output data.

  However, in writing with a data width shorter than the data width necessary for the ECC circuit to operate, the ECC function is not realized with the data path as shown in FIG. This is because part of the input becomes “invalid” at the input of the parity bit generation circuit 8 for generating the parity bit, and the parity bit is not generated correctly.

  FIG. 11 shows an example of a DRAM having an ECC circuit that realizes writing at a data width shorter than the data width necessary for the ECC circuit to operate. Compared with FIGS. 9 and 10, FIG. 11 has a circuit in which read data is connected to write data through a multiplexer MP2. Further, the multiplexer MP2 selects whether to output read data or write data according to mask data for selecting data lines for writing data from all data lines. The circuit operation is as follows.

  First, when a write command for writing data having a short data width is input, a read command similar to that shown in FIG. 10 is input to the DRAM, and the uncorrected data and the data from the memory cell array 2a and the memory cell array 2b are input. The parity bit is read out. Then, the check bit generation circuit 9 generates a check bit from the read uncorrected data and parity bits, and when a 1-bit error exists, the correction circuit 10 corrects the data.

  Here, the multiplexer MP2 selects a data line to which data corrected based on the mask data is transferred or a data line to which write data is transferred. Thus, the multiplexer MP2 selected by the mask data outputs write data. On the other hand, the multiplexer MP2 not selected by the mask data outputs the corrected data.

  Then, the write data selected by the mask data and the read data that is input by not being selected by the mask data are in a state where a normal write command is input as in the data path indicated by the bold line in FIG. Almost the same, the data is written as it is into the memory cell array 2a. At the same time, the parity bit generation circuit 8 generates a parity bit from the input write data and read data. The generated parity bit is written into the memory cell array 2b.

  FIG. 12 shows a timing chart showing the command input at this time and data occupying a circuit in the DRAM. “Norm.-W” and “Mask-W” in FIG. 12 represent a normal write command and a mask write command, respectively. The normal write command is a command representing writing in a data width necessary for the ECC circuit to operate. The mask write command is a command representing writing in a data width shorter than the data width necessary for the ECC circuit to operate.

  “Prech.” Represents a precharge command, and is a command for deselecting a word line. Here, in the memory cell array 2a and the memory cell array 2b, in order to perform both reading and writing within one cycle, the reading port is “R-port” and the writing port is “W-port”. Prepare and open ports at different timings.

  “Data Cell (R-port)” represents a read port of the memory cell array 2a for storing data. “Data Cell (W-port)” represents a write port of the memory cell array 2a. “Code Cell (R-port)” represents a read port of the memory cell array 2b that stores parity bits (codes). “Code Cell (W-port)” represents a write port of the memory cell array 2b.

  “Correction circuit 10 (Read)” represents the check bit generation circuit 9 and the correction circuit 10 that operate during a read operation. “Generation circuit 8 (Write)” represents the parity bit generation circuit 8 that operates during a write operation. In addition, a number represented by a “#” symbol in the chart in FIG. 12 indicates a column address (bit line address) number.

  In the DRAM configured as described above, when writing data with a short data width, it is necessary to read and correct data from memory cells more than when writing data with a normal data width. As a result, the latency is excessively increased by the time required for this circuit operation.

As this type of related technology, a DRAM having the following ECC circuit is disclosed (see Non-Patent Document 1).
JAFifield and CHStapper, High-Speed On-Chip ECC for Synergistic Fault-Tolerant Memory Chips, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.26, NO.10, OCTOBER 1991, p.1449-1452

  An object of the present invention is to provide a semiconductor memory device capable of reducing the time for writing data to a memory cell array.

  A semiconductor memory device according to an aspect of the present invention includes a memory cell array including a plurality of memory cells, first data having a first data width, and second data having a second data width shorter than the first data width. An input circuit, a generation circuit that generates a code that is generated in units of the first data width and corrects errors in the first and second data, and the first data is stored in the memory cell array. A first writing circuit for writing, a latency that is a time from when an address of the second data is specified until writing to the memory cell array is made longer than a latency of the first data, and the second data is stored in the memory A second writing circuit for writing to the cell array; and when the first data is input after the second data is input, the first data is converted to the second data. And a control circuit for writing in the memory cell array more ahead.

  According to the present invention, it is possible to provide a semiconductor memory device capable of reducing the time for writing data to the memory cell array.

  The present inventors have developed the following DRAM in the course of development of the present invention. As a result, the present inventors have obtained knowledge as described below.

  For example, when writing data with a short data width in a DRAM, it is conceivable to adopt a late write method in which data is written into a memory cell after being delayed by a predetermined number of cycles. Although this late write has a long latency, the time required for one cycle can be shortened. Note that the latency means a time from when a command for writing data is issued (or after an address is designated) to when data is actually written into a memory cell.

  As an example of such a system, FIG. 13 shows a configuration example of the DRAM 1 in which a two-stage flip-flop (F / F) is inserted in the data path of FIG. FIG. 14 is a timing chart showing commands and data occupying the circuits in the DRAM 1.

  First, when a “Norm.-W # 0” command is input, the write data at address # 0 is latched in the first stage F / F 1 inserted in the write data line WDL. Next, when a “Mask-Write # 1” command is input, the write data at address # 0 is latched in the next stage F / F2, and the write data at address # 1 is latched in the first stage F / F1. Further, the uncorrected data and the parity bit of the address # 1 are read from the memory cell array 2a and the memory cell array 2b and latched in the first stage F / F 3 inserted in the read data line RDL and the parity bit line RPL.

  Next, when a “Mask-Write # 2” command is input, the write data at address # 0 is written into the memory cell array 2a, and the parity bit generation circuit 8 starts from the input write data at address # 0. A parity bit of address # 0 is generated. This parity bit is written into the memory cell array 2b. The write data at address # 1 is latched at the next stage F / F2, and the write data at address # 2 is latched at the first stage F / F1.

  Further, the check bit generation circuit 9 generates a check bit from the data before correction of the address # 1 and the parity bit. The correction circuit 10 performs correction when a 1-bit error exists. The corrected data and the check bit are latched in the next stage F / F 4 inserted in the read data line RDL and the check bit line CBL, respectively. Then, the uncorrected data and the parity bit of the address # 2 are read from the memory cell arrays 2a and 2b and latched in the first stage F / F 3 inserted in the read data line RDL and the parity bit line RPL.

  Next, when the “Mask-Write # 3” command is input, the mask data input together with the “Mask-Write # 1” command is input to the multiplexer MP2. The mask data selects the write data line WDL through which data having a data width shorter than the normal data width is transmitted from all the write data lines WDL. The multiplexer MP2 selected by the mask data selects the write data at the address # 1. The multiplexer MP2 not selected by the mask data selects the corrected data (data on the read data line RDL). The write data and corrected data at address # 1 are written into the memory cell array 2a.

  The parity bit generation circuit 8 generates a parity bit at address # 1 from the write data at address # 1 and the corrected data. This parity bit is written into the memory cell array 2b. The write data at address # 2 is latched at the next stage F / F2, and the write data at address # 3 is latched at the first stage F / F1.

  The check bit generation circuit 9 generates a check bit from the data before correction of the address # 2 and the parity bit. The correction circuit 10 performs correction when a 1-bit error exists. The corrected data and the check bit are latched in the F / F 4 at the next stage of the read data line RDL, respectively. Then, the uncorrected data and the parity bit of the address # 3 are read from the memory cell array 2a and the memory cell array 2b and latched in the first stage F / F 3 of the read data line RDL.

  Finally, when a “Norm.-Write # 4” command is input, the write data at the address # 2 held in the F / F2 of the next stage of the write data line WDL and the next stage of the read data line RDL are stored. Similarly, the corrected data of the address # 2 held in the F / F4 is selected through the multiplexer MP2 that selects connection by the mask data input together with the “Mask-Write # 2” command, and is stored in the memory cell array 2a. Written. The parity bit generation circuit 8 generates a parity bit at address # 2 from the write data at address # 2 and the corrected data, and the generated parity bit at address # 2 is written into the memory cell array 2b.

  The write data at address # 3 is latched in the next stage F / F2, and the write data at address # 4 is latched in the first stage F / F1. Further, the check bit generation circuit 9 generates a check bit from the uncorrected data and the parity bit of the address # 3 held in the first stage F / F 3 of the read data line RDL and the parity bit line RPL. When there is a 1-bit error, the correction circuit 10 performs correction. The corrected data and the check bit are latched in the next stage F / F 4 inserted in the read data line RDL and the check bit line CBL, respectively.

  In the example of FIG. 14, the command issued by the user is up to this “Norm.-Write # 4” command, but the “Mask-Write # 3” command and “Norm.-Write # 4” issued in the last two cycles. "Write data and parity bits with the command are not written to the memory cell arrays 2a and 2b, but are held in the F / F in the circuit.

  Therefore, while the no operation command (“NOP” command) is in effect, the write operation is continued when the write data is held in the F / F in the circuit. The “NOP” command is a command that does not cause the DRAM 1 to perform any operation. In this example, the write data at the address # 3 held in the next stage F / F2 of the write data line WDL and the same address # 3 held in the next stage F / F4 of the read data line RDL. The corrected data is selected through the multiplexer MP2 that selects connection by mask data input together with the “Mask-Write # 3” command, and written to the memory cell array 2a.

  The parity bit generation circuit 8 generates a parity bit at address # 3 from the write data at address # 3 and the corrected data, and the generated parity bit is written into the memory cell array 2b. The write data at address # 4 is held in F / F2 at the next stage of the write data line WDL. In the next last cycle, the write data at address # 4 is written into the memory cell array 2a. The parity bit generation circuit 8 generates a parity bit at address # 4 from the input write data at address # 4, and the generated parity bit is written into the memory cell array 2b.

  Since writing of all the write data and parity bits to the memory cell array is completed for the first time here, the user can issue a precharge command and deselect the word line WL in the next cycle and thereafter.

  However, when this method is adopted, the latency when the “Norm.-Write” command is effective also becomes longer in accordance with the latency when the “Mask-Write” command is effective. In the chart of FIG. 14, it is necessary to always issue the precharge command after two cycles regardless of the “Mask-Write” command and the “Norm.-Write” command. That is, the write recovery time (Write Recovery Time: tWR) increases by two cycles.

  Hereinafter, embodiments of the present invention configured based on such knowledge will be described with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the DRAM 1 according to the first embodiment of the present invention. The DRAM 1 includes a memory cell array 2, a data line circuit 3, a word line circuit 4, and a memory control circuit 5. The DRAM 1 is composed of, for example, a memory macro.

  The memory cell array 2 is configured by arranging memory cells in a matrix. The memory cell is composed of one cell transistor CT and one cell capacitor CC. That is, the memory cell array 2 has a plurality of dynamic memory cells.

  In the memory cell array 2, a plurality of bit lines BL and a plurality of word lines WL are arranged. Memory cells are arranged at intersections between the plurality of bit lines BL and the plurality of word lines WL, respectively. The bit line BL is connected to one electrode of the cell capacitor CC via the cell transistor CT. The word line WL is connected to the gate electrode of the cell transistor CT. For example, an equalize voltage is supplied to the other electrode of the cell capacitor CC.

  Write data is input to the data line circuit 3 from an external circuit. The data line circuit 3 writes this write data into the memory cell array 2. The data line circuit 3 reads read data from the memory cell array 2. The data line circuit 3 outputs this read data to an external circuit.

  The data line circuit 3 receives mask data from an external circuit. As the mask data, when write data having a data width shorter than the normal data width is input, the write data line RDL corresponding to the short data width is selected from all the write data lines RDL. This mask data is input from an external circuit together with a mask write command (Mask-W).

  Further, the data line circuit 3 has an ECC circuit. A specific configuration of the data line circuit 3 will be described later.

  The word line circuit 4 selects a word line WL based on an address signal input from an external circuit. The memory control circuit 5 receives a command, an address, and a clock signal CLK from an external circuit. The memory control circuit 5 controls the data line circuit 3 and the word line circuit 4 based on this command. That is, the memory control circuit 5 controls the write data write operation and the read data read operation based on the command.

  FIG. 2 is a circuit block diagram showing the configuration of the memory cell array 2 and the data line circuit 3. The memory cell array 2 includes a memory cell array 2a that stores data and a memory cell array 2b that stores parity bits generated by the ECC circuit.

  The ECC circuit performs error correction on data having a predetermined data width. The ECC circuit includes a parity bit generation circuit 8, a check bit generation circuit 9, and a correction circuit 10. The DRAM 1 includes an SEC-DED type ECC circuit. The parity bit generation circuit 8 generates a parity bit for correcting an error based on the write data. The generated parity bit is written into the memory cell array 2b.

  The check bit generation circuit 9 generates check bits based on uncorrected data read from the memory cell array 2a and parity bits read from the memory cell array 2b. When a 1-bit error exists due to the check bit, the correction circuit 10 corrects the data based on the check bit. The corrected data is output to the external circuit as read data. A check bit is also output to the external circuit.

  The DRAM 1 can write data having a data width necessary for the operation of the ECC circuit (hereinafter referred to as a normal data width) and data having a data width shorter than the normal data width. A normal write command and a mask write command are input to the DRAM 1 (specifically, the memory control circuit 5) from an external circuit. The normal write command is a command representing writing of data having a normal data width. The mask write command is a command representing writing of data having a data width shorter than the normal data width.

  The write data line WDL for transmitting the write data is provided with a data path DP2 for bypassing the F / F. Similarly to the write data line WDL, the read data line RDL, the parity bit line RPL, and the check bit line CBL are also provided with a data path DP2 for bypassing the F / F. The DRAM 1 also includes multiplexers MP1, MP3, and MP4 for selecting the data path DP1 and data path DP2 that pass through the F / F. The multiplexers MP1, MP3, and MP4 select the data path DP1 and the data path DP2 based on the mask write command. Two flip-flops F / F5 and F / F6 are provided on the mask data line MDL for transmitting the mask data. The flip-flops F / F5 and F / F6 are provided corresponding to the insertion of two flip-flops into the write data line WDL for late writing. As a result, mask data corresponding to the address of the write data is supplied to the multiplexer MP2.

  FIG. 3 is a circuit diagram showing the configuration of the control circuit 11 that controls the operation of the multiplexer and the flip-flop. The control circuit 11 is included in the memory control circuit 5 shown in FIG. A mask write command (Mask-W) and a clock signal CLK are input to the control circuit 11. The control circuit 11 has an AND circuit 11a.

  When the mask write command is input, the control circuit 11 outputs a high level control signal C1. The control signal C1 is supplied to the multiplexer MP1. The multiplexer MP1 has an inverter circuit INV and transmission gates TG1 and TG2. The control signal C1 is also supplied to the multiplexers MP3 and MP4. The multiplexers MP3 and MP4 have the same configuration as the multiplexer MP1.

  The control circuit 11 outputs a control signal C2 corresponding to the clock signal CLK when a mask write command is input. This control signal C2 is supplied to the clock terminal of F / F2. That is, the F / F 2 latches input data in synchronization with the clock signal CLK when a mask write command is input. When no mask write command is input, the F / F 2 does not latch input data. The control signal C2 is also supplied to F / F1, F / F3, F / F4, F / F5, and F / F6. F / F1, F / F3, F / F4, F / F5, and F / F6 perform the same operation as F / F2.

  The operation of the DRAM 1 configured as described above will be described. First, the operation of the DRAM 1 when normal write commands are continuously input will be described. The driver circuit DR1 as an input circuit receives write data input from the outside. The write data output from the driver circuit DR1 is input to the multiplexer MP1 via the data path DP2.

  The multiplexer MP1 outputs the write data of the data path DP2. The write data output from the multiplexer MP1 is input to the multiplexer MP2. The write data output from the multiplexer MP2 is input to the column selection circuit 7a via the driver circuit DR2. The column selection circuit 7a connects the write data line WDL and the bit line BL based on the column address signal. Thereby, the write data is written into the memory cell array 2a.

  The write data output from the multiplexer MP2 is input to the parity bit generation circuit 8. The parity bit generated by the parity bit generation circuit 8 is input to the column selection circuit 7b via the driver circuit DR2. The column selection circuit 7b connects the parity bit line WPL and the bit line BL based on the column address signal. Thereby, the parity bit is written into the memory cell array 2b.

  The driver circuits DR1 and DR4, the flip-flops F / F1 and F / F2, and the multiplexers MP1 and MP2 are provided in a number corresponding to the normal data width. Driver circuits DR2 and DR3, flip-flops F / F3 and F / F4, and multiplexers MP3 and MP4 are provided with a number corresponding to the normal data width and a number corresponding to the data width of the parity bit. ing. The driver circuit DR5 has a number corresponding to the data width of the parity bit.

  FIG. 4 is a timing chart showing a command and data occupying a circuit in the DRAM 1 when normal write commands are continuously input. Note that the notation in FIG. 4 is the same as the notation described in FIG. When normal write commands are continuously input, all circuit operations are performed within one row cycle as shown in FIG.

  Note that one row cycle refers to a cycle from the release of the word line precharge to write data to the memory cell until the word line is precharged after the data is written to the memory cell. Specifically, one row cycle is a cycle from the input of a bank active command for selecting a bank for writing data to the input of a precharge command. When the bank active command is input, the word line WL is activated. When a precharge command is input, the word line WL is deactivated. Although omitted in FIG. 4, a bank active command is input to the DRAM 1 before the “Norm.-W # 0” command.

  Next, the operation of the DRAM 1 when the mask write command is continuously input will be described. FIG. 5 is a timing chart showing a command and data occupying a circuit in the DRAM 1 when mask write commands are continuously input.

  In this case, the write data is written into the memory cell array 2a via the data path DP1. The operation of the DRAM 1 when the mask write command is continuously input is similar to the operation described in FIG. Therefore, with the pipeline structure shown in FIG. 2, the write data and the parity bit are written into the memory cell arrays 2a and 2b after two cycles, respectively.

  Next, the operation of the DRAM 1 when a normal write command and a mask write command are input together will be described. FIG. 6 is a timing chart showing a command and data occupying a circuit in the DRAM 1 in this case.

  First, when a “Norm.-W # 0” command is input, write data at address # 0 is written into the memory cell array 2a. The parity bit generation circuit 8 generates a parity bit at address # 0 from the input write data at address # 0, and the generated parity bit is written into the memory cell array 2b.

  Next, when the “Mask-W # 1” command is input, the write data at the address # 1 is latched in the first stage F / F1 of the write data line WDL. Further, the uncorrected data and the parity bit of the address # 1 are read from the memory cell arrays 2a and 2b and latched in the first stage F / F 3 inserted in the read data line RDL and the parity bit line RPL.

  Next, when the “Mask-W # 2” command is input, the write data at the address # 1 is in the next stage F / F2 of the write data line WDL, and the write data at the address # 2 is in the first stage F / F1. Latched. Further, the check bit generation circuit 9 generates a check bit from the data before correction of the address # 1 and the parity bit. The correction circuit 10 performs correction when a 1-bit error exists.

  The corrected data and the check bit are latched in the next stage F / F 4 inserted in the read data line RDL and the check bit line CBL, respectively. Then, the data and the parity bit at the address # 2 are read from the memory cell arrays 2a and 2b and latched in the first stage F / F 3 inserted in the read data line RDL and the parity bit line RPL.

  Next, when the “Mask-W # 3” command is input, the write data and the corrected data at the address # 1 are written into the memory cell array 2a through the multiplexer MP2. That is, the multiplexer MP2 selected by the mask data input together with the “Mask-W # 1” command selects the write data at the address # 1. The multiplexer MP2 not selected by the mask data selects the corrected data (data on the read data line RDL).

  The parity bit generation circuit 8 generates a parity bit at an address # 1 from the write data at the address # 1 and the corrected data, and the generated parity bit is written into the memory cell array 2b. The write data at address # 2 is latched in F / F2 at the next stage of write data line WDL, and the write data at address # 3 is latched at F / F1 at the first stage of write data line WDL.

  Further, the check bit generation circuit 9 generates a check bit from the uncorrected data and the parity bit of the address # 2 held in the first stage F / F 3 of the read data line RDL and the parity bit line RPL. The correction circuit 10 performs correction when a 1-bit error exists. The corrected data and the check bit are latched in the next stage F / F 4 inserted in the read data line RDL and the check bit line CBL, respectively. Then, the data and the parity bit at the address # 3 are read from the memory cell arrays 2a and 2b, and latched in the first stage F / F 3 inserted in the read data line RDL and the parity bit line RPL.

  Finally, when a “Norm.-W # 4” command is input, the write data at the address # 2 held in the F / F2 of the write data line WDL and the F / F1 of the write data line WDL are held. Write data of address # 3, read data line RDL and check bit line CBL of the corrected data and check bit of address # 2 held in F / F4, and read data line RDL and parity bit line RPL The uncorrected data and check bit of address # 3 held in F / F3 are held as they are. This control is performed by the control circuit 11 as described above.

  The write data at address # 4 is first written into the memory cell array 2a. The parity bit generation circuit 8 generates a parity bit at address # 4 from the write data at address # 4, and the generated parity bit at address # 4 is written into the memory cell array 2b.

  In the cycle in which the next “NOP” command is issued, the write data at the address # 2 held in the next stage F / F2 of the write data line WDL and the next stage F / F4 of the read data line RDL. Similarly, the corrected data of the address # 2 is selected through the multiplexer MP2 that selects connection by the mask data input together with the “Mask-W # 2” command, and is written in the memory cell array 2a, respectively. .

  The parity bit generation circuit 8 generates a parity bit at address # 2 from the write data at address # 2 and the corrected data, and the generated parity bit at address # 2 is written into the memory cell array 2b.

  Further, the check bit generation circuit 9 generates a check bit from the uncorrected data and the parity bit of the address # 3 held in the first stage F / F 3 of the read data line RDL and the parity bit line RPL. The correction circuit 10 performs correction when a 1-bit error exists. The corrected data and the check bit are latched in the F / F 4 at the next stage of the read data line RDL and the check bit line CBL, respectively. The write data at address # 3 is held in F / F2 at the next stage of write data line WDL.

  Then, in the last cycle in which the next “NOP” command is issued, the write data at the address # 3 is written into the memory cell array 2a. The parity bit generation circuit 8 generates a parity bit at address # 3 from the write data at address # 3 and the corrected data, and the generated parity bit at address # 3 is written into the memory cell array 2b.

  Since writing of all the write data and parity bits to the memory cell array is completed for the first time here, the word line WL can be deselected by inputting a precharge command in the next cycle and thereafter.

  As described above in detail, in the present embodiment, the DRAM 1 writes data having a normal data width necessary for the operation of the ECC circuit and data having a data width shorter than the normal data width. The DRAM 1 includes a data path DP2 that bypasses the data path DP1 for transmitting data having a short data width. Then, data having a normal data width is written into the memory cell array via the data path DP2.

  Therefore, according to the present embodiment, the write recovery time (tWR) is increased by two cycles only when at least one mask write command is issued during one row cycle, so that the mask write command is not issued during one row cycle. In this case, the write recovery time (tWR) does not increase. As a result, the write time when the mask write command is not issued can be shortened.

  In the present embodiment, the present invention can be similarly implemented by providing a data path DP2 and a multiplexer that bypass each of F / F1 and F / F2.

  Further, in this embodiment, two stages of F / Fs for performing late writing are inserted. However, the present invention is not limited to this, and it may be one stage or three or more stages.

(Second Embodiment)
In the second embodiment, the write time when data having the same address as the data held in the F / F is input is shortened compared to the first embodiment.

  FIG. 7 is a circuit diagram showing a main part of the DRAM 1 according to the second embodiment of the present invention. The DRAM 1 includes a data path DP2 that bypasses the flip-flop and a multiplexer for each of F / F1 and F / F2. That is, the DRAM 1 includes a data path DP2 and a multiplexer MP1 in order to bypass the F / F2. Further, the DRAM 1 includes a data path DP2 and a multiplexer MP5 in order to bypass the F / F1.

  The DRAM 1 includes a control circuit 13 that controls the F / F 2 and the multiplexer MP1. The DRAM 1 includes a control circuit 12 that controls the F / F 1 and the multiplexer MP5.

  The control circuit 12 includes an F / F 12a, an exclusive OR (XOR) circuit 12b, a NOR circuit 12c, an OR circuit 12d, an AND circuit 12e, and an OR circuit 12f. The control circuit 12 includes a mask write command (Mask-W), a clock signal CLK, an address at the time of a normal write command (address (normal write)), and an address at the time of a mask write command (address (mask write)). Is entered. Note that the F / F 12a and the XOR circuit 12b are provided in a number corresponding to the number of addresses.

  The address (normal write) is supplied to the XOR circuit 12b. The address (mask write) is supplied to the F / F 12a. The output part of the F / F 12a is connected to the XOR circuit 12b. The output part of the XOR circuit 12b is connected to the NOR circuit 12c. The F / F 12a, the XOR circuit 12b, and the NOR circuit 12c detect coincidence and mismatch between the address (normal write) and the address (mask write). The NOR circuit 12c outputs a high level address match signal AMS1 when the addresses match.

  The output part of the NOR circuit 12c is connected to the OR circuit 12d. The mask write command (Mask-W) is supplied to the OR circuit 12d and the OR circuit 12f. The output part of the OR circuit 12d is connected to the AND circuit 12e. The output part of the OR circuit 12f is connected to the multiplexer MP5. The clock signal CLK is supplied to the AND circuit 12e. An output part of the AND circuit 12e is connected to clock terminals of the F / F1 and the F / F 12a. The F / F1 and the F / F 12a respectively latch data based on the output of the AND circuit 12e.

  The control circuit 13 includes an F / F 13a, an exclusive OR (XOR) circuit 13b, a NOR circuit 13c, an OR circuit 13d, and an AND circuit 13e. A mask write command (Mask-W), a clock signal CLK, and an address (normal write) are input to the control circuit 13.

  The address (normal write) is supplied to the XOR circuit 13b. The input unit of the F / F 13a is connected to the output unit of the F / F 12a. The output part of the F / F 13a is connected to the XOR circuit 13b. The output part of the XOR circuit 13b is connected to the NOR circuit 13c. F / F 13a and XOR circuits 13b are provided in a number corresponding to the number of addresses, respectively. The F / F 13a, the XOR circuit 13b, and the NOR circuit 13c detect coincidence and mismatch between the address (normal write) and the address (mask write). The NOR circuit 13c outputs a high level address match signal AMS2 when the addresses match.

  The output part of the NOR circuit 13c is connected to the OR circuit 13d. The mask write command is supplied to the OR circuit 13d and the multiplexer MP1. The output part of the OR circuit 13d is connected to the AND circuit 13e. The clock signal CLK is supplied to the AND circuit 13e. The output part of the AND circuit 13e is connected to clock terminals of the F / F2 and the F / F 13a.

  The output part of the NOR circuit 13c is connected to the input parts of the OR circuit 12d and the OR circuit 12f. That is, the address match signal AMS2 (output of the NOR circuit 13c) output from the control circuit 13 is supplied to the control circuit 12.

  The operation of the control circuits 12 and 13 configured as described above will be described. When the “Mask-W” command is input, the control circuit 12 cancels the gating of the clock signal CLK and operates the F / F1. At this time, the F / F 12a also operates, and the F / F 12a latches an address (mask write). Thereby, the F / F 12a holds an address corresponding to the data held in the F / F1.

When the “Norm.-W” command is input and the address input together with the “Norm.-W” command is the same address as the address held in the F / F 12a, the address match signal of the control circuit 12 AMS1 goes high. Thereby, the control circuit 12 operates F / F1. At this time, the F / F 12a also operates. That is,
When the “Mask-W” command is input, the control circuit 13 cancels the gating of the clock signal CLK and operates the F / F2. As a result, the F / F 2 latches the data held by the F / F 1. At this time, the F / F 13a also operates, and the F / F 13a latches the address (mask write) held by the F / F 12a. As a result, the F / F 13a holds an address corresponding to the data held in the F / F2.

  When the “Norm.-W” command is input and the address input together with the “Norm.-W” command is an address different from the address held in the F / F 13a, the control circuit 13 sets the F / F2 Does not work.

  When the “Norm.-W” command is input and the address input together with the “Norm.-W” command is the same address as the address held in the F / F 13a, the address match signal of the control circuit 13 AMS2 goes high. Thereby, the control circuit 13 operates F / F2. At this time, the F / F 13a also operates.

  Further, the address match signal AMS2 is also supplied to the control circuit 12. Therefore, the control circuit 12 operates F / F1. At this time, the F / F 12a also operates.

  When the “Norm.-W” command is input and the address input together with the “Norm.-W” command is an address different from the address held in the F / F 12a, the control circuit 13 supplies the address. When the signal AMS2 is at a high level, the control circuit 12 operates the F / F1.

  When the “Norm.-W” command is input and the address input together with the “Norm.-W” command is an address different from the address held in the F / F 12a, the control circuit 13 supplies the address. When the signal AMS2 is low level, the control circuit 12 does not operate the F / F1. That is, the control circuit 12 gates the clock signal CLK.

  The control circuit 12 is also connected to the first stage F / F 3 and the multiplexer MP3 inserted in the read data line RDL and the parity bit line RPL. The control circuit 13 is also connected to the next-stage F / F 4 and the multiplexer MP4 inserted into the read data line RDL and the check bit line CBL. Therefore, the F / F 3 and the multiplexer MP3 operate in the same manner as the F / F 1 and the multiplexer MP5, respectively. Further, the F / F 4 and the multiplexer MP4 operate in the same manner as the F / F 2 and the multiplexer MP1, respectively.

  Next, the operation of the DRAM 1 configured as described above will be described. The timing chart showing the state of command input and the data occupying the circuit in the DRAM 1 is the same as FIG. 4 when the “Norm.-W” command is continuously input. When the “Mask-W” command is continuously input, the process is the same as in FIG. When the “Norm.-W” command and the “Mask-W” command are input together, the operation is the same as in FIG.

  The “Norm.-W” command and the “Mask-W” command are mixedly input, and the address of the input “Norm.-W” command is the same as the address held in the F / F. The case of an address will be described with reference to FIG. First, the process is the same as in FIG. 6 until the “Mask-W # 3” command is input. After that, when the “Norm.-W # 2” command is input, it becomes the same as the address of the “Mask-W # 2” command input two cycles before, and therefore slightly different from the case of FIG.

  In this cycle, the operation when the “Norm.-W # 2” command is input is the same as that in FIG. 6. Write data and the corrected data and check bit of the address # 2 held in the next stage F / F 4 of the read data line RDL are lost. First, the check bit generation circuit 9 generates a check bit from the uncorrected data and the parity bit of the address # 3, and the correction circuit 10 corrects when a 1-bit error exists. The corrected data and the check bit are latched in the next stage F / F 4 inserted in the read data line RDL and the check bit line CBL, respectively.

  Then, in the next last cycle, the write data at address # 3 is written into the memory cell array 2a, and the parity bit generation circuit 8 determines the address # 3 from the input write data at address # 3 and the corrected data. Parity bits are generated, and the generated parity bits are written into the memory cell array 2b.

  Since writing of all the write data and parity bits to the memory cell is completed for the first time here, the word line WL can be deselected by inputting a precharge command in the next cycle and thereafter.

  As described above in detail, according to the present embodiment, when a mask write command is input at least once in one row cycle, the addresses of normal write commands input in one row cycle are added two commands before. If it is the same as the address of the mask write command input so far, the write recovery time (tWR) can be reduced by one cycle compared to the first embodiment. Therefore, the write recovery time (tWR) in this case can be increased by one cycle.

  Further, in this embodiment, two stages of F / Fs for performing late writing are inserted. However, the present invention is not limited to this, and it may be one stage or three or more stages.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

1 is a block diagram showing a configuration of a DRAM 1 according to a first embodiment of the present invention. 3 is a circuit block diagram showing the configuration of a memory cell array 2 and a data line circuit 3. FIG. The circuit diagram which shows the structure of the control circuit 11 which controls operation | movement of a multiplexer and a flip-flop. 6 is a timing chart showing commands and data occupying a circuit in the DRAM 1 when normal write commands are continuously input. 6 is a timing chart showing commands and data occupying circuits in the DRAM 1 when mask write commands are continuously input. 6 is a timing chart showing a command and data occupying a circuit in the DRAM 1 when a normal write command and a mask write command are mixedly input. The circuit diagram which shows the principal part of DRAM1 which concerns on the 2nd Embodiment of this invention. 6 is a timing chart showing a command and data occupying a circuit in the DRAM 1 when the address of the normal write command is the same address as the address held in the F / F. The circuit block diagram which shows an example of DRAM which has an ECC circuit. The circuit block diagram which shows an example of DRAM which has an ECC circuit. The circuit block diagram which shows an example of DRAM which has the ECC circuit which implement | achieves writing in the data width shorter than the data width required for an ECC circuit to operate | move. 4 is a timing chart showing commands and data occupying a circuit in the DRAM. FIG. 12 is a circuit block diagram showing a configuration example of a DRAM 1 in which two stages of flip-flops are inserted in the data path of FIG. 11. 4 is a timing chart showing commands and data occupying a circuit in the DRAM 1.

Explanation of symbols

  WDL ... Write data line, RDL ... Read data line, RPL ... Parity bit line, WPL ... Parity bit line, CBL ... Check bit line, DP1, DP2 ... Data path, F / F1, F / F2, F / F3, F / F4, F / F5, F / F6, 12a, 13a ... flip-flop, MP1, MP2, MP3, MP4, MP5 ... multiplexer, DR1, DR2, DR3, DR4, DR5 ... driver circuit, INV ... inverter circuit, TG1, TG2 ... transmission gate, 1 ... DRAM, 2 ... memory cell array, 2a ... data memory cell array, 2b ... code memory cell array, 3 ... data line circuit, 4 ... word line circuit, 5 ... memory control circuit, 7a, 7b ... Column selection circuit, 8 ... parity bit generation circuit, 9 ... check bit generation times , 10 ... correction circuit, 11, 12, 13 ... control circuit, 11a, 12e, 13e ... the AND circuit, 12b, 13b ... exclusive OR circuit, 12c, 13c ... NOR circuit, 12d, 12f, 13d ... OR circuit.

Claims (5)

A memory cell array including a plurality of memory cells;
An input circuit to which first data having a first data width and second data having a second data width shorter than the first data width are input;
A generating circuit that generates a code that is generated in units of the first data width and corrects errors in the first and second data;
A first write circuit for writing the first data to the memory cell array;
A second write circuit for setting a latency, which is a time from when the address of the second data is designated to when the address is written to the memory cell array, to be longer than the latency of the first data, and for writing the second data into the memory cell array When,
And a control circuit for writing the first data to the memory cell array prior to the second data when the first data is input after the second data is input. apparatus. The second write circuit includes: a holding circuit that holds second data input to the input circuit; and a conversion circuit that converts the second data width into the first data width. The semiconductor memory device according to Item 1. The first writing circuit includes a first data path for transmitting the first data;
The second writing circuit includes a second data path for transmitting the second data;
The control circuit selects the second data path when the second data is input, and selects the first data path when the first data is input and 3. The semiconductor memory device according to claim 2, wherein the operation is stopped.   The control circuit includes a detection circuit that detects whether an address of the second data held in the holding circuit matches an address of the first data input to the input circuit, and the holding circuit The second data held in the holding circuit is canceled when the address of the second data held in the memory matches the address of the first data inputted in the input circuit. 2. The semiconductor memory device according to 2 or 3.   The conversion circuit uses the second data width of the second data input to the input circuit and the data corresponding to the address of the second data stored in the memory cell array and input to the input circuit. 5. The semiconductor memory device according to claim 2, further comprising a selection circuit that selects third data necessary for conversion into the first data width.

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