JPH04319670A - Acquisition circuit - Google Patents

Abstract

PURPOSE:To realize an acquisition circuit of a digital oscilloscope capable of detecting the rising and falling glitch generated between samples to store the same. CONSTITUTION:An acquisition circuit is provided with positive and negative voltages, an A/D converter circuit 1, a circuit converting the output of the A/D converter circuit 1 to an analogue value, a subtraction circuit 3 outputting the difference between the signal subjected to D/A conversion and an input signal and a circuit comparing the signal inputted from the subtraction circuit with positive and negative reference voltages are provided. Further, glitch detection circuits 8, 9 detecting glitch on the basis of the signal from the comparison circuit and a memory means 10 storing the digital signal from an A/D converter means and the signals from the glitch detection circuits 8, 9 are provided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an acquisition circuit for a digital oscilloscope, and more particularly to an acquisition circuit having a function of detecting and storing glitches that occur between data samples when observing a logic waveform.

0002

2. Description of the Related Art A conventional digital oscilloscope samples an input waveform at regular time intervals, stores the sampled data in a storage device, and displays the data based on the stored data and specified arithmetic processing.

0003

[Problem to be solved by the invention] When using such a digital oscilloscope to observe waveforms such as logic waveforms over a certain period of time, the storage capacity is limited, so it is necessary to slow down the sampling speed. There is a need to. However, the waveforms obtained in this way have a considerably reduced amount of information, and there is a problem in that even if changes such as glitches occur between samples, they cannot be detected. The present invention has been made to solve these problems, and its purpose is to realize an acquisition circuit for a digital oscilloscope that can observe changes such as glitches that occur between samples. do.

0004

[Means for Solving the Problems] The present invention provides an A/D conversion circuit that converts an analog input signal into a digital signal;
a D/A conversion circuit that converts a digital signal input from the A/D conversion means into an analog signal; a subtraction circuit that outputs a difference between the analog signal input from the D/A conversion means and the input signal; and the subtraction circuit. a first comparison circuit that compares the output signal of the circuit with a positive reference voltage; and a second comparison circuit that compares the output signal of the subtraction circuit with a negative reference voltage;
a first glitch detection circuit that receives the signal from the first comparison circuit and detects a rising glitch; and a second glitch detection circuit that receives the signal from the second comparison circuit and detects a falling glitch. , an acquisition circuit characterized in that it is provided with storage means for inputting and storing the digital signal inputted from the A/D conversion means and the signals from the first and second glitch detection circuits.

[0005]

[Operation] By comparing the A/D converted data of the input signal with the data before being converted into a comparator, glitches that could not be captured by sampling can be detected, and the A/D conversion data can be detected.
It is added to the D-converted data and stored in memory.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a basic configuration diagram of the present invention.

Reference numeral 1 denotes an A/D conversion circuit which receives an analog input signal and converts it into a digital signal. 2 is a D/A conversion circuit that converts the digital signal converted by the A/D conversion circuit into an analog signal. 3 is a subtraction circuit which calculates the difference in magnitude between the two by subtracting the analog signal output from the D/A conversion circuit from the input signal. 4 is a positive reference voltage, 5 is a negative reference voltage, 6 is a comparator that compares the output of the subtraction circuit with the positive reference voltage, and 7 is a comparator that compares the output of the subtraction circuit with the negative reference voltage. 8 is a first glitch detection circuit that detects a glitch from the result of the comparator 6; 9 is a second glitch detection circuit that detects a glitch from the result of the comparator 7; 10 is an A/D conversion circuit 1
This memory stores data output from the glitch detection circuits 8 and 9. In such a configuration, an input signal is sampled and converted into a digital signal by the A/D conversion circuit 1. This data is D/A converted into an analog signal again, and the data is subtracted from the original input signal by a subtraction circuit 3. For example, suppose that a positive glitch occurs with respect to the original input signal, as shown in FIG. At this time, there is a relationship such as (potential of the original input signal) ≧ (potential of the D/A converted analog signal), and if this difference is greater than or equal to the value set by the positive reference voltage 4, the comparator 5 Then output "H". In the glitch detection means 8, this comparator 5
latches the "H" output. The data output from the A/D converter circuit 1 at the time of sampling with this "H" output is stored in the memory 10 at the same time as the data that is output from the glitch detection means 8 and has information indicating that a positive glitch has occurred. Stored. Further, as shown in FIG. 7, it is assumed that a negative glitch occurs with respect to the original input signal. At this time, there is a relationship: (potential of the original input signal) ≦ (potential of the D/A converted analog signal), and if this difference is greater than or equal to the value set by the negative reference voltage 5, the comparator 6 Then output "H". The glitch detection means 9 latches the "H" output of the comparator 6. This “H”
A/D conversion circuit 1 at the time of sampling with the output of “
The data outputted from the glitch detection means 9 is stored in the memory 10 at the same time as the data outputted from the glitch detection means 9 which has information indicating that a negative glitch has occurred.

FIG. 2 is a block diagram of a first embodiment of the present invention. In the figure, the same parts as in FIG. 1 are given the same reference numerals. This embodiment specifically shows the glitch detection circuits 8 and 9 in the configuration diagram of the present invention described above. 12,
13 is an OR gate, 11 is a clock signal generator, b1~
b8 is a D type latch. These D-type latches b1 and b2, b3 and b4, b5 and b6, and b7 and b8 work as a master-slave flip-flop by combining two of each. The clock signal generator 11 converts SampleClock into the A/D conversion circuit 1.
input for sampling, and set Reset1 to the Sa
D type latch b with twice the period of mpleClock
1, b2, b5, b6, and input Reset2 to the S
The cycle is twice that of ampleClock and Reset1
It is input to D-type latches b3, b4, b7, and b8 with the opposite phase. The outputs of the D-type latches b2 and b4 are stored in the memory 10 via the OR gate 12, and are stored in the D-type latch b6.
, 8 are stored in the memory 10 via the OR gate 13.

FIG. 4 is a time chart showing the operation of the first embodiment. At the rising edge of SampleClock output from the clock signal generation circuit 11, the A/D conversion circuit 1 samples the input signal and resets the input signal.
1 and Reset2, D type latches b1, b2,
b5, b6 and D-type latches b3, b4, b7, b8 are reset alternately. The reference voltage generators 4 and 5 are set to generate voltages (±VD). This is shown in Figure 4,
This is shown at the dotted line level in FIGS. 6 and 7. A/D
The conversion circuit 1 receives an input signal as shown in FIG. 4 and samples it at the points indicated by black circles. A voltage resulting from D/A conversion of this sample result is output from the D/A conversion circuit 2. The subtraction circuit 3 inputs the input signal and the analog signal from the D/A conversion circuit 2, and outputs the amount of change when the input signal changes during sampling. The output from this subtraction circuit 3 is the voltage of the reference voltage generation circuit 4 (+VD
), the output of the comparator 6 becomes "H", and at its rising edge, at least one of the D-type latches b1 and b3 becomes "H". After that, when the output from the subtraction circuit 3 becomes lower than the voltage (+VD) of the reference voltage generation circuit 4 before the reset signal is generated, the output of the comparator 6 becomes "L", and the D-type latch is activated at the falling edge. Since at least one of b2 and b4 becomes "H", the output of the OR gate 12 becomes "H". Similarly, the output from the subtraction circuit 3 is the voltage (-V) of the reference voltage generation circuit 5.
D ), the output of comparator 7 becomes "H", and at the rising edge, D type latches b5 and b7
At least one of them becomes "H". Thereafter, if the output from the subtraction circuit 3 exceeds the voltage (+VD) of the reference voltage generation circuit 5 before the reset signal is generated, the comparator 6
The output of the OR gate 13 becomes "L", and at least one of the D-type latches b6 and b8 becomes "H" at the falling edge, so the output of the OR gate 13 becomes "H". As a result, when the input signal rises between samples (if a glitch occurs), the output of the OR gate 12 becomes "H", and when the input signal falls, the output of the OR gate 13 becomes "H".
These signals are stored in the memory 10 at the same time as the digital signals output from the A/D conversion circuit 1. For this reason, the G.I. D display (Glitch Detection
It can now be expressed as shown in (n display).

FIG. 3 is a block diagram of a second embodiment of the present invention. Similar to the first embodiment, this embodiment specifically shows the glitch detection circuits 8 and 9 in the block diagram of the present invention shown in FIG. a1 to a4 are D flip-flops. The clock signal generator 11 generates a sample clock (S
sampleClock) is inputted to the A/D conversion circuit 1 for sampling, a reset signal (Reset1) is inputted to the D flip-flops a1 and a3 at a cycle twice that of the sample clock (SampleClock),
The reset signal (Reset2) is
The period is twice that of ock and the reset signal (Reset
1) is input to the D flip-flops a2 and a4 with an opposite phase. The outputs of the D flip-flops a1 and a2 are stored in the memory 10 via the OR gate 12, and the outputs of the D flip-flops a3 and a4 are stored in the memory 10 via the OR gate 13.

FIG. 5 is a time chart showing the operation of the second embodiment. At the rising edge of SampleClock output from the clock signal generation circuit 11, the A/D conversion circuit 1 samples the input signal and resets the input signal.
1 and Reset2, D flip-flops a1 and D
Flip-flop a2 is alternately D flip-flop a
3 and D flip-flop a4 are reset alternately. The reference voltage generators 4 and 5 are set to generate voltages (±VD). This is shown at the dotted line level in FIGS. 3, 6, and 7. The A/D conversion circuit 1 receives an input signal as shown in the input signal of FIG. 3 and samples it at the points indicated by black circles. A voltage resulting from D/A conversion of this sample result is output from the D/A conversion circuit 2. The subtraction circuit 3 inputs the input signal and the analog signal from the D/A conversion circuit 2, and outputs the amount of change when the input signal changes during sampling. When the output from the subtraction circuit 3 exceeds the voltage (+VD) of the reference voltage generation circuit 4, the output of the comparator 6 becomes "H", and at its rising edge, at least one of the D flip-flops a1 and a2 becomes "H".
The output of the OR gate 12 becomes "H".Similarly, when the output from the subtraction circuit 3 becomes lower than the voltage (-VD) of the reference voltage generation circuit 5, the output of the comparator 7 becomes "H". At the rising edge, at least one of the D flip-flops a3 and a4 becomes "H", so the output of the OR gate 13 becomes "H".As a result, when the input signal rises between samples, the output of the OR gate 12 becomes "H".
When the input signal falls, the output of the OR gate 13 becomes "H", and these signals are sent to the A/D conversion circuit 1.
is stored in the memory 10 at the same time as the digital signal outputted by. In this embodiment, by detecting edges between samples, the E. D display (EdgeDetec
tion display).

Note that the means for storing information in which a glitch has occurred in the memory 10 is such that, for example, the digital signal output from the A/D conversion circuit 1 is 8 bits, the output of the OR gate 12 is the 9th bit, and the output of the OR gate 13 is 8 bits. It is also possible to input the output at the 10th bit and store it in the memory 10 as 10-bit data. Alternatively, input the OR of the output of the OR gate 12 and the output of the OR gate 13 into the 9th bit, store it in the memory 10 as 9-bit data, and a rising glitch may have occurred during arithmetic processing during display, or a falling glitch may have occurred. It is also possible to determine whether the user has done so and display the information accordingly.

[0013]

As explained above, according to the present invention, it is possible to realize an acquisition circuit such as a digital oscilloscope that can detect and store the rising and falling edges that occur between samples. Observation became possible.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of the present invention.

FIG. 2 is a diagram showing a first embodiment of the present invention.

FIG. 3 is a diagram showing a second embodiment of the invention.

FIG. 4 is a time chart showing the operation of the first embodiment of the present invention.

FIG. 5 is a time chart showing the operation of the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of a rising glitch in an input signal between samples.

FIG. 7 is an explanatory diagram of a falling glitch in an input signal between samples.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... A/D conversion circuit, 2... D/A conversion circuit, 3... Subtraction circuit, 4... Positive reference voltage, 5... Negative reference voltage, 6, 7... Comparator, 8, 9... Glitch detection circuit, 10 ...Memory, 11...Clock signal generation circuit, 12, 13...OR gate, a1-a4...D flip-flop, b1-b8...D
Type latch.

Claims (1)

[Claims] 1. An A/D conversion circuit that converts an analog input signal into a digital signal; a D/A conversion circuit that converts the digital signal input from the A/D conversion means into an analog signal; a subtraction circuit that outputs the difference between the analog signal input from the conversion means and the input signal; a first comparison circuit that compares the output signal of the subtraction circuit with a positive reference voltage; and an output signal of the subtraction circuit. a second comparison circuit that compares the signal with a negative reference voltage; a first glitch detection circuit that receives the signal from the first comparison circuit and detects a rising glitch; a second glitch detection circuit that receives the input signal and detects a falling glitch;
The digital signal input from the A/D conversion means and the first
and a storage means for inputting and storing the signal from the second glitch detection circuit.