JPH04318718A - Data processing unit - Google Patents

Abstract

PURPOSE:To allow a receiver side of an output data to surely detect it that an information bit of a user information transfer channel (TCH) is stolen through a high speed additional control channel (FACCH) of plural frame interleave signals in a data processing unit such as a digital automobile telephone set or the like. CONSTITUTION:Transmission data of a mobile station 1 is sent from a demodulation section 5 of a base station 2 to a data processing unit 6 and a control section 8 detects the presence of steal. Data equivalent to an interleaved number of a channel FACCH is stored once in a memory section 7 even in the case of data conversion processing of a channel TCH not interleaved, and after no steal in existence after interleave and delay is confirmed, a data conversion processing section 9 converts the data into a data for a public line and the converted data is outputted from an output section 10. Upon the detection of steal, a data stored in a memory section 7 is replaced into a specific pattern surely detected by error detection or the like at the reception side of an output data and the result is outputted after conversion processing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device used in digital car phones, mobile phones, and the like.

0002

[Prior Art] A data processing device is a device provided at the base station side of a digital car phone or mobile phone system, and is used to process transmission data in a system-specific format that is sent and received between a mobile station and a base station, and which is used on a public line. This is a device that performs conversion processing with transmission data in a format that is The data to be converted is an audio signal or a fax
These are non-audio signals such as

FIG. 3 shows the configuration of such a conventional data processing device. In FIG. 3, 21 is a mobile station, 22
is the base station. 23 and 24 are antennas, and 25 is a demodulator. A data processing device 26 includes a data conversion processing section 27, a control section 28, and an output section 29.

Next, the operation of the above conventional example will be explained. Data transmitted from the mobile station 21 through the antenna 23 is received at the base station 22 through the antenna 24, and is sent from the demodulator 25 to the data processing device 26 as received data. If the transmitted data is a non-voice signal that is not interleaved, unlike a multi-frame interleaved voice signal that undergoes voice decoding processing, no interleaving delay is required, so each frame is converted into a public line data format. It is possible to output it as follows. For this reason, in the conventional data processing device, the control unit 28 detects the steal and immediately converts each frame into public line data and outputs it from the output unit 29.

FIG. 4A shows data transmitted from a mobile station 21 with 20 ms as one frame, received by the base station 22 side, and input to the data processing device 26 using a user information transfer channel (hereinafter referred to as TCH). It is a figure showing the data of ). In this figure, the data is not interleaved, and in frames 32 and 33 the TCH is a two-frame interleaved signal, the fast associated control channel (
Hereinafter, it will be abbreviated as FACCH. ) has been stolen by. Here, stealing refers to temporarily replacing TCH with FACCH. This FACCH is temporarily TC
This is a control channel that steals H and performs data transfer at high speed. Further, the FACCH identification bit (hereinafter abbreviated as FST bit) indicating that the input data is stolen data becomes 1 in the frame 33 that transmits FACCH in the latter half.

FIG. 4(b) shows output data after data conversion by the data processing device 26. The data processing device 26 detects steals for each frame by checking the FST bit in the control unit 28. Frames 31 and 32 whose FST bit is 0 are immediately subjected to data conversion and output as frames 34 and 35. Frame 33 with FST bit set to 1
is determined to have been stolen by FACCH, and a specific pattern (indicated by p in the figure) that can be reliably detected by error detection, etc. performed on the TCH information bit of frame 33 on the receiving side of the output data of the data processing device 26. ), convert it, and output it to the public line. At this time, there is no interleaving delay in the data processing device 26. Furthermore, on the receiving side which receives this output data via the public line, error detection is performed on the information bits of each frame.

[0007]

However, in the conventional data processing device described above, for a frame in which the FST bit is 1, such as frame 33 in FIG. Since the data is replaced, converted, and output as shown in frame 36, the receiving side that receives this output data via the public line can reliably detect, through error detection, etc., that the data is missing information bits due to stealing. However, in data such as frame 35, the information bits do not have a specific pattern, so even though half of the information bits are FACCH signals, it is certain that the information bits are missing due to error detection etc. There was a problem that it was not always possible to detect the

[0008] The present invention is intended to solve such conventional problems, and an object of the present invention is to provide an excellent data processing device that can reliably detect data in which information bits are missing due to being stolen. It is.

[0009]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a data processing device with an FS for each frame.
a control unit that checks the T bit to detect stealing due to FACCH; a memory unit that stores data for the number of interleaves of the multiple frame interleaved signal;
It is equipped with a processing section that converts data with an interleaving delay and an output section that outputs the converted data. The information bits of the TCH stolen by FACCH, including the frame, are replaced with a specific pattern that can be reliably detected by error detection on the receiving side of the output data, and then converted and output.

0010

[Operation] Therefore, according to the present invention, TCH is
By replacing frames with missing information bits on the TCH due to being stolen by the CH with data of a specific pattern in the data conversion processing unit, converting them, and outputting them, the receiving side of the output data can eliminate the missing information bits. This has the effect of being able to reliably detect data that has been detected.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of a data processing apparatus according to an embodiment of the present invention. In FIG. 1, 1 is a mobile station;
2 is a base station. 3 and 4 are antennas, and 5 is a demodulator. 6 is a data processing device, which includes a memory section 7 and a control section 8.
, a data conversion processing section 9 and an output section 10.

Next, the operation of the above embodiment will be explained. When non-interleaved non-voice data is transmitted from the mobile station 1 through the antenna 3, the received data received at the base station 2 through the antenna 4 is sent from the demodulator 5 to the data processing device 6. This input data is temporarily stored in the memory unit 7 as much data as the number of FACCH interleaves (assumed to be 2 frames), and is delayed by one frame as an interleaving delay while the control unit 8 detects stills, and then data conversion processing is performed. A unit 9 performs a conversion process to public line data, and outputs it from an output unit 10.

FIG. 2A is a diagram showing the TCH of data transmitted from the mobile station 1 in one frame of 20 ms, received by the base station 2, and input to the data processing device 6. In this figure, the data is not interleaved and TCH is 2 in frames 12 and 13.
It is stolen by the frame interleaving signal FACCH. Further, the FST bit indicating that the input data is stolen data is set to 1 in frame 13 that transmits the latter half of the FACCH.

FIG. 2(b) shows output data after data conversion by the data processing device 6. The data processing device 6 detects steals for each frame by checking the FST bit in the control unit 8. F
For frame 11 whose ST bit is 0, after receiving the next frame, confirm that the FST bit of frame 12 is also 0 and that frame 11 does not contain a FACCH signal, and then transmit the data. Performs conversion processing and outputs. On the other hand, in frame 12, the FST bit is 0, but since the FST bit of the next frame 13 is 1, it can be seen that frame 12 contains the FACCH signal. Then, the information bits of the TCH of frame 12 are replaced with a signal of a specific pattern (indicated by p in the figure) that can be reliably detected by error detection performed on the receiving side of the output data of the data processing device 6, and then conversion processing is performed. and output to public line. Also,
Frame 13 has a FST bit of 1, and even if the FST bit of the next frame is 0, frame 13 has a FAC
Since it is clear that a CH signal is included, as in frame 16, the TCH information bits are replaced with a specific pattern signal, converted, and output to the public line in the same manner as in frame 12. That is, the data conversion processing section 9
In this case, the input data is not immediately converted and output, but after a delay of one frame, the data is converted and output based on the judgment of the control section 8.

As described above, according to the above embodiment, the data conversion processing unit which provides interleaving delay for data included in a frame in which TCH information bits are missing due to stealing of FACCH of a multi-frame interleaved signal. , the receiving side that receives the output data via the public line replaces it with a specific pattern that can be detected by error detection, performs conversion processing, and outputs it to the public line, so the receiving side of the output data can steal the data as soon as an error is detected. This has the effect of reliably detecting data with missing information bits.

[0016]

Effects of the Invention As is clear from the above embodiments, the present invention provides an interleaving delay in a data processing device, and when a steal due to FACCH is detected, not only the frame in which the steal was detected but also the frame is stored in the memory. The stolen TCH information bits, including past frames, are replaced with a specific pattern that can be reliably detected by error detection on the output data receiving side, and then converted and output. This has the effect that on the receiving side, which receives this output data via the public line, data in which information bits are missing due to stealing can be reliably detected by error detection or the like.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a data processing device in an embodiment of the present invention.

[Figure 2] (a) is a diagram showing the arrangement of input data to the same device; (b) is a diagram showing the arrangement of output data from the same device;

[Figure 3
] Schematic block diagram of conventional data processing device

[Figure 4] (a
) is a diagram showing the arrangement of input data to the same device; (b) is a diagram showing the arrangement of output data from the same device.

[Explanation of symbols]

1 Mobile station 2 Base station 3 Antenna 4 Antenna 5 Demodulation section 6 Data processing device 7 Memory section 8 Control section 9 Data conversion processing section 10 Output section 11. Unstealed data

Claims (1)

[Claims] [Claim 1] On the transmitting side, the high-speed associated control channel steals the user information transfer channel and is transmitted as a multi-frame interleaved signal, and on the receiving side, the received data is data stolen by the high-speed associated control channel. a control unit for use in a digital data transmission system in which an identification bit indicating the information changes only in the final frame of an interleaved high-speed associated control channel, and for checking the identification bit for each frame to detect stealing of information bits; , comprising a memory unit for storing data for the number of interleavings of the high-speed associated control channel which is a multi-frame interleaved signal, a data conversion processing unit having an interleaving delay, and an output unit for outputting the converted data. , when the control unit detects a steal, the data conversion processing unit converts not only the frame in which the steal was detected, but also the past frames stored in the memory unit, from the stolen user via the high-speed associated control channel. A data processing device characterized in that information bits of an information transfer channel are replaced with a specific pattern that can be reliably detected by error detection or the like on a receiving side of output data, and the converted data is converted and outputted from the output section.