JPH04318678A - Logical design verification system - Google Patents

Abstract

PURPOSE:To automatically, efficiently, and accurately carry out each processing of logical verification failure verification, and circuit rule verification on initial design data for a logical circuit without manual work. CONSTITUTION:Initial design data 1 to be verified is input to a verification section 5 to carry out logical verification, failure verification and circuit rule verification in accordance with a prescribed procedure. A result of this series of verifications and a standard 7 are compared and discriminated by a discriminating section 6, and if there is a necessity of correcting the circuit and actually it is necessary to correct the circuit, the method of correcting the circuit is analysed by an analysis section 8, and the circuit is corrected by a correcting section 9 in accordance with the result of the analysis. Design data that is obtained after this correction is repeated for processing to generate complete design data.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD The present invention relates to a logic design verification system, and in particular to a logic design verification system for initial design data regarding logic circuits.
The present invention relates to a logic design verification system for performing fault verification and circuit rule verification.

0002

[Prior Art] Conventional logic verification systems of this type check whether the initial design data is designed correctly according to logic standards, whether it is designed to detect 0 and 1 faults, and whether it satisfies circuit standards. It relies on human labor to verify whether it is designed to do what it does.

[0003] If these standards are not met, the circuit must be modified, and this modification is also done manually.
The reality is that the revised data is then repeatedly verified manually.

[0004] As described above, conventional logic design verification systems require human intervention in analysis verification processing and design data correction processing, which is time consuming and inevitably involves human errors. It has the disadvantage that it needs to be used many times and verification efficiency is low.

[0005]

OBJECTS OF THE INVENTION An object of the present invention is to provide a logic design verification system that automatically performs logic verification, eliminates manual verification and correction, and enables efficient logic verification.

[0006]

[Structure of the Invention] The logic design verification system according to the present invention has the following features:
an input pattern generating means for generating all possible combinations of input conditions for all input terminals in a logic circuit to be verified; , a simulation means for generating an output pattern at the output terminal of each component of the logic circuit to be verified; a comparison means for comparing the output pattern with a normal output pattern; and when an output mismatch is detected by the comparison. The present invention is characterized in that it includes circuit searching means for searching the circuit from the mismatched output toward the input and detecting a starting point of mismatch in the output, and correction means for modifying the circuit at the detected point.

Another logic design verification system of the present invention includes input pattern generation means for generating all possible combinations of input conditions for all input terminals in a logic circuit to be fault verified, and simulation means that executes simulation while supplying one pattern to the input terminal and generates an output pattern at the output terminal of each component of the logic circuit to be fault verified; A means for generating a fault list that generates a list of output terminals, a means for simulating a fault by setting a logic value of 0 (or 1) to all of these input/output terminals, and a means for simulating a fault by setting a logic value of 0 (or 1) to all of these input/output terminals; When a change occurs, a circuit modification means searches for an input terminal of a circuit element connected to an output terminal set to be faulty and directly derives an output terminal from this input terminal, and a circuit modification means re-simulates in this modification circuit by the simulation means. and a control means for controlling the correction circuit to execute the failure simulation again, and comparing the simulation results in the correction circuit and the failure simulation results, and when the output values match, the control means controls the correction circuit to execute the failure simulation again. means for controlling the execution of the correction means and the control means, and when the output values do not match and the output value of the fault simulation does not change, the input terminal corresponding to the mismatched or changed output terminal is deleted from the fault list; The present invention is characterized in that it includes means for moving the operation to the fault simulation again according to the deleted fault list, and the respective means are executed until all the contents of the fault list are deleted.

Still another logic design verification system of the present invention includes a circuit rule storage table in which circuit rules are determined in advance and stored therein, and a circuit rule for detecting whether or not a logic circuit subject to circuit rule verification matches the circuit rule. The present invention is characterized in that it includes a verification means, and means for correcting the circuit according to the rule when the verification result indicates a violation of the rule.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention. This embodiment includes an editor 2 that receives initial design data 1 regarding the created logic circuit as input, a compiler 3 that encodes the design data in this editor 2, and a loader 4 that temporarily receives this compiled code. A verification section 5 receives the code from the loader 4 and performs each verification of the logic design (logic verification, failure verification, circuit rule verification), and a determination is made by comparing the verification results with preset standard data 7. A part 6, an analysis part 8 which discovers which part of the design data caused the error when an error occurs in the determination result, and an analysis part 8 which determines how to correct the design data that is the cause of the error. It consists of a correction section 9.

A designer of a logic circuit first creates and inputs initial design data 1 on the editor 2 . This initial design data 1
is converted by the compiler 3 into a code suitable for the verification unit 5 and output to the loader 4.

[0012] The loader 4 directly passes this code to the verification unit 5.
The verification unit 5 performs logic design verification, and the result is output to the determination unit 6. The determination unit 6 compares the verification result with the standard 7, and if the content of the standard is satisfied, the verification ends normally. If the content of the standard is not met, the analysis unit 8 will ask which part of the initial design data 1 meets the standard 7.
An analysis request will be issued to see if it does not match.

[0013] The analysis section 8 narrows down the portions that violate the standard 7, determines the content of correction, and issues correction instructions to the correction section 9. The modification unit 9 modifies the initial design data and outputs the modified data to the editor 2. Thereafter, verification is performed again by the verification unit 5 via the compiler 3 and loader 4, and the above-described processing is repeated.

Next, each verification processing operation will be explained in detail using the system shown in FIG.

First, the logic verification processing operation will be explained with reference to the flowchart shown in FIG. Logic standard 7 (FIG. 1) in this case is shown as data in FIG. 2, and a circuit as initial setting data to be subjected to logic verification is shown in FIG. In the logic standard shown in FIG. 2, * indicates AND logic, and + indicates OR logic.

The verification unit 5 receives the initial design data shown in FIG. 3 via the loader 4, and performs step 11.
Execute circuit tracing at 0 and the data input terminal is 4.
In this case, it is recognized that there is only one clock input terminal, and that the number of register stages from the input terminal to the output terminal is three.

Next, in step 111, a pattern of input values for simulation is generated. This input value pattern is shown in FIG. 15, and for the four data input terminals A, B, S, and T,
This pattern is sequentially incremented up to ``, and is all possible combination patterns of input conditions for the four input terminals.

In addition to this input pattern, the number of register stages is 3.
Clock input CLK patterns for stages are also inserted as shown in FIG. 15 to generate the input value pattern shown in FIG.

Based on this input value, a simulation is performed in step 112 for the logic standard 7 of FIG.
Run it with The pattern shown in FIG. 16 is obtained as the output value 120 obtained by executing this simulation. Note that each pattern number in FIGS. 15 and 16 corresponds to both.

Next, in step 113, the initial design data 1 shown in FIG. 3 is similarly simulated using the input value pattern shown in FIG. 15, and the output value 121 obtained by the simulation is shown in FIG.

In step 116, step 11
The output values 120 and 121 obtained by both simulations 2 and 113 are compared to detect coincidence or mismatch. In this example, since patterns after pattern No. 4 do not match, a circuit search is performed in step 115 to narrow down the mismatched circuits.

[0022] This narrowing down method is first performed in the input direction from output terminals with different output values, and a register closer to the input terminal and with different output values is searched for. In this example, when comparing the patterns in FIG. 16 and FIG. 17, the output C is different, and the registers RD and RC are different.
Each output is different.

Here, the register RC closest to the input terminal
trace until you reach the register on the fan-in side,
The gates are narrowed down to gates GA, GB, and GC between register RC and registers RA, RB, RS, and RT.

In the next step 114, the circuit is modified, and at this time, the register RC of the initial design data 1 in FIG. 3 is expressed by the logical descriptions in FIGS. 13(A) and 13(B). In addition, in FIG. 13, "'" means inversion (NOT).

FIG. 13(C) is a conversion description of the corresponding location (indicated by the dotted line) 21 of the logic standard in FIG. 2, and FIG.
Compare with 3(B). In order to make these two match, it is sufficient to invert the logic immediately before inputting the register RC, so the gate GC is modified from an AND gate to a NAND gate to obtain modified design data as shown in FIG.

Returning again to step 113, a simulation is executed for this modified design data using the input value pattern shown in FIG. Since the resulting output value 121 matches the output value pattern 120 of FIG. 16, the logic verification ends at step 117.

In the flowchart of FIG. 10, each process of circuit tracing 110, input value generation 111, simulation 112, 113 is performed in the verification unit 5 of FIG. 1, and each process of output matching 116 and total output matching 117 is performed by the determination unit 6 in FIG. Also, circuit search 11
5 is performed in the analysis unit 8 of FIG. 1, and the circuit modification 11
Processing No. 4 is performed in the modification section 9 of FIG.

Next, the failure verification processing operation will be explained with reference to the flowchart of FIG. The initial design data in this case is the corrected data for which the previous logic verification has been completed, and is shown in FIG.

This failure verification refers to checking predetermined signal points (for example, input/output terminals and input/output terminals of circuit components (registers, gates, etc.) This is a verification performed to discover 0 faults (faults that are always 0) and 1 faults (faults that are always 1) at points, etc.).

First, the initial design data shown in FIG. 4 is supplied to the verification section 5 via the loader 4. The verification unit 5 performs step 210
By performing a circuit trace, it is recognized that there are four input terminals and one clock input terminal, and that the number of register stages from input to output is three.

Next, in step 211, similarly to step 111 in FIG. 10, an input value pattern shown in FIG. 15 is generated. Simulation 21 based on this input value
2 to create an output value 230 shown in FIG. After that, in the failure assumption step of step 213,
A failure list 231 shown in 4 is created. This fault list is a list of circuit points at which 0 and 1 faults need to be discovered on the actually manufactured circuit.

First, 0 failure verification will be explained. In the fault setting step 214, 0 faults are set for all 0 fault setting points in the fault list for the initial setting data of FIG.
Execute. The simulation result 232 is the pattern shown in FIG. 18, where all values are 0 and there is no change.

In the next step 221, it is determined whether or not there is a terminal whose input is directly an output for the circuit points in the fault list 231 of FIG. 14 where 0 faults have been set. If the input is not directly output, in the next step 222, the output value 2 of the fault simulation is
32 Check whether the total output remains unchanged.

In this example, there is no change. This means that the output C is also 0
This is because 0 is always set as a failure, and the internal circuit does not operate due to a 0 clock failure. This state is detected by the circuit search step 217, and it is determined that no zero faults can be found.

First, in order to be able to discover only the 0 failure of the clock, the circuit is modified in a circuit modification step 216 so that the clock is directly output as is. FIG. 5 shows modified design data when a clock output terminal D is added as a result of this circuit modification.

Thereafter, the simulation 212 is executed again on this modified design data. A partial pattern of the output value 230 at this time (NO1 and 2 only) is shown in Figure 19.
This corresponds to some patterns (NO1, 2) in FIG. 16, and only input/output terminals are added. still,
Figures 21 and 23 show the simulation results described below.
, 25, 27, and 29 also correspond to some of the patterns in FIG. 16.

Then, using the fault setting 214, all 0 faults in the fault list 231 are set again, and the fault simulation 215 is performed again in this setting state. A partial pattern of the output value 232 (NO1 and NO2 only) is shown in FIG. At this time, when pattern No. 2 in FIG. 19, which is the normal simulation result, and pattern No. 2 in FIG. 20, which is the failure simulation result, are compared, the direct output D of the clock is different. This direct output D makes it possible to detect a zero failure in the clock CLK.

In step 221, since there is a direct output D of this clock, the process goes to fault deletion step 218, where input terminal CLK is selected from the fault list in FIG.
Delete 0 failures. This is because the detection of the zero clock failure was made possible by the circuit modification process that directly outputs the terminal D.

In the fault setting 214, 0 faults are set for the faults other than the clock input terminal CLK in the fault list of FIG. 14, and the fault simulation 215 is performed again. Since 0 fault is set at the output terminal C, the total output does not change in this fault simulation result.

Therefore, the process goes from step 222 to circuit search step 217, traces the input of register RD that creates output terminal C, and performs circuit modification step 21.
In Step 6, as in the case of the clock, the output terminal E is modified to output directly from the input of the register RD, as shown in FIG.

After this correction, a simulation 212 is executed to obtain a portion of the output value 230 as shown in FIGS. 21 and 23. Then, set 0 failures again in the same failure list,
Perform failure simulation 215. A part of the output value 232 at this time is shown in FIGS. 22 and 24.

These normal simulation results (Figs. 21 and 23) and failure simulation results (Figs. 22 and 2)
4) (step 222), pattern N
The value of the output E is different in O15, and the reason for this is that the values of 1 and 1 of inputs A and B of pattern No. 13 in FIG. 21 are set to 0 and 0 in FIG. 22 by setting 0 failure. As a result, each 0 failure of input terminals A and B can be discovered.

Furthermore, since the output value C itself is different in pattern No. 16, the 0 failure of the output terminal C can be found here as well. Comparing the output in the same way, Figures 23 and 2
4, each 0 failure of input terminals S and T can be found in pattern No. 47.

In this way, if a 0 fault is found, the corresponding 0 fault is deleted from the fault list in FIG. 14 in a fault deletion step 218, and after all 0 faults have been deleted (step 220), 0 fault verification is performed. is the end. Therefore, in the modified design data shown in FIG. 6, all zero faults in the locations listed in the fault list of FIG. 14 can be found.

Regarding one fault, by setting one fault according to the fault list in FIG. 14 and performing processing according to the flowchart in FIG. 11, all the one faults set in the fault list can be found.

Note that in FIG. 12, the circuit trace 210
, input value generation 211 , simulation 212 ,
Each process of fault assumption 213, fault setting 214, fault simulation 215, and fault deletion 218 is performed in the verification unit 5 of FIG. 1, and output value matching 219 and all fault deletion 220
, direct output 221 , and total output unchanged 222 are performed by the determination unit 6 in FIG. Also, circuit search 21
7 is performed in the analysis unit 8 of FIG. 1, and the circuit correction 216
This process is performed by the modification unit 9 in FIG.

Next, the operation of circuit rule verification will be explained with reference to the flowchart of FIG. The initial design data 1 for this circuit verification is the data shown in FIG. 8 after logic verification and fault verification have been completed.

Here, the standard 7 in FIG. 1 at the time of circuit rule verification is ``input/output buffer required'', ``fanout 4 or less'', and ``register direct output terminal connection not possible''.

First, a terminal check process 310 of the initial design data shown in FIG. 6 is performed to determine in step 311 whether there is an input/output buffer immediately after the input terminal and immediately before the output terminal. In this example, there is no input/output buffer, so step 312
Then, input/output buffers are added to each terminal, and the circuit is modified as shown in FIG. In FIG. 7, elements indicated by squares are an added input/output buffer.

Next, a fan-out check 313 is performed, and it is detected in step 314 that the input terminal CLK exceeds the maximum fan-out "4". Therefore, in step 315, a buffer gate is added here and the circuit is modified as shown in FIG. In FIG. 8, elements indicated by diamond shapes are added buffer gates.

Then, a connection rule check 316 is performed, a connection violation check 317 detects that the output of the register RD is directly connected to the external terminal C, a buffer gate is inserted in a connection correction step 318, and the process shown in FIG. Please correct it accordingly.

[0052] After this, fan-out check 313 is performed again.
, connection rule check 316 is performed, and if there are no violations, the verification ends in step 319.

In the flowchart of FIG. 12, terminal check 310, fan-out check 313,
A connection rule check 316 is performed by the verification unit 5 of FIG. 1, and input/output buffer required 311, maximum fan out over 314, connection violation 317, and two consecutive OKs 319 are performed by the determination unit 6 of FIG. Input/output buffer addition 312, buffer addition 315,
Connection modification 318 is performed in the modification section 9 of FIG.

[0054]

[Effects of the Invention] As described above, according to the present invention, error analysis and correction of design data are automatically performed, eliminating the need for human intervention, allowing for accurate and efficient design in a short period of time. This has the effect of completing the data.

[Brief explanation of drawings]

FIG. 1 is a system block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of logic standards during logic verification.

FIG. 3 is a diagram showing initial design data at the time of logic verification.

FIG. 4 is a diagram showing modified design data after completion of logic verification.

FIG. 5 is a diagram showing design data during failure verification.

FIG. 6 is a diagram showing design data during failure verification.

FIG. 7 is a diagram showing design data during circuit rule verification.

FIG. 8 is a diagram showing design data during circuit rule verification.

FIG. 9 is a diagram showing design data after completion of circuit rule verification.

FIG. 10 is a flowchart showing logic verification processing.

FIG. 11 is a flowchart showing failure verification processing.

FIG. 12 is a flowchart showing circuit rule verification processing.

FIGS. 13A and 13B are diagrams showing examples of error descriptions during logic verification, and FIGS. 13C is a diagram showing an example of the conversion description.

FIG. 14 is a diagram showing a failure list during failure verification.

FIG. 15 is a diagram showing patterns of input values during logic verification and failure verification.

16 is a diagram showing an output value pattern when a simulation is performed using the input value pattern of FIG. 15. FIG.

FIG. 17 is a diagram showing output value patterns of simulation results during logic verification.

FIG. 18 is a pattern diagram showing failure simulation results.

FIG. 19 is a pattern diagram showing a part of normal simulation results during failure verification.

FIG. 20 is a pattern diagram showing a part of failure simulation results.

FIG. 21 is a pattern diagram showing a part of normal simulation results during failure verification.

FIG. 22 is a pattern diagram showing a part of failure simulation results.

FIG. 23 is a pattern diagram showing a part of normal simulation results during failure verification.

FIG. 24 is a pattern diagram showing a part of failure simulation results.

FIG. 25 is a pattern diagram showing a part of normal simulation results during failure verification.

FIG. 26 is a pattern diagram showing a part of failure simulation results.

FIG. 27 is a pattern diagram showing a part of normal simulation results during failure verification.

FIG. 28 is a pattern diagram showing a part of failure simulation results.

FIG. 29 is a pattern diagram showing a part of normal simulation results during failure verification.

FIG. 30 is a pattern diagram showing a part of failure simulation results.

[Explanation of symbols]

1 Initial design data 5 Verification Department 6 Judgment section 7 Standards 8 Analysis department 9 Modification section

Claims (3)

[Claims] 1. Input pattern generating means for generating all possible combinations of input conditions for all input terminals in a logic circuit to be verified; a simulation means for executing a simulation and generating an output pattern at the output terminal of each component of the logic circuit to be verified; a comparison means for comparing this output pattern with a normal output pattern; is detected, circuit searching means searches the circuit from the mismatched output toward the input to detect the starting point of the mismatch in the output, and correction means corrects the circuit at the detected point. Logical design verification system. 2. Input pattern generation means for generating all possible combinations of input conditions for all input terminals in a logic circuit to be fault verified; simulation means for executing a simulation and generating an output pattern at the output terminal of each component of the logic circuit to be fault-verified; and a fault list for generating a list of input/output terminals in which 0 (or 1) faults should be found, respectively. 0 (or 1) for the generation means and all these input/output terminals.
) to perform a fault simulation by setting the logical value of circuit modification means for directly deriving an output terminal from an input terminal; a control means for controlling the modification circuit to perform the simulation again by the simulation means; and controlling the modification circuit to perform the failure simulation again; When the simulation result in the correction circuit and the failure simulation result are compared and the output values match, the circuit correction means and the control means are executed and controlled to determine that the output values do not match and the output value of the failure simulation does not change. and means for deleting from the fault list the input terminal corresponding to the mismatched or changed output terminal, and means for moving the operation to the fault simulation again according to the deleted fault list, and the content of the fault list is A logical design verification system characterized in that each of the above means is executed until all of the means are deleted. 3. A circuit rule storage table in which circuit rules are predetermined and stored; circuit rule verification means for detecting whether a logic circuit subject to circuit rule verification conforms to the circuit rule; and means for making a circuit modification according to the rule when the logic design verification system indicates the above-described rule.