JPH04318483A - Radar receiver - Google Patents

Radar receiver

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Publication number
JPH04318483A
JPH04318483A JP3085413A JP8541391A JPH04318483A JP H04318483 A JPH04318483 A JP H04318483A JP 3085413 A JP3085413 A JP 3085413A JP 8541391 A JP8541391 A JP 8541391A JP H04318483 A JPH04318483 A JP H04318483A
Authority
JP
Japan
Prior art keywords
voltage
amplification
gain
signal
stc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3085413A
Other languages
Japanese (ja)
Other versions
JP2549473B2 (en
Inventor
Yoshihiro Ishii
義弘 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furuno Electric Co Ltd
Original Assignee
Furuno Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furuno Electric Co Ltd filed Critical Furuno Electric Co Ltd
Priority to JP3085413A priority Critical patent/JP2549473B2/en
Publication of JPH04318483A publication Critical patent/JPH04318483A/en
Application granted granted Critical
Publication of JP2549473B2 publication Critical patent/JP2549473B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To enable an optimum sea level reflection suppression state to be retained constantly by multiplying an amplitude control signal by a proportion component of a gain which is set by a gain-setting circuit and then adding it to a radar video signal amplitude of a voltage-controlled amplifier as an input bias. CONSTITUTION:A voltage-controlled amplifier 1 amplifies a radar video signal which is input from an antenna portion 100 according to the control voltage and an STC (sea-level reflection suppression) voltage generation circuit 2 generates an STC voltage which changes according to a time lapse from a transmission trigger generation timing. A gain-setting circuit 3 adds a bias to a control voltage which is given to the amplifier 1 through an adder 4 and controls an entire amplification rate. With this configuration, an STC voltage signal where a proportional component of a gain which is set by the circuit 3 is multiplied is generated, a bias of the set gain is added to the signal by the adder 4 and then is given to the amplifier 1. In this manner, as the set gain is higher (lower), the amplitude becomes higher (lower), thus enabling an optimum sea-level reflection suppression to be performed constantly.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は、パルス状電波を送信
し、物標からの反射波を受信して物標を探知するレーダ
装置に関し、特に海面反射抑制機能を有するレーダ受信
装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radar device that detects a target object by transmitting pulsed radio waves and receiving reflected waves from the target object, and particularly relates to a radar receiving device having a sea surface reflection suppressing function.

【0002】0002

【従来の技術】アンテナの指向方向を変化させるととも
にパルス状電波を発射し、物標からの反射波を受信する
ことによって物標探知を行うレーダ装置(パルスレーダ
)では、近距離で波浪からの反射信号がCRT上に表れ
、中心付近が輝き、自船の近くにある物標が見えなくな
る現象が生じる。これは海面反射によるものであり、海
面反射は近距離であるほど強く、遠距離になるにしたが
って次第に弱くなる。また海況によっても異なり、波が
高い時には中心から6〜7海里近くまで海面反射の影響
がある。
[Prior Art] A radar device (pulse radar) detects a target by changing the pointing direction of the antenna, emitting pulsed radio waves, and receiving reflected waves from the target. The reflected signal appears on the CRT, and the area near the center shines, causing a phenomenon in which targets near the ship become invisible. This is due to sea surface reflection, which is stronger the closer you are, and gradually weakens as you get farther away. It also varies depending on sea conditions, and when waves are high, sea surface reflections can affect up to 6 to 7 nautical miles from the center.

【0003】従来より、海面反射の影響を抑制する装置
としてSTC回路(海面反射抑制回路)が受信部に設け
られている。図6に従来のレーダ装置のブロック図を示
す。
Conventionally, an STC circuit (sea surface reflection suppression circuit) has been provided in a receiving section as a device for suppressing the influence of sea surface reflection. FIG. 6 shows a block diagram of a conventional radar device.

【0004】図6においてレーダ装置は空中線部100
、受信部101、画像処理部102および表示装置10
3から構成される。受信部101において電圧制御増幅
器1は図9に示すように与えられる制御電圧に応じた増
幅率で空中線部100からのレーダ映像信号を増幅する
。STC電圧発生回路2は送信トリガが発生してからの
時間経過に伴って変化するSTC電圧信号を発生する。 このSTC電圧発生回路2は積分回路または微分回路な
どの波形変換回路からなり、図7に示すように、送信ト
リガの入力により、図8に示すようなSTC電圧信号を
発生する。同図においてtは送信トリガ発生タイミング
からの経過時間である。図6においてゲイン設定回路3
は受信部101における全体の増幅率を設定するもので
あり、加算器4によりSTC電圧信号にバイアス電圧を
加えて、電圧制御増幅器1へ制御電圧を与える。従って
、ゲイン設定回路3の出力電圧によって電圧制御増幅器
1の増幅度は図10に示すように変化する。
In FIG. 6, the radar device includes an antenna section 100.
, receiving section 101, image processing section 102, and display device 10
Consists of 3. In the receiving section 101, the voltage control amplifier 1 amplifies the radar video signal from the antenna section 100 with an amplification factor corresponding to the applied control voltage as shown in FIG. The STC voltage generation circuit 2 generates an STC voltage signal that changes with the passage of time after the transmission trigger is generated. This STC voltage generation circuit 2 is comprised of a waveform converting circuit such as an integrating circuit or a differentiating circuit, and as shown in FIG. 7, generates an STC voltage signal as shown in FIG. 8 upon input of a transmission trigger. In the figure, t is the elapsed time from the transmission trigger generation timing. In Figure 6, gain setting circuit 3
is used to set the overall amplification factor in the receiving section 101, and the adder 4 adds a bias voltage to the STC voltage signal to provide a control voltage to the voltage control amplifier 1. Therefore, depending on the output voltage of the gain setting circuit 3, the amplification degree of the voltage control amplifier 1 changes as shown in FIG.

【0005】以上のようにして、送信トリガが発生する
ごとに図11に示すようなSTC電圧波形が電圧制御増
幅器1に与えられる。
As described above, an STC voltage waveform as shown in FIG. 11 is provided to the voltage control amplifier 1 every time a transmission trigger occurs.

【0006】[0006]

【発明が解決しようとする課題】このように従来のレー
ダ装置においては、受信部の電圧制御増幅器に与えるS
TC電圧信号を発生する回路が、積分回路または微分回
路により構成されていたため、STC電圧波形は回路定
数によって決定される。
[Problems to be Solved by the Invention] As described above, in conventional radar equipment, the S applied to the voltage control amplifier of the receiving section is
Since the circuit that generates the TC voltage signal is composed of an integrating circuit or a differentiating circuit, the STC voltage waveform is determined by circuit constants.

【0007】ところが、送信トリガ発生タイミングから
の時間経過にともなって変化すべき増幅器の最適な増幅
度変化特性(以下STC特性と言う。)は、受信装置全
体の増幅度によって異なることが経験的に知られていて
、そのことは理論的にも考察される。すなわち、中心(
アンテナ位置)から比較的近距離範囲で海面反射の影響
が現れる場合には、受信装置全体の増幅度を高めて中距
離から遠距離にかけての物標の消失を防止しようとする
が、それとともに近距離における海面反射を抑制しなけ
ればならない。また逆に、中心から比較的遠方まで海面
反射による影響が現れる場合には、受信装置全体の増幅
度を下げなければならないが、近距離における物標が消
失しないようにしなければならない。
However, it has been empirically determined that the optimum amplification change characteristic (hereinafter referred to as STC characteristic) of the amplifier, which should change over time from the transmission trigger generation timing, differs depending on the amplification degree of the entire receiving device. This is known and can be considered theoretically. That is, the center (
When the influence of sea surface reflection appears in a relatively short range from the antenna position, the amplification of the entire receiving device is increased to prevent the target from disappearing from medium to long distances. Sea surface reflections at distance must be suppressed. On the other hand, if the influence of sea surface reflection appears at a relatively far distance from the center, the amplification of the entire receiving device must be lowered, but it is necessary to ensure that targets at short distances do not disappear.

【0008】従来のレーダ受信装置では、図6に示した
ゲイン設定回路3を用いて図10示すようにSTC電圧
カーブを全体にシフトさせることによって、海面反射の
抑制を適正化するようにしている。そのため、中距離か
ら遠距離にかけての物標の消失を防止するために全体の
増幅度を高めれば、近距離における増幅度が高くなりす
ぎ、海面反射の影響が現れる。また、比較的遠方まで現
れる海面反射の影響を防止するために全体の増幅度を低
下させれば近距離における増幅度が低下しすぎることに
なり、近距離における物標消失の問題が生じる。
[0008] In the conventional radar receiving device, suppression of sea surface reflection is optimized by shifting the entire STC voltage curve as shown in FIG. 10 using the gain setting circuit 3 shown in FIG. . Therefore, if the overall amplification degree is increased in order to prevent the disappearance of targets from medium to long distances, the amplification degree at short distances becomes too high, and the influence of sea surface reflection appears. Furthermore, if the overall amplification degree is lowered in order to prevent the influence of sea surface reflections that appear at relatively far distances, the amplification degree at short distances will be reduced too much, resulting in the problem of target objects disappearing at short distances.

【0009】この発明の目的は、受信装置全体の増幅度
を設定するゲイン設定に応じて増幅度制御信号を適正化
(これによりSTC特性を適正化)して、観測時の条件
や状況に最も適した海面反射抑制状態で観測できるよう
にしたレーダ受信装置を提供することにある。
An object of the present invention is to optimize the amplification control signal (thereby optimizing the STC characteristics) in accordance with the gain setting that sets the amplification degree of the entire receiving device, so as to optimize the amplification control signal according to the conditions and situations at the time of observation. It is an object of the present invention to provide a radar receiving device that enables observation in a state where reflections from the sea surface are appropriately suppressed.

【0010】0010

【課題を解決するための手段】この発明のレーダ受信装
置は、レーダ映像信号を増幅度制御信号に応じた増幅率
で増幅する電圧制御増幅器と、送信トリガ発生タイミン
グからの時間経過にともなって変化する増幅度制御信号
を発生する増幅度制御信号発生回路と、前記電圧制御増
幅器に与える信号にバイアスを加えて受信装置全体の増
幅度を設定するゲイン設定回路と、設定されたゲインの
比例成分を前記増幅度制御信号に乗じる増幅度修正手段
とを備えてなる。
[Means for Solving the Problems] The radar receiving device of the present invention includes a voltage control amplifier that amplifies a radar video signal with an amplification factor that corresponds to an amplification control signal, and a voltage control amplifier that amplifies a radar video signal with an amplification factor that corresponds to an amplification factor control signal, and a voltage control amplifier that amplifies a radar video signal with an amplification factor that corresponds to an amplification factor control signal, and a voltage control amplifier that amplifies a radar video signal with an amplification factor that corresponds to an amplification factor control signal. an amplification control signal generation circuit that generates an amplification control signal to control the voltage control amplifier; a gain setting circuit that adds a bias to the signal to be applied to the voltage control amplifier to set the amplification of the entire receiving device; and amplification correction means for multiplying the amplification control signal.

【0011】[0011]

【作用】この発明のレーダ受信装置では、増幅度制御信
号発生回路は、送信トリガ発生タイミングからの時間経
過にともなって変化する増幅度制御信号を発生し、ゲイ
ン設定回路は電圧制御増幅器に与える信号にバイアスを
加えて受信装置全体の増幅度を設定するが、増幅度修正
手段が、設定されたゲインの比例成分を増幅度制御信号
に乗じる。電圧制御増幅器は与えられた増幅度制御信号
に応じてレーダ映像信号を増幅するため、ゲイン設定回
路による設定ゲインが高いほど送信トリガ発生タイミン
グからの時間経過にともなう増幅度制御信号の変化(傾
き)が急になり、逆に設定ゲインが低いほど電圧制御増
幅器に与えられる増幅度制御信号の変化(傾き)は緩く
なる。したがって設定ゲインにより適する増幅度変化特
性(STC特性)とすることができ、近距離から遠距離
まで海面反射による影響を除去し、且つ物標消失のない
状態で観測を行うことができるようになる。
[Operation] In the radar receiver of the present invention, the amplification control signal generation circuit generates an amplification control signal that changes with time from the transmission trigger generation timing, and the gain setting circuit generates a signal that is applied to the voltage control amplifier. The amplification degree of the entire receiving apparatus is set by adding a bias to the gain, and the amplification degree modifying means multiplies the amplification degree control signal by a proportional component of the set gain. Since the voltage control amplifier amplifies the radar video signal according to the given amplification control signal, the higher the gain set by the gain setting circuit, the more the amplification control signal changes (slope) with the passage of time from the transmission trigger generation timing. becomes steeper, and conversely, the lower the set gain, the slower the change (slope) of the amplification control signal given to the voltage control amplifier. Therefore, the amplification change characteristic (STC characteristic) can be made more suitable for the set gain, and the influence of sea surface reflection can be removed from short distances to long distances, and observation can be performed without target disappearance. .

【0012】0012

【実施例】まず、この発明の実施例であるレーダ装置の
ブロック図を図1に示す。図1においてレーダ装置は空
中線部100、受信部101、画像処理部102および
表示装置103から構成される。受信部101において
電圧制御増幅器1は空中線部100から送られてくるレ
ーダ映像の中間周波信号を与えられた制御電圧に応じた
増幅率で増幅する。STC電圧発生回路2は送信トリガ
発生タイミングからの時間経過にともなって変化するS
TC電圧を発生する。ゲイン設定回路3は加算器4を介
して電圧制御増幅器1に与えるべき制御電圧にバイアス
を加えて受信部全体の増幅率を制御する。STC特性選
択スイッチ6はSTC電圧発生回路2が発生すべきST
C電圧信号を選択する。検波回路5は適正な増幅率で増
幅されたレーダ映像信号の中間周波信号を検波して画像
処理部102へ出力する。画像処理部102においてA
−Dコンバータ7はレーダ映像信号をディジタルデータ
に変換する。画像メモリ8はレーダ映像のディジタルデ
ータを順次記憶する。画像処理回路9は画像メモリ8に
すでに書き込まれているデータおよび新たな画像データ
との関係によって所定の画像処理を行い、その結果を画
像メモリ8へ書き込む。表示装置103は画像メモリ8
を所定タイミングで読み出すとともに映像信号を作成し
CRTにレーダ映像を表示する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a block diagram of a radar apparatus according to an embodiment of the present invention is shown in FIG. In FIG. 1, the radar device includes an antenna section 100, a receiving section 101, an image processing section 102, and a display device 103. In the receiving section 101, the voltage control amplifier 1 amplifies the intermediate frequency signal of the radar image sent from the antenna section 100 with an amplification factor corresponding to the applied control voltage. The STC voltage generation circuit 2 has an STC voltage that changes with the passage of time from the transmission trigger generation timing.
Generates TC voltage. The gain setting circuit 3 adds a bias to the control voltage to be applied to the voltage control amplifier 1 via the adder 4 to control the amplification factor of the entire receiving section. The STC characteristic selection switch 6 selects the ST to be generated by the STC voltage generation circuit 2.
Select C voltage signal. The detection circuit 5 detects the intermediate frequency signal of the radar video signal amplified with an appropriate amplification factor and outputs it to the image processing section 102. In the image processing unit 102, A
-D converter 7 converts the radar video signal into digital data. The image memory 8 sequentially stores digital data of radar images. The image processing circuit 9 performs predetermined image processing based on the relationship between the data already written in the image memory 8 and the new image data, and writes the results to the image memory 8. The display device 103 is the image memory 8
is read out at a predetermined timing, a video signal is created, and the radar video is displayed on a CRT.

【0013】次に、図1に示したSTC電圧発生回路2
の具体的な構成をブロック図として図2に示す。図2に
おいて、クロック発生回路20は一定周波数のクロック
信号を発生する。カウンタ22はクロック信号をカウン
トして、所定値に達するごとに分周回路21の分周比を
切り換える。分周回路21はカウンタ22の状態により
定まる分周比でクロック信号を分周する。アドレスカウ
ンタ23は分周回路21の出力信号をカウントするとと
もに、そのカウント値を増幅度データメモリ24の下位
アドレス(A0〜A5)として与える。アドレスセレク
タ25はSTC特性選択スイッチ6の選択に応じて増幅
度データメモリ24の上位アドレス(A6〜A15)を
与える。増幅度データメモリ24は指定されたアドレス
の内容を出力する。すなわちこの例では、複数のSTC
特性データが増幅度データメモリ24に予め書き込まれ
ていて、STC特性選択スイッチ6の操作で目的のST
C特性を選択することができる。D−Aコンバータ26
は増幅度データメモリ24の出力データをアナログ信号
に変換し、ローパスフィルタ27はサンプリングノイズ
を除去する。乗算器28はその信号に対しゲイン設定回
路による設定ゲインに比例する電圧を乗じてSTC電圧
信号として出力する。
Next, the STC voltage generation circuit 2 shown in FIG.
FIG. 2 shows a specific configuration of the system as a block diagram. In FIG. 2, a clock generation circuit 20 generates a clock signal of a constant frequency. The counter 22 counts the clock signal and switches the frequency division ratio of the frequency dividing circuit 21 every time the clock signal reaches a predetermined value. The frequency dividing circuit 21 divides the clock signal at a frequency division ratio determined by the state of the counter 22. The address counter 23 counts the output signal of the frequency dividing circuit 21 and provides the count value as a lower address (A0 to A5) of the amplification degree data memory 24. The address selector 25 provides the upper address (A6 to A15) of the amplification data memory 24 in accordance with the selection of the STC characteristic selection switch 6. The amplification data memory 24 outputs the contents of the designated address. That is, in this example, multiple STCs
Characteristic data is written in the amplification degree data memory 24 in advance, and the target ST can be selected by operating the STC characteristic selection switch 6.
C characteristics can be selected. D-A converter 26
converts the output data of the amplification data memory 24 into an analog signal, and the low-pass filter 27 removes sampling noise. The multiplier 28 multiplies the signal by a voltage proportional to the gain set by the gain setting circuit and outputs the result as an STC voltage signal.

【0014】図2に示した増幅度データメモリ24のデ
ータ構成例を図3に示す。この増幅度データメモリの上
位アドレスA6〜A15がデータの種類(STC特性)
を選択し、下位アドレスA0〜A5が各データの読出位
置(送信トリガ発生タイミングからの時間経過にともな
って定まる位置)を決定する。すなわちデータ000、
データ001、データ002・・・のSTC特性データ
の内一つの特性データが図2に示したアドレスセレクタ
25により選択され、アドレスカウンタ23によりその
STC特性データがスタートアドレスから順次読み出さ
れることになる。
An example of the data structure of the amplification data memory 24 shown in FIG. 2 is shown in FIG. The upper addresses A6 to A15 of this amplification degree data memory are the data types (STC characteristics)
is selected, and the lower addresses A0 to A5 determine the read position of each data (position determined as time elapses from the transmission trigger generation timing). That is, data 000,
One of the STC characteristic data of data 001, data 002, . . . is selected by the address selector 25 shown in FIG. 2, and the address counter 23 sequentially reads out the STC characteristic data from the start address.

【0015】図2に示した各部の波形を図4に示す。図
2において分周回路21はカウンタ22の作用により分
周比を段階的に順次大きくしていくため、アドレスカウ
ンタ23は送信トリガの発生直後は細かくカウントアッ
プし、時間経過にともない段階的に次第にゆっくりカウ
ントアップすることになる。このことにより近距離にお
けるSTC電圧カーブの分解能を高め且つ増幅度データ
メモリ24のメモリ容量を節約している。また、クロッ
ク発生回路20、分周回路21、カウンタ22およびア
ドレスカウンタ23は送信トリガによりリセットされ、
送信トリガの発生ごとにアドレスカウンタ23は同一ス
タートアドレスから順次増幅度データメモリ24をアド
レス選択することになる。
FIG. 4 shows waveforms of each part shown in FIG. 2. In FIG. 2, the frequency divider circuit 21 gradually increases the frequency division ratio by the action of the counter 22, so the address counter 23 counts up minutely immediately after the transmission trigger occurs, and gradually increases the frequency division ratio as time passes. It will count up slowly. This increases the resolution of the STC voltage curve at short distances and saves the memory capacity of the amplification data memory 24. Further, the clock generation circuit 20, frequency division circuit 21, counter 22, and address counter 23 are reset by the transmission trigger,
Each time a transmission trigger occurs, the address counter 23 sequentially selects addresses in the amplification degree data memory 24 starting from the same start address.

【0016】このようにして、送信トリガに同期して、
設定ゲインの比例成分が乗じられたSTC電圧信号が発
生され、そのSTC電圧信号に対して加算器4(図1参
照)により設定ゲイン分のバイアスが加えられ、電圧制
御増幅器1に与えられる。
In this way, in synchronization with the transmission trigger,
An STC voltage signal multiplied by a proportional component of the set gain is generated, a bias corresponding to the set gain is added to the STC voltage signal by an adder 4 (see FIG. 1), and the added bias is applied to the voltage control amplifier 1.

【0017】図1および図2に示した受信部の増幅度変
化特性の例を図5に示す。このようにゲイン設定回路3
による設定ゲインが高いほど全体の増幅度が高くなり、
且つトリガ発生タイミングからの時間経過に伴う増幅度
の上昇変化の傾きは急となる。逆に設定ゲインが低いほ
ど全体の増幅度が低くなり、且つ増幅度の上昇変化の傾
きが緩くなる。
FIG. 5 shows an example of the amplification change characteristics of the receiving section shown in FIGS. 1 and 2. In this way, gain setting circuit 3
The higher the gain setting, the higher the overall amplification.
Moreover, the slope of the increase in the amplification degree as time passes from the trigger generation timing becomes steep. Conversely, the lower the set gain, the lower the overall amplification degree, and the slower the slope of the increase in the amplification degree.

【0018】[0018]

【発明の効果】この発明によれば、受信装置全体の設定
ゲインが高い時には、送信トリガ発生タイミングからの
時間経過にともなう、電圧制御増幅器の増幅率変化の傾
きが急となるため、比較的近距離における海面反射が効
果的に抑制され、中距離から遠距離にかけての物標消失
が防止される。また、受信装置全体の設定ゲインが低い
時には、電圧制御増幅器の増幅率変化の傾きは緩くなる
ため、比較的遠方まで海面反射による影響を除去し、且
つ近距離における物標消失を防止することができる。し
たがって観測状態や条件に応じて、常に最適な海面反射
抑制を行って確実な観測を行うことができる。
According to the present invention, when the set gain of the entire receiving device is high, the slope of the amplification factor change of the voltage controlled amplifier becomes steep as time elapses from the transmission trigger generation timing. Sea surface reflections at long distances are effectively suppressed, preventing target objects from disappearing from medium to long distances. In addition, when the overall gain setting of the receiving device is low, the slope of the change in the amplification factor of the voltage control amplifier becomes gentler, so it is possible to eliminate the influence of sea surface reflections over relatively long distances and prevent target objects from disappearing at short distances. can. Therefore, depending on the observation state and conditions, optimal sea surface reflection suppression can be performed at all times to ensure reliable observation.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】実施例に係るレーダ装置のブロック図である。FIG. 1 is a block diagram of a radar device according to an embodiment.

【図2】実施例のレーダ装置におけるSTC電圧発生回
路のブロック図である。
FIG. 2 is a block diagram of an STC voltage generation circuit in the radar device of the embodiment.

【図3】増幅度データメモリの構成図である。FIG. 3 is a configuration diagram of an amplification degree data memory.

【図4】図2各部の波形図である。FIG. 4 is a waveform diagram of each part in FIG. 2;

【図5】設定ゲインによる増幅度変化特性の違いを示す
図である。
FIG. 5 is a diagram showing the difference in amplification change characteristics depending on the set gain.

【図6】従来のレーダ装置のブロック図である。FIG. 6 is a block diagram of a conventional radar device.

【図7】従来のSTC電圧発生回路の回路図である。FIG. 7 is a circuit diagram of a conventional STC voltage generation circuit.

【図8】従来のSTC電圧発生回路の特性図である。FIG. 8 is a characteristic diagram of a conventional STC voltage generation circuit.

【図9】電圧制御増幅器の特性図である。FIG. 9 is a characteristic diagram of a voltage controlled amplifier.

【図10】ゲインの設定により変化する従来の受信部の
増幅率変化特性図である。
FIG. 10 is a diagram showing the amplification factor change characteristic of a conventional receiving section that changes depending on the gain setting.

【図11】図6各部の波形図である。FIG. 11 is a waveform diagram of each part in FIG. 6;

【符号の説明】[Explanation of symbols]

100−空中線部 101−受信部 102−画像処理部 100-Antenna section 101-Receiving section 102-Image processing unit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】レーダ映像信号を増幅度制御信号に応じた
増幅率で増幅する電圧制御増幅器と、送信トリガ発生タ
イミングからの時間経過にともなって変化する増幅度制
御信号を発生する増幅度制御信号発生回路と、前記電圧
制御増幅器に与える信号にバイアスを加えて受信装置全
体の増幅度を設定するゲイン設定回路と、設定されたゲ
インの比例成分を前記増幅度制御信号に乗じる増幅度修
正手段とを備えてなるレーダ受信装置。
1. A voltage control amplifier that amplifies a radar video signal with an amplification factor according to an amplification control signal, and an amplification control signal that generates an amplification control signal that changes with time from the transmission trigger generation timing. a generating circuit; a gain setting circuit that applies a bias to the signal applied to the voltage control amplifier to set the amplification degree of the entire receiving device; and an amplification degree correction means that multiplies the amplification degree control signal by a proportional component of the set gain. A radar receiving device equipped with
JP3085413A 1991-04-17 1991-04-17 Radar receiver Expired - Fee Related JP2549473B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3085413A JP2549473B2 (en) 1991-04-17 1991-04-17 Radar receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3085413A JP2549473B2 (en) 1991-04-17 1991-04-17 Radar receiver

Publications (2)

Publication Number Publication Date
JPH04318483A true JPH04318483A (en) 1992-11-10
JP2549473B2 JP2549473B2 (en) 1996-10-30

Family

ID=13858121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3085413A Expired - Fee Related JP2549473B2 (en) 1991-04-17 1991-04-17 Radar receiver

Country Status (1)

Country Link
JP (1) JP2549473B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008089469A (en) * 2006-10-03 2008-04-17 Toshiba Corp Radar device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4927181A (en) * 1972-07-05 1974-03-11
JPS5023955A (en) * 1973-07-03 1975-03-14
JPS58780A (en) * 1981-06-24 1983-01-05 Mitsubishi Electric Corp Pulse radar receiver
JPS60190882A (en) * 1984-03-11 1985-09-28 Mitsubishi Electric Corp Gain control apparatus
JPS60195470A (en) * 1984-03-16 1985-10-03 Anritsu Corp Stc circuit of radar receiver
JPS61202174A (en) * 1985-03-06 1986-09-06 Nec Corp Receiving sensitivity control circuit for radar
JPS63184082A (en) * 1986-09-20 1988-07-29 Tokyo Keiki Co Ltd Hue controller for color radar

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4927181A (en) * 1972-07-05 1974-03-11
JPS5023955A (en) * 1973-07-03 1975-03-14
JPS58780A (en) * 1981-06-24 1983-01-05 Mitsubishi Electric Corp Pulse radar receiver
JPS60190882A (en) * 1984-03-11 1985-09-28 Mitsubishi Electric Corp Gain control apparatus
JPS60195470A (en) * 1984-03-16 1985-10-03 Anritsu Corp Stc circuit of radar receiver
JPS61202174A (en) * 1985-03-06 1986-09-06 Nec Corp Receiving sensitivity control circuit for radar
JPS63184082A (en) * 1986-09-20 1988-07-29 Tokyo Keiki Co Ltd Hue controller for color radar

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008089469A (en) * 2006-10-03 2008-04-17 Toshiba Corp Radar device

Also Published As

Publication number Publication date
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