JPS6218085B2 - - Google Patents

Info

Publication number
JPS6218085B2
JPS6218085B2 JP55076427A JP7642780A JPS6218085B2 JP S6218085 B2 JPS6218085 B2 JP S6218085B2 JP 55076427 A JP55076427 A JP 55076427A JP 7642780 A JP7642780 A JP 7642780A JP S6218085 B2 JPS6218085 B2 JP S6218085B2
Authority
JP
Japan
Prior art keywords
circuit
level
control signal
signal
agc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55076427A
Other languages
Japanese (ja)
Other versions
JPS573409A (en
Inventor
Takashi Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP7642780A priority Critical patent/JPS573409A/en
Publication of JPS573409A publication Critical patent/JPS573409A/en
Publication of JPS6218085B2 publication Critical patent/JPS6218085B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3005Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
  • Control Of Amplification And Gain Control (AREA)

Description

【発明の詳細な説明】 本発明は、例えば音波を水中に発射しその反響
音を受波して水中物体の挿索を行うアクテイブソ
ーナー装置において、レベル変動の大きい受波信
号を略一定レベルに抑え込みCRT(Cathode
Ray Tube)への表示等を容易にするために有用
なAGC(Automatic Gain Contol)回路に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention is an active sonar device that emit sound waves underwater and receive the echoes to locate underwater objects, for example. Cathode
This invention relates to AGC (Automatic Gain Control) circuits that are useful for facilitating display on Ray Tubes.

アクテイブソーナー装置は正弦波をパルス変調
した音波を発射し、水中物体からの反響音の時間
遅れを計測して水中物体までの距離を求め、又、
多数の方位の異なる受波指向性ビームを準備し水
中物体からの反響音についてどの受波指向性ビー
ムの出力レベルが最も大きいか比較計測し水中物
体の位置を明らかにするものである。
Active sonar devices emit sound waves that are pulse-modulated sine waves, measure the time delay of echoes from underwater objects, and determine the distance to underwater objects.
This method involves preparing a number of receiving directional beams in different directions and comparing and measuring which receiving directional beam has the highest output level regarding the echoes from underwater objects, thereby clarifying the position of the underwater object.

このアクテイブソーナー装置において受信され
る信号は水中物体からの反響音の他、水中微少物
体等により散乱され戻つて来る残響、水中自然界
に存在する水中自然雑音等がありこれらのレベル
は時々刻々変化し、その変化の程度は通常60〜
150dBにも達する。大幅に変動する残響及び雑音
の中から水中物体からの反響音を検出するために
は、この残響及び雑音を略一定のレベルに抑え込
む必要があり、アクテイブソーナー装置の受信系
には通常AGC回路が準備されている。すなわち
アクテイブソーナー装置のAGC回路はそのレベ
ル変化が時間的に比較的ゆるやかな残響、水中雑
音等の妨害雑音のレベルを均一化し、継続時間が
短かい水中物体からの反響音の品質を損なわずに
出力しその検出を容易にするものである。
The signals received by this active sonar device include echoes from underwater objects, reverberations scattered by minute underwater objects, etc., underwater natural noise that exists in the underwater natural world, and the levels of these signals change from moment to moment. , the degree of change is usually 60 ~
It reaches as high as 150dB. In order to detect reverberant sounds from underwater objects among widely fluctuating reverberations and noise, it is necessary to suppress this reverberation and noise to a nearly constant level, and the receiving system of active sonar devices usually includes an AGC circuit. It is prepared. In other words, the AGC circuit of an active sonar device equalizes the level of interfering noise such as reverberation and underwater noise whose level changes are relatively gradual over time, without impairing the quality of echoes from underwater objects that have a short duration. output and facilitates its detection.

従来このソーナーAGC回路は第1図に示す様
に利得可変増幅回路1及び制御信号発生回路2か
ら構成される。なお3及び4はそれぞれAGC回
路入力端子、及び出力端子、5は制御信号発生回
路の入力、6は制御信号発生回路の出力の利得制
御信号である。利得可変増幅回路はダイオードの
非直線効果使つたもの、乗算回路を利用するもの
等があり、制御信号発生回路は利得可変増幅回路
の方式に対応し種々のものがある。一例としてダ
イオードを使つた方式について第2図により、そ
の動作原理を説明する。第2図において、7は入
力抵抗、8はダイオード、9は増幅回路、10及
び11は直流阻止用のコンデンサ、12は利得制
御信号用の入力抵抗であり、これにより利得可変
増幅回路を構成し、更に13は検波回路、14は
積分回路、15は増幅回路であり、これらにより
制御信号発生回路を構成する。
Conventionally, this sonar AGC circuit is comprised of a variable gain amplifier circuit 1 and a control signal generation circuit 2, as shown in FIG. Note that 3 and 4 are the AGC circuit input terminal and output terminal, respectively, 5 is the input of the control signal generation circuit, and 6 is the gain control signal of the output of the control signal generation circuit. Variable gain amplifier circuits include those that use the nonlinear effect of diodes and those that utilize multiplier circuits, and there are various types of control signal generation circuits that correspond to the types of variable gain amplifier circuits. As an example, the principle of operation of a method using a diode will be explained with reference to FIG. In Figure 2, 7 is an input resistor, 8 is a diode, 9 is an amplifier circuit, 10 and 11 are capacitors for direct current blocking, and 12 is an input resistor for gain control signals, which constitutes a variable gain amplifier circuit. , 13 is a detection circuit, 14 is an integration circuit, and 15 is an amplifier circuit, which constitute a control signal generation circuit.

レベル時間的に複雑に変化する信号が入力端子
3に加つた場合、その信号は利得可変増幅回路1
の入力部を通り増幅回路により増幅され制御信号
発生回路2に加えられる。制御信号発生回路では
検波された後積分回路で時間的に変化の激しい成
分は除去され変化のゆるやかな成分だけが出力さ
れ増幅されて制御信号となる。制御信号の電圧が
増大すると、ダイオード8はその抵抗が低下する
ため増幅回路9に入力される信号のレベルが低下
し逆に制御電圧が減少すると増幅回路9に入力さ
れる信号のレベルが増大する。
When a signal whose level changes complexly over time is applied to the input terminal 3, the signal is transferred to the variable gain amplifier circuit 1.
The signal is amplified by the amplifier circuit and applied to the control signal generation circuit 2. In the control signal generation circuit, after the wave is detected, components that change rapidly over time are removed by an integrating circuit, and only components that change slowly are outputted and amplified to become a control signal. When the voltage of the control signal increases, the resistance of the diode 8 decreases, so the level of the signal input to the amplifier circuit 9 decreases, and conversely, when the control voltage decreases, the level of the signal input to the amplifier circuit 9 increases. .

以上の動作により、入力端子3に加えられた時
間的に複雑に変化する信号は、時間的にゆるやか
に変化する成分は除去され均一化されて出力され
る。
As a result of the above-described operation, the signal applied to the input terminal 3 that changes complexly over time is outputted after its components that change slowly over time are removed and the signal is made uniform.

しかしながら、この様に動作する従来のソーナ
ー用AGC回路では通常次のような問題が発生す
る。一般にソーナーのAGC回路の入力信号は第
3図aに示す特性を持つ。この図に於いてZで示
す部分が残響であり時間とともにレベルが減少す
る。Hで示す部分は潜水艦からの反響音であり残
響よりもAだけレベルが高いものとする。第2図
に示すソーナー用AGC回路に第3図aに示す信
号が加つた場合、その出力は第3図bに示すもの
となる。第3図aに示すとおり時間的に減少する
残響の部分のレベルは均一化されるがHで示す反
響音のエンベロープが歪を受けている。この第3
図bのHで示す反響音のエンベロープの歪が従来
のAGC回路の欠陥である。すなわち、歪が激し
い場合立上り部分のAのレベルは確保されるがそ
のエンベロープは急峻な三角形となり、この信号
を検波し積分してCRTの輝度信号を発生する一
般のソーナーでは輝度信号のレベルを大幅に低下
することになる。極端な場合にはAGC回路の入
力では第3図aのHで示す様な反響音がある場合
でも、AGC回路の特性によつては、CRTの輝度
信号では反響信号が消えてしまう恐れもある。
However, conventional AGC circuits for sonar that operate in this manner usually have the following problems. In general, the input signal to the AGC circuit of a sonar has the characteristics shown in Figure 3a. In this figure, the part indicated by Z is the reverberation, and the level decreases over time. The part indicated by H is the reverberation sound from the submarine, and the level is higher than the reverberation by A. When the signal shown in FIG. 3a is applied to the sonar AGC circuit shown in FIG. 2, the output will be as shown in FIG. 3b. As shown in FIG. 3a, the level of the reverberation portion that decreases over time is equalized, but the envelope of the reverberant sound indicated by H is distorted. This third
Distortion of the envelope of the reverberant sound, indicated by H in Figure b, is a defect in the conventional AGC circuit. In other words, when the distortion is severe, the level of A in the rising part is maintained, but its envelope becomes a steep triangle, and in a general sonar that detects and integrates this signal to generate a CRT brightness signal, the level of the brightness signal is significantly increased. This will result in a decline in In extreme cases, even if there is a reverberant sound as shown by H in Figure 3a at the input of the AGC circuit, depending on the characteristics of the AGC circuit, the reverberant signal may disappear in the CRT luminance signal. .

以上示した従来のAGC回路の反響音の歪は主
に第2図の積分回路内の時定数により、影響され
る。もし時定数が極端に短い場合は積分回路の入
力の短形状の反響信号は積分回路で平滑化される
事が少い状態で出力され制御信号に現われる。こ
の様な状態では前述の通りダイオード8によりそ
の信号のレベルは減少されAGC回路の出力部で
の反響信号は急峻な三角形となつてしまう。一方
積分回路の時定数を極端に長くした場合反響音の
エンベロープの歪は少くなるが時間的にゆるやか
に変化する第3図aのZで示す残響の部分を均一
化出来ない事になる。従つて従来のAGC回路で
は、反響音のエンベロープの歪と残響のレベルの
均一化が妥協できる様に、積分回路の時定数を求
める必要があり試行錯誤的な実験をくり返しこの
積分数を求めるというのが通例であつた。
The distortion of the reverberant sound in the conventional AGC circuit shown above is mainly affected by the time constant in the integrating circuit shown in FIG. If the time constant is extremely short, the rectangular echo signal input to the integrating circuit will be output without being smoothed by the integrating circuit and will appear in the control signal. In such a state, the level of the signal is reduced by the diode 8 as described above, and the echo signal at the output section of the AGC circuit becomes a steep triangle. On the other hand, if the time constant of the integrating circuit is made extremely long, the distortion of the envelope of the reverberating sound will be reduced, but the reverberation part shown by Z in Fig. 3a, which changes slowly over time, cannot be made uniform. Therefore, in conventional AGC circuits, it is necessary to find the time constant of the integrating circuit so that the distortion of the echo envelope and the level of reverberation can be compromised, and this integral number is found by repeating trial and error experiments. It was customary.

本発明は制御信号発生回路において積分する前
に、設定されたレベル以上の信号を制限して、制
限範囲内の信号のみを積分回路に送り出すことに
より上記の欠点を解決し、歪が少なく応答が良
く、又回路設計が容易に実施出来るソーナー
AGC回路を提供するものである。
The present invention solves the above drawbacks by limiting signals above a set level and sending only signals within the limit range to the integrating circuit before integrating in the control signal generation circuit, resulting in low distortion and response. A sonar with good performance and easy circuit design.
It provides an AGC circuit.

次に本発明の実施例について図面を参照して説
明する。本発明によるソーナーAGC回路を示す
第4図を参照すると利得可変増幅回路1の出力は
検波回路13、レベル制限回路16、積分回路1
4及び増幅回路15から構成される制御信号発生
回路2に入力される。この入力された信号は検波
された後、設定されたレベル以上の信号を制限す
るレベル制限回路16に加えられる。残響、水中
雑音等の背景雑音よりもレベル高い水中物体から
の反響音はこのレベル制限回路により制限され
る。もしも反響音が設定されたレベルを越える場
合は反響音は設定レベルに制限され設定レベル以
下の場合はそのまゝ積分回路14に出力される。
Next, embodiments of the present invention will be described with reference to the drawings. Referring to FIG. 4 showing the sonar AGC circuit according to the present invention, the output of the variable gain amplifier circuit 1 is a detection circuit 13, a level limiting circuit 16, and an integrating circuit 1.
4 and an amplifier circuit 15. After this input signal is detected, it is applied to a level limiting circuit 16 that limits signals exceeding a set level. Reverberation sounds from underwater objects that are higher in level than background noise such as reverberation and underwater noise are limited by this level limiting circuit. If the reflected sound exceeds the set level, the reflected sound is limited to the set level, and if it is below the set level, it is output as is to the integrating circuit 14.

この様に、反響音信号は設定されたレベル以下
に制限され積分回路に入力されるため積分回路の
出力の反響音信号成分はレベル制限回路で設定さ
れたレベルに対応するレベルを越える事はない。
従つて積分回路の出力を増幅回路15により増幅
して作り出される利得制御信号6の中の反響音成
分は制限されたものとなりソーナーAGC回路の
反響音の出力はレベル制限回路で設定されたレベ
ルに対応する歪が最大のもので常に歪はこの一定
の値以下となる。
In this way, the reverberant sound signal is limited to below the set level and input to the integrating circuit, so the reverberant sound signal component output from the integrating circuit will never exceed the level corresponding to the level set by the level limiting circuit. .
Therefore, the reverberant sound component in the gain control signal 6 generated by amplifying the output of the integrating circuit by the amplifier circuit 15 is limited, and the reverberant sound output of the sonar AGC circuit is at the level set by the level limiter circuit. The corresponding distortion is the maximum one, and the distortion is always below this certain value.

以上により制御信号発生回路2の中の積分回路
14の時定数は、レベル制限回路の設定されたレ
ベルに対応する反響音に対してのみ歪みが十分小
さく出来る様に設定すれば良くそれ以上レベルの
高い反響音に対しては一切配慮する必要がなくな
る。
As described above, the time constant of the integrating circuit 14 in the control signal generating circuit 2 only needs to be set so that the distortion can be made sufficiently small only for the echo sound corresponding to the level set in the level limiting circuit. There is no need to take any consideration to high reverberant sounds.

本発明は以上説明したように制御信号発生回路
の中にレベル制限回路を持つことにより、反響音
信号の歪を定められたもの以下に制限出来、又積
分回路の時定数が容易に計算出来それ以上に時定
数を延ばす必要がないため応答特性の優れたソー
ナーAGC回路が得られる。
As explained above, by including the level limiting circuit in the control signal generating circuit, the present invention can limit the distortion of the echo sound signal to a predetermined value or less, and the time constant of the integrating circuit can be easily calculated. Since there is no need to extend the time constant any further, a sonar AGC circuit with excellent response characteristics can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はソーナーAGC回路の基本原理ブロツ
ク図、第2図は従来使用されていたソーナー
AGC回路のブロツク図、第3図a及びbは第2
図の入力端子3及び出力端子4の信号波形、第4
図は本発明の実施例を示すブロツク図である。 1…利得可変増幅回路、2…制御信号発生回
路、3…入力端子、4…出力端子、5…制御信号
発生回路入力、6…利得制御信号、7…入力抵
抗、8…ダイオード、9…増幅回路、10…直流
阻止コンデンサ、11…直流阻止コンデンサ、1
2…利得制御信号入力抵抗、13…検波回路、1
4…積分回路、15…増幅回路、16…レベル制
限回路。
Figure 1 is a basic principle block diagram of a sonar AGC circuit, Figure 2 is a conventional sonar AGC circuit.
Block diagram of the AGC circuit, Figure 3 a and b are the second
Signal waveforms of input terminal 3 and output terminal 4 in the figure, 4th
The figure is a block diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Variable gain amplifier circuit, 2...Control signal generation circuit, 3...Input terminal, 4...Output terminal, 5...Control signal generation circuit input, 6...Gain control signal, 7...Input resistance, 8...Diode, 9...Amplification Circuit, 10... DC blocking capacitor, 11... DC blocking capacitor, 1
2... Gain control signal input resistance, 13... Detection circuit, 1
4... Integrating circuit, 15... Amplifying circuit, 16... Level limiting circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 制御信号により利得が可変される利得可変増
幅回路と、前記利得可変増幅回路の出力信号を受
けるように接続され予め定められたレベル以上の
信号を制限するレベル制限回路と、前記レベル制
限回路の出力信号を受けるように接続された積分
回路とを有し、前記積分回路の出力信を前記制御
信号として前記利得可変増幅回路へ供給すること
を特徴とするAGC回路。
1. A variable gain amplifier circuit whose gain is varied by a control signal, a level limiting circuit connected to receive the output signal of the variable gain amplifier circuit and limiting signals above a predetermined level, and a level limiting circuit of the level limiting circuit. An AGC circuit comprising: an integrating circuit connected to receive an output signal, and supplying the output signal of the integrating circuit as the control signal to the variable gain amplifier circuit.
JP7642780A 1980-06-06 1980-06-06 Agc circuit Granted JPS573409A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7642780A JPS573409A (en) 1980-06-06 1980-06-06 Agc circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7642780A JPS573409A (en) 1980-06-06 1980-06-06 Agc circuit

Publications (2)

Publication Number Publication Date
JPS573409A JPS573409A (en) 1982-01-08
JPS6218085B2 true JPS6218085B2 (en) 1987-04-21

Family

ID=13604865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7642780A Granted JPS573409A (en) 1980-06-06 1980-06-06 Agc circuit

Country Status (1)

Country Link
JP (1) JPS573409A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6165180A (en) * 1984-09-07 1986-04-03 Tech Res & Dev Inst Of Japan Def Agency Method for compensating gain variation of radar
JP2008161895A (en) * 2006-12-27 2008-07-17 Showa Denko Kk Extrusion method and extrusion device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54151356A (en) * 1978-05-20 1979-11-28 Kopia Kk Automatic gain control amplifier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54151356A (en) * 1978-05-20 1979-11-28 Kopia Kk Automatic gain control amplifier

Also Published As

Publication number Publication date
JPS573409A (en) 1982-01-08

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